KR100940843B1 - Circuit for Generating Column Selecting Signal of Semiconductor Memory Apparatus - Google Patents

Abstract

The present invention discharges the first capacitor during the enable period of the preliminary column select signal, and when the preliminary column select signal is disabled, discharges the second capacitor so that the voltage level of the second capacitor is increased from the discharge point of the second capacitor. The unit delay time is generated as a time until the voltage level of the first capacitor is lowered, and the preliminary column selection signal is delayed by the unit delay time of K (K is a natural number of 2 or more) times in response to a control signal. A variable delay unit generating a column select signal, and a signal combination unit configured to output an enable period of the preliminary column select signal and an enable period of the delay column select signal as an enable period of the column select signal.

Capacitor, Column Selection Signals

Description

Circuit for Generating Column Selecting Signal of Semiconductor Memory Apparatus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a column select signal generation circuit.

The semiconductor memory device is configured to input and output data through the data line. As the number of data lines increases, the semiconductor memory device may input and output many bits of data in one read or write command. However, as the number of data lines increases, the area of the semiconductor memory device becomes large. For example, if eight bits of data are output in one read command, eight data lines are required. However, the area occupied by eight data lines increases the area of the semiconductor memory device.

In order to prevent an increase in the number of data lines, the semiconductor memory device is configured to output four bits of data twice in one read command to four data lines. As a result, the semiconductor memory device configured to output 4-bit data twice in one read command includes a column select signal generation circuit capable of enabling the column select signal twice.

The conventional column select signal generation circuit is configured to delay the first column select signal to generate the second column select signal so that the first column select signal is enabled and the second column select signal can be enabled after a predetermined time. Therefore, the conventional column select signal generation circuit has a delay circuit for delaying the first column select signal. In this case, the delay circuit is generally implemented as a plurality of series connected inverters. The delay circuit composed of an inverter has a disadvantage in that the delay time is changed according to a change in P.V.T (process, voltage, temperature).

As a result, the conventional column select signal generation circuit must secure a time until the first column select signal is enabled and the second column select signal is enabled, but there is a problem in that it cannot be secured constantly according to the P.V.T change.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and a semiconductor memory in which the time until the second column selection signal is enabled after the first column selection signal is enabled regardless of the PVT change can be secured constantly. It is an object of the present invention to provide a column select signal generation circuit of an apparatus.

The column selection signal generation circuit of the semiconductor memory device according to an embodiment of the present invention discharges the first capacitor during the enable period of the preliminary column selection signal, and discharges the second capacitor when the preliminary column selection signal is disabled. The time from the discharge point of the capacitor to the time when the voltage level of the second capacitor becomes lower than the voltage level of the first capacitor is generated as a unit delay time, and K (K is a natural number of 2 or more) times in response to the control signal. A variable delay unit configured to delay the preliminary column selection signal by the unit delay time to generate a delay column selection signal, and an enable period of the preliminary column selection signal and an enable period of the delay column selection signal to the column selection signal. And a signal combination unit for outputting as an enable period.

The column selection signal generation circuit of the semiconductor memory device according to another embodiment of the present invention enables the output signal when the input signal is disabled, and the voltage level of the first capacitor discharged during the enable period of the input signal is the input signal. When the signal is disabled, a plurality of fixed delay units for disabling the output signal are provided in series when the voltage level of the second capacitor discharged is higher, and selectively one of the output signals of each fixed delay unit in response to the plurality of control signals A variable combination section for outputting a signal combination section for outputting an enable section of each of the input signal of the variable delay section and the output signal of the variable delay section as an enable section of the column selection signal, wherein the input signal of the variable delay section is a preliminary Is a column select signal, and the output signal of the variable delay unit Characterized in that the signal obtained by delaying the spare column select signal.

The column selection signal generation circuit of the semiconductor memory device according to the present invention can generate the first and second column selection signals with a constant time difference regardless of the P.V.T change, thereby increasing the operation reliability of the semiconductor memory device.

The column selection signal generation circuit of the semiconductor memory device according to the embodiment of the present invention includes a variable delay unit 100 and a signal combination unit 200 as shown in FIG. 1.

The variable delay unit 100 discharges the first capacitor during the enable period of the preliminary column selection signal Yi_pre and discharges the second capacitor when the preliminary column selection signal Yi_pre is disabled.

In response to the control signal ctrl, the preliminary column selection signal Yi_pre is delayed by a unit delay time of K (K is a natural number of 2 or more) times to generate a delay column selection signal Yi_d. In this case, the unit delay time is a time from the discharge time of the second capacitor to the time when the voltage level of the second capacitor is lower than the voltage level of the first capacitor. For example, the variable delay unit 100 of the column select signal generation circuit of the semiconductor memory device according to an embodiment of the present invention selects the preliminary column by twice the unit delay time when the control signal ctrl is enabled. The signal Yi_pre is delayed and output as the delay column selection signal Yi_d. Meanwhile, when the control signal ctrl is disabled, the variable delay unit 100 delays the preliminary column selection signal Yi_pre by a triple unit delay time and outputs the delayed column selection signal Yi_d as the delay column selection signal Yi_d.

The signal combination unit 200 outputs the sum of the enable period of the preliminary column selection signal Yi_pre and the enable period of the delay column selection signal Yi_d as an enable period of the column selection signal Yi. .

As shown in FIG. 2, the variable delay unit 100 includes a delay signal generator 110 and a selector 120.

The delay signal generation unit 110 generates the first delay signal delay_s1 by delaying the preliminary column selection signal Yi_pre by twice the unit delay time and triples the preliminary column selection signal Yi_pre. The second delay signal delay_s2 is generated by delaying the unit delay time by.

The delay signal generator 110 includes a first fixed delay unit 111, a second fixed delay unit 112, and a third fixed delay unit 113.

The first fixed delay unit 111 generates the preliminary delay signal delay_pre by delaying the preliminary column selection signal Yi_pre by the unit delay time.

The second fixed delay unit 112 generates the first delay signal delay_s1 by delaying the preliminary delay signal delay_pre by the unit delay time.

The third fixed delay unit 113 generates the second delay signal delay2 by delaying the first delay signal delay_s1 by the unit delay time.

Each of the first to third fixed delay units 111 to 113 includes the first and second capacitors, and an input signal (in the case of the first fixed delay unit 111, the preliminary column selection signal Yi_pre), In the case of the second fixed delay unit 112, the first capacitor is discharged during the enable period of the preliminary delay signal delay_pre and in the case of the third fixed delay unit 113, the first delay signal delay_s1. When the input signal is disabled, the second capacitor is discharged. When the input signal is disabled, an output signal (in the case of the first fixed delay unit 111, the preliminary delay signal delay_pre and the second fixed circuit). In the case of the delay unit 112, the first delay signal delay_1 and in the case of the third fixed delay unit 113 enable the second delay signal delay_s2, and the voltage level of the second capacitor is increased. If the voltage level of the first capacitor is lower than Disable the output signal.

As described above, each of the first to third fixed delay units 111 to 113 differs only in the names of the input signal and the output signal, and the configuration thereof is the same. Therefore, the configuration of the first and second fixed delay units 112 and 113 will be replaced by describing the configuration of the first and fixed delay units 111.

As shown in FIG. 3, the first fixed delay unit 111 includes a first charge and discharge unit 111-1, a second charge and discharge unit 111-2, and a signal generator 111-3. do.

When the comparison signal com_s is enabled at the high level, the first charge / discharge unit 111-1 charges the first capacitor C11 and while the preliminary column select signal Yi_pre is enabled at the high level. The first capacitor C11 is discharged. In this case, the voltage of the first capacitor C11 is the first voltage V1.

The first charge / discharge unit 111-1 includes a first inverter IV11, the first capacitor C11, a first resistor element R11, and first to second transistors P11 and N11. The first inverter IV11 receives the comparison signal com_s. The first transistor P11 receives an output signal of the first inverter IV11 to a gate and receives an external voltage VDD to a source. The second transistor N11 receives the preliminary column selection signal Yi_pre at a gate thereof, and a ground terminal VSS is connected to a source thereof. A drain of the first transistor P11 is connected to one end of the first resistor element R11 and a drain of the second transistor N11 is connected to the other end of the first resistor element R11. A drain of the first transistor P11 is connected to one end of the first capacitor C11 and a ground terminal VSS is connected to the other end thereof. In this case, the first voltage V1 is output at the node where the first transistor P11 and the first capacitor C11 are connected. When the first transistor P11 is turned on, a voltage is applied to the first capacitor C11 so that the first transistor P11 is called a charging unit. When the second transistor N11 is turned on, the first capacitor C11 is discharged to refer to the second transistor N11 as a discharge unit.

The second charge / discharge unit 111-2 charges the second capacitor C12 when the preliminary column select signal Yi_pre is enabled at a high level, and the preliminary column select signal Yi_pre is displayed at a low level. When enabled, the second capacitor C12 is discharged. In this case, the voltage of the second capacitor C12 is the second voltage V2.

The second charge / discharge unit 111-2 includes a second inverter IV12, the second capacitor C12, a second resistor element R12, and third to fourth transistors P12 and N12. The second inverter IV12 receives the preliminary column selection signal Yi_pre. The third transistor P12 receives an output signal of the second inverter IV12 to a gate and receives an external voltage VDD to a source. The fourth transistor N12 receives the output signal of the second inverter IV12 at its gate and is connected to the ground terminal VSS at the source. A drain of the third transistor P12 is connected to one end of the second resistor element R12 and a drain of the fourth transistor N12 is connected to the other end thereof. A drain of the third transistor P12 is connected to one end of the second capacitor C12 and a ground terminal VSS is connected to the other end thereof. In this case, the second voltage V2 is output at a node to which the third transistor P12 and the second capacitor C12 are connected. When the third transistor P12 is turned on, the third transistor P12 may be called a charging unit by applying a voltage to the second capacitor C12. When the fourth transistor N12 is turned on, the fourth capacitor N12 may be called a discharge unit by discharging the second capacitor C12.

The signal generator 111-3 enables the comparison signal com_s to a high level when the second voltage V2 is lower than the level of the first voltage V1. The preliminary delay signal delay_pre is enabled when the preliminary column selection signal Yi_pre is disabled at a low level, and the preliminary delay signal delay_pre is enabled when the comparison signal com_s is enabled at a high level. Disable to low level.

The signal generator 111-3 includes a comparator com, a third inverter IV13, and a flip flop FF.

The comparator com compares the level of the first voltage V1 and the second voltage V2 to generate the comparison signal com_s. For example, the comparator com generates the comparison signal com_s disabled to a low level when the second voltage V2 is higher than the level of the first voltage V1. Meanwhile, the comparator com generates the comparison signal com_s enabled to a high level when the second voltage V2 is lower than the level of the first voltage V1.

The third inverter IV13 receives the preliminary column selection signal Yi_pre.

The flip-flop FF receives the output signal of the third inverter IV13 at the input terminal S, receives the comparison signal com at the reset terminal R, and outputs the preliminary delay signal at the output terminal Q. delay_pre). Accordingly, the flip-flop FF outputs the output signal level of the third inverter IV13 as the level of the preliminary delay signal delay_pre when the comparison signal com_s is disabled at the low level. As a result, the flip-flop FF transitions the preliminary delay signal delay_pre to a high level when the preliminary column select signal Yi_pre transitions to a low level when the comparison signal com_s is at a low level. The flip-flop FF initializes the output signal of the flip-flop FF, that is, the preliminary delay signal delay_pre, to a low level when the comparison signal com_s is enabled at a high level.

The selector 120 outputs the first delay signal delay_s1 as the delay column select signal Yi_d when the control signal ctrl is enabled, and when the control signal ctrl is disabled, the selector 120 outputs the first delay signal delay_s1. A two delay signal delay_s2 is output as the delay column select signal Yi_d.

As shown in FIG. 2, the selector 120 includes a first switch 121 and a second switch 122.

When the control signal ctrl is enabled, the first switching unit 121 outputs the first delay signal delay_s1 as the delay column selection signal Yi_d.

The second switching unit 122 outputs the second delay signal delay_s2 as the column selection signal Yi_d when the control signal ctrl is disabled. In this case, the control signal ctrl may be generated using a fuse circuit generally used. When the fuse circuit is used, whether the control signal ctrl is enabled or not depends on cutting of the fuse.

The selector 120 is configured to select and output one of a plurality of signals. In the present invention, the first and second switches 121 and 122 are described as examples, but may be configured as a multiplexer.

The signal combination unit 200 illustrated in FIG. 4 selects the column in a section in which the preliminary column selection signal Yi_pre is enabled at a high level and in a section in which the delay column selection signal Yi_d is enabled at a high level. It outputs as an enable period of signal Yi.

The signal combination unit 200 includes a NOR gate NOR21 and a fourth inverter IV21. The NOR gate NOR21 receives the delay column selection signal Yi_d and the preliminary column selection signal Yi_pre. The fourth inverter IV21 receives the output signal of the NOR gate NOR21 and outputs it as the column select signal Yi.

The column select signal generation circuit of the semiconductor memory device according to the present invention configured as described above operates as follows.

First, the operation of the first fixed delay unit 111 shown in FIG. 3 will be described.

First, the first capacitor C11 is in a charged state, and the second capacitor C12 is in a discharged state.

When the preliminary column select signal Yi_pre is enabled at a high level, the second transistor N11 and the third transistor P12 are turned on. Thus, the first capacitor C11 that has been charged begins to be discharged and the second capacitor C12 is charged.

When the preliminary column select signal Yi_pre is disabled at a low level, the second transistor N11 and the third transistor P12 are turned off, and the fourth transistor N12 is turned on. Therefore, the first capacitor C11 is no longer discharged. Meanwhile, the second capacitor C12 starts to be discharged. That is, the voltage V1 level of the first capacitor C11 does not decrease any more and the voltage V2 level of the second capacitor C12 starts to decrease.

When the voltage V2 level of the second capacitor C12 is higher than the voltage level of the first capacitor C11, the comparison signal com_s disabled to a low level is generated. In addition, when the voltage V2 level of the second capacitor C12 is lower than the voltage level of the first capacitor C11, the comparison signal com_s enabled to the high level is generated. When the preliminary column select signal Yi_pre is disabled, the preliminary delay signal delay_pre is enabled and when the comparison signal com_s is enabled, the preliminary delay signal delay_pre is disabled.

As a result, the first capacitor C11 is discharged during the enable period of the preliminary column selection signal Yi_pre. When the preliminary column selection signal Yi_pre is disabled, the second capacitor C12 is discharged. The preliminary delay signal delay_pre is enabled when the preliminary column select signal Yi is disabled, and the preliminary delay when the voltage level of the second capacitor C12 is lower than the voltage level of the first capacitor C11. Disable the signal delay_pre. More specifically, the second capacitor C12 that discharges when the voltage level of the first capacitor C11 discharged during the enable period of the preliminary column selection signal Yi_pre and the preliminary column selection signal Yi_pre are disabled. By comparing the voltage levels of the plurality of signals, the enable period of the preliminary delay signal delay_pre may be generated in the same manner as the enable period of the preliminary column selection signal Yi_pre. In addition, when the preliminary column select signal Yi_pre is disabled, the preliminary delay signal delay_pre is enabled, so that the preliminary column select signal Yi_pre is delayed by its enable period, and thus the preliminary delay signal delay_pre. Is generated as:

Referring to FIG. 2, second and third fixed delay units 112 and 113 having the same configuration as the first fixed delay unit 111 are illustrated, and the first to third fixed delay units 111 to 118 are illustrated. 113 is connected in series. In this case, the second fixed delay unit 112 generates the first delay signal delay_s1 and the third fixed delay unit 113 generates the second delay signal delay_s2. Therefore, the preliminary column selection signal Yi_pre is delayed by a delay time twice as long as it is enabled and is output as the first delay signal delay_s1. In addition, the preliminary column selection signal Yi_pre is delayed by a delay time three times as long as it is enabled and is output as the second delay signal delay_s2.

Referring to FIG. 5, an enable period of the preliminary column selection signal Yi_pre, that is, a time tPW1 in which the preliminary column selection signal Yi_pre is enabled is referred to as a unit delay time.

The preliminary delay signal delay_pre is generated by delaying the preliminary column selection signal Yi_pre for a unit delay time tPW1.

The first delay signal delay_s1 is generated by delaying the preliminary delay signal delay_pre for a unit delay time tPW1.

The second delay signal delay_s2 is generated by delaying the first delay signal delay_s1 for a unit delay time tPW1.

When the control signal ctrl is enabled, the first delay signal delay_s1 is output as the delay column selection signal Yi_d, so that the first enable timing of the column selection signal Yi and the length of the enable period are the preliminary periods. The length of the enable timing and the enable period of the column select signal Yi_pre is the same, and the length of the second enable timing and the enable period is the same as the enable timing of the first delay signal delay_s1 and the length of the enable period. Do.

When the control signal ctrl is disabled, the second delay signal delay_s2 is output as the delay column selection signal Yi_d. Thus, the first enable timing of the column selection signal Yi and the length of the enable period are The length of the enable timing and the enable period of the preliminary column selection signal Yi_pre is the same as the length of the second enable timing and the enable period, and the length of the enable timing and the enable period of the second delay signal delay_s2. Is the same as

The column selection signal generation circuit of the semiconductor memory device according to the present invention has an effect of increasing the operation reliability of the semiconductor memory device by determining the second enable timing and interval of the column selection signal without being affected by the PVT using the charge and discharge time of the capacitor. have.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram of a column select signal generation circuit of a semiconductor memory device according to an embodiment of the present invention;

2 is a configuration diagram of a variable delay unit of FIG. 1;

3 is a detailed circuit diagram of a first fixed delay unit of FIG. 2;

4 is a circuit diagram of the signal combination unit of FIG. 1;

5 is a timing diagram of a column select signal generation circuit of a semiconductor memory device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: variable delay unit 200: signal combination unit

Claims (16)

The first capacitor is discharged during the enable period of the preliminary column select signal, and when the preliminary column select signal is disabled, the second capacitor is discharged so that the voltage level of the second capacitor is increased from the discharge point of the second capacitor. Delay column selection signal is generated by generating the unit delay time until the time lower than the voltage level, and delaying the preliminary column selection signal by the unit delay time of K (K is a natural number of 2 or more) times in response to a control signal. Variable delay unit for generating a; And And a signal combination unit configured to output an enable period of the preliminary column selection signal and an enable period of the delay column selection signal as an enable period of the column selection signal. The method of claim 1, The variable delay unit When the control signal is enabled, the preliminary column selection signal is delayed by twice the unit delay time to generate the delay column selection signal. And if the control signal is disabled, delaying the preliminary column selection signal by three times the unit delay time to generate the delay column selection signal. The method of claim 2, The variable delay unit Delay signal for generating a first delay signal by delaying the preliminary column selection signal by twice the unit delay time, and generating a second delay signal by delaying the preliminary column selection signal by three times the unit delay time. Generating unit, and And a selector for selectively outputting the first delayed signal or the second delayed signal as the delayed column selection signal in response to the control signal. The method of claim 3, wherein The delay signal generator A first fixed delay unit generating the preliminary delay signal by delaying the preliminary column selection signal by the unit delay time; A second fixed delay unit generating the first delay signal by delaying the preliminary delay signal by the unit delay time, and And a third fixed delay unit configured to delay the first delay signal by the unit delay time to generate the second delay signal. The method of claim 4, wherein Each of the first to third fixed delay units Each having the first capacitor and the second capacitor, Discharging the first capacitor during an enable period of an input signal, discharging the second capacitor when the input signal is disabled, enabling an output signal when the input signal is disabled, and voltage of the second capacitor And disabling the output signal when the level is lower than the voltage level of the first capacitor. The method of claim 5, Each of the first to third fixed delay units A first charging and discharging unit configured to charge the first capacitor and discharge the first capacitor during an enable period of the input signal when the comparison signal is enabled. A second charge / discharge unit configured to charge the second capacitor when the input signal is enabled, and to discharge the second capacitor when the input signal is disabled, Generating the comparison signal by comparing the voltage levels of the first and second capacitors, generating the signal to enable the output signal when the input signal is disabled and to disable the output signal when the comparison signal is enabled And a column select signal generation circuit of the semiconductor memory device. The method of claim 6, The first charge and discharge unit The first capacitor, A charging unit configured to apply an external voltage to the first capacitor when the comparison signal is enabled, and And a discharge unit configured to discharge the first capacitor when the input signal is enabled. The method of claim 7, wherein The second charge and discharge unit The second capacitor, A charging unit configured to apply an external voltage to the first capacitor when the comparison signal is enabled, and And a discharge unit configured to discharge the first capacitor when the input signal is enabled. The method of claim 6, The signal generator A comparator for comparing the voltage levels of the first and second capacitors to produce the comparison signal, An inverter for inverting the level of the input signal, and And a flip-flop for enabling the output signal in response to the inverted input signal and for disabling the output signal when the comparison signal is enabled. The method of claim 1, The signal combination unit A NOR gate receiving the delay column selection signal and the preliminary column selection signal, and And an inverter for inverting the output signal of the NOR gate and outputting the inverted signal as the column selection signal. The output signal is enabled when the input signal is disabled, and the output when the voltage level of the first capacitor discharged during the enable period of the input signal is higher than the voltage level of the second capacitor discharged when the input signal is disabled. A variable delay unit configured to disable a signal and having a plurality of fixed delay units in series, and selectively outputting one of an output signal of each fixed delay unit in response to the plurality of control signals; And And a signal combination unit configured to output an enable period of each of the input signal of the variable delay unit and the output signal of the variable delay unit as an enable period of the column selection signal. And the input signal of the variable delay unit is a preliminary column selection signal, and the output signal of the variable delay unit is a signal obtained by delaying the preliminary column selection signal. The method of claim 11, The fixed delay unit A first charge / discharge unit configured to charge the first capacitor and discharge the first capacitor during an enable period of the input signal when the comparison signal is enabled; A second charging and discharging unit which charges the second capacitor when the input signal is enabled and discharges the second capacitor when the input signal is disabled, and Enable the comparison signal when the voltage level of the first capacitor is higher than the voltage level of the second capacitor; enable the output signal when the input signal is disabled; and output the output signal when the comparison signal is enabled. And a signal generator for disabling the column select signal generation circuit of the semiconductor memory device. The method of claim 12, The first charge and discharge unit The first capacitor, A charging unit for charging the first capacitor when the comparison signal is enabled, and And a discharge unit configured to discharge the first capacitor when the input signal is enabled. The method of claim 12, The second charge and discharge unit The second capacitor, A charging unit for charging the second capacitor when the input signal is enabled, and And a discharge unit configured to discharge the second capacitor when the input signal is disabled. The method of claim 12, The signal generator A comparator comparing the voltage of the first capacitor and the voltage level of the second capacitor to generate the comparison signal; An inverter for inverting the input signal, and And a flip-flop to enable the output signal when the comparison signal is disabled and the inverted input signal is enabled, and to disable the output signal when the comparison signal is enabled. Column selection signal generation circuit. The method of claim 11, The variable delay unit And a plurality of switching elements corresponding to each of the plurality of control signals, and selectively output one of the output signals of the fixed delay units.

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