KR100938620B1 - Method for detecting pixel status of flat panel display and display driver thereof - Google Patents

Abstract

The present invention discloses a method and display driver for pixel state detection of a flat panel display. The method includes providing scan data to a register, using scan data to drive a pixel, detecting a pixel state to obtain state data, refreshing the register with state data, and the pixel is in an abnormal state. Comparing the scan data with the state data to determine whether the recognition. Based on the method described above, the pixel state can be monitored in real time.

Description

Method for detecting pixel status of flat panel display and display driver

The present invention relates to flat panel display technology. More specifically, the present invention relates to a method and a display driver for detecting a pixel state of a flat panel display.

As technology advances, video products, especially digital video / image processing products, have become indispensable in our daily lives. Among digital video / image processing devices, a display device is one of the important devices for displaying related information. The user can read the information from the display to further operate the device. Flat panel displays made of optoelectronic and semiconductor technology, for example a light emitting diode (LED) display, are drawing attention in the field of displays. Because LED displays have the advantages of large size, high quality display, high light emission, and wide viewing angle, LED displays have become a common display of large displays.

The LED display has the following features: When a pixel of an LED display is damaged, the pixel can be repaired by immediately replacing the damaged LED with a new LED. As a result, techniques for detecting the state of LEDs have begun to appear on LED displays. Abnormal states of LEDs in LED display devices include open circuits, short circuits, and high temperatures. In general, the method of detecting the state of the LED can be classified into the following three techniques in the prior art.

1 shows an LED driver according to the prior art for explaining the first technique for detecting the state of the LED in the prior art. In the first technique, as shown in FIG. 1, each driving circuit 103-1 to 103-m connected to the plurality of pixels includes a warning terminal connected to the control unit 101. When one of the pixels is in an abnormal state and an abnormal state is detected by the driving circuits 103-1 to 103-m, a warning signal is received from the warning terminal of the driving circuit connected to the abnormal pixel among the pixels. It is transmitted to the control unit 101. In general, the warning terminals of the driving circuits 103-1 to 103-m are connected together to be connected to the control unit 101 to reduce the number of pins of the control unit 101. However, by doing so, the control unit 101 has difficulty in determining which pixel is abnormal.

In the second technique of the prior art, a detection circuit is added to each driving circuit to detect the state of the pixel and report the state to the controller. The detection circuit of each drive circuit has its own wire assigned to the control unit. Therefore, the second technique increases device cost and design complexity.

The third technique of the prior art uses a mode-switch circuit and two control signals for the drive circuit to switch the drive circuit between the display mode and the non-display mode. This technique is disclosed in US Pat. No. 6,930,679B2. When the drive circuit is in the non-display mode, the serial data line can carry pixel state information. However, using two control signals will increase the complexity of the firmware design, and switching to non-display mode can interfere with the image being displayed. These technologies also do not meet real-time monitor requirements.

It is an object of the present invention to provide a method for providing pixel state detection of a flat panel display.

Another object of the present invention is to provide a display driver for pixel state detection of a flat panel display.

A method and display driver for pixel state detection in a flat panel display device are disclosed herein. According to the invention no mode-switch circuitry is required for pixel state detection. In addition, what is called a real-time monitor is realized because pixel state data is collected without disturbing the pixels while displaying the image. Furthermore, by comparing the scan data with the state data, the position of the abnormal pixel can be represented accurately.

A method for pixel state detection of a flat panel display comprising a display driver having a register for driving a pixel, the method comprising: providing scan data to a register, using the scan data to drive the pixel, and obtaining state data Detecting the pixel state to obtain, refreshing the register with the state data, and comparing the scan data and state data to determine whether the pixel is in an abnormal state.

Another method for pixel state detection of a flat panel display comprising a display driver having n shift registers for driving n pixels, the method further comprises: activating n pixels by the driver; Detecting the state of the n pixels to obtain, refreshing the n shift registers with the n state data, and which of the n pixels is in an abnormal state to the n state data And determining according to the present invention, wherein n is a natural number.

It is still another object of the present invention to provide a display driver for pixel state detection of a flat panel display. The display driver connected to the plurality of pixels of the display includes m driving circuits and a controller.

Each drive circuit of the display driver comprises: a data input terminal; A data output terminal, wherein the data output terminal of the i-th driving circuit comprises: a data output terminal connected to the data input terminal of the (i + 1) th driving circuit; n driving terminals, each of n driving terminals connected to n pixels in the pixels; n shift registers, each shift register comprising an input terminal and an output terminal, wherein the output terminal of the i-th shift register is connected to the input terminal and the i-th driving terminal of the (i + 1) th shift register, M, n, and i are natural numbers and i is n shift registers greater than 0 and less than n; And a detection device including n detection terminals and n output terminals, wherein the detection terminals of the detection device are connected to driving terminals, respectively, and the output terminals of the detection device detect a state of n pixels. It is connected to the shift registers respectively to output status data to the shift registers.

The control unit of the display driver includes a receiving terminal and a scan data terminal, wherein the scan data terminal is connected to a data input terminal of a first driving circuit, and the receiving terminal is an m-th driving circuit for sequentially receiving the status data. And a data input terminal of the first driving circuit sequentially receives the scan data from the scan data terminal of the controller according to a clock signal.

According to the present invention, it is possible to accurately indicate the position of pixels in an abnormal state, a mode switch circuit is not required for pixel state detection, the number of terminals used for pixel state detection can be reduced, a real time monitor and Invisible detection can be realized without any interference to the image being displayed.

BRIEF DESCRIPTION OF DRAWINGS To cover the foregoing and other objects, features, and advantages of the present invention, the preferred embodiments with the accompanying drawings are described in detail below.

Both the foregoing general description and the following description are exemplary and intended to provide a further description of the invention as claimed.

According to the present invention, it is possible to accurately indicate the position of pixels in an abnormal state, a mode switch circuit is not required for pixel state detection, the number of terminals used for pixel state detection can be reduced, a real time monitor and Invisible detection can be realized without any disturbance of the image being displayed.

LED displays have become a common display of large displays because they have the advantages of large size, high quality display, high light emission, and wide viewing angle. In the following, an LED display will be used as an example for explaining an embodiment of the present invention. However, although the pixels of the display are provided with LEDs in the embodiments described below, in other embodiments the pixels may be provided by thin film transistors and liquid crystals, an organic light emitting diode (OLED) or other light emitting device. have.

2 is a structural diagram of a display driver for detecting a LED state according to a first embodiment of the present invention. Referring to FIG. 2, the display driver includes a control unit 201 and m driving circuits 203-1 to 203-m. The m driving circuits 203-1 to 203-m are connected in cascade. If each of the driving circuits 203-1 to 203-m can drive n LEDs, the display driver of FIG. 2 can drive m x n LEDs. Each drive circuit has a data input (DAI) terminal and a data output (DAO) terminal. Shift registers of each of the driving circuits 203-1 to 203-m may shift input data from the data input (DAI) terminal toward the data output (DAO) terminal bit by bit. The data input terminal of the driving circuit 203-1 is connected to the scan data terminal of the controller 201. The scan data transferring the data of the images to be displayed are transmitted from the controller 201 to the driving circuits 203-1 to 203-m through the scan terminal. The data output terminal of the first driving circuit 203-1 is connected to the data input terminal of the second driving circuit 203-2, and the data output terminal of the second driving circuit 203-2 is connected to the third driving circuit ( To a data input terminal (not shown in FIG. 2), which continues in the same manner. The data output terminal of the last driving circuit 203-m is connected to the receiving terminal of the control unit 201. The scan data is continuously transmitted by the controller 201 to the driving circuits 203-1 to 203-m, and one bit of scan data is transmitted every clock CLK.

The detection device for every drive circuit 203-1 to 203-m in FIG. 2 can detect the state of the LED, which is done while these LEDs display an image, for example image #K. When scan data of a new image, for example # K + 1, is transferred from the control unit 201 to the shift registers in the drive circuits 203-1 to 203-m, the control unit may drive the drive circuit to latch the scan data. Transmits the latch enable signal LAT to the latch registers in the fields 203-1 through 203-m, and the drive buffer device in each drive circuit 203-1 through 203-m latches in the latch registers. Drive the LED according to the data. The latch registers include a latch enable terminal. The latch activation terminal receives a latch activation signal LAT, and when the latch activation signal is received, the latch register latches data received from an input terminal of the latch register to an output terminal of the latch register. At the same time the latch activation signal is received by the drive circuits 203-1 to 203-m, the detection device provided for every drive circuit 203-1 to 203-m transmits state data for the LED. Is loaded into the shift registers provided in the driving circuits 203-1 to 203-m. When the next new scan data carrying the data of image # K + 2 has been sent to the drive circuits 203-1 through 203-m, these LED state data are continuously controlled in synchronization with the clock CLK signal to the control unit 201. As a result, the shifted output signal is shifted through the data output DAO terminal of the driving circuits 203-1 to 203-m.

Only when the LED is turned on by the driver can the results of the LED state detection be meaningful. Therefore, the control unit 201 can only determine whether those LEDs turned on are in an abnormal state. The controller 201 may store the LED state data and corresponding scan data in the memory device, and compare the scan data with the state data to pinpoint the exact location of such abnormal LEDs.

If the state of all LEDs is to be detected, the control unit 201 may transmit scan data for transferring the data of the white image to the driving circuits 203-1 to 203-m to turn on all the LEDs. Since the LED state data will be shifted to the controller 201 continuously in synchronization with the clock CLK signal, the controller 201 can count the clock CLK signal to pinpoint the exact location of such an abnormal LED. .

3 is a structural diagram of an internal connection of a driving circuit according to the first embodiment of the present invention, for example, 203-1 of FIG. Referring to FIG. 3, for example, the driving circuit 203-1 for driving n LEDs includes n shift registers 301-1 through 301-n, n latch registers 301-1 through 303-. n), drive buffer device 305, detection device 307, data input (DAI) terminal, data output (DAO) terminal, clock (CLK) input terminal, and latch (LAT) input terminal.

In the n shift registers 301-1 through 301-n, the data output terminal of the i th shift register is connected to the data input terminal of the (i + 1) th shift register, and i is greater than 0 and less than n. Is an integer.

For the n latch registers 303-1 to 303-n, the output terminal of the jth latch register is connected to the drive buffer device 305 to drive the jth LED, and the input terminal of the jth latch register is is coupled to the output terminal of the j th shift register, where j is an integer greater than 0 and less than n.

In the drive buffer device 305, its input terminal is connected to the output terminals of the n latch registers 303-1 to 303-n, and its output terminal is connected to the n LEDs.

In the detection device 307, its input terminal is connected to the LED, and its output terminal is connected to the n shift registers 301-1 to 301-n.

The data input (DAI) terminal of the driving circuit 203-1 is connected to the input terminal of the first shift register 301-1. The data output DAO terminal of the driving circuit 203-1 is connected to the output terminal of the n th shift register 301-n. The clock CLK input terminal provides a clock signal to the driving circuit 203-1. A latch (LAT) input is coupled to the n latch registers 303-1 through 303-n and the detection device 307.

CLK and LAT signals are transmitted from the control unit to the driving circuit 203-1.

The detection device 307 of FIG. 3 can detect the state of the n LEDs 309-1 through 309-n, which is done while these LEDs display an image, for example image #K. When a new image, e.g., scan data of # K + 1, is sent to the shift registers 301-1 through 301-n, the latch (LAT) signal is latch latches 303-1 to latch the scan data. To 303-n, the drive buffer device 305 can drive the LEDs 309-1 to 309-n according to the latched data in the latch registers 303-1 to 303-n. will be. At the same time as the latch signal is received, the detection device 307 will load the state data of the LEDs 309-1 to 309-n into the shift registers 301-1 through 301-n. This LED status data is continuously shifted in synchronization with the clock (CLK) signal via the data output (DAO) terminal when a new image, for example # K + 2 scan data, is shifted through the data input (DAI) terminal. Will be printed.

4 is a diagram illustrating a method for detecting an LED state according to a first embodiment of the present invention. Referring to FIG. 4, first, the controller provides scan data to the shift register (S401). Subsequently, the driving buffer device drives the LED according to the scan data (S403). The detection device detects a state of the LEDs to obtain state data (S405). Next, the detection apparatus refreshes the shift registers with the state data (S407). Finally, the state data is shifted to the control unit, and the control unit may compare the state data and the scan data to determine which LED is in an abnormal state (S409).

The following example is used to explain the configuration of the first embodiment of the present invention. Assume that the control unit 201 transmits n-bit scan data, for example, 01 ... 1, as data of the image #K to the driving circuit (203-1 of FIG. 3). That is, the bits of logic 0 are shifted to the first shift register 301-1, the bits of logic 1 are shifted to the second shift register 301-2, and the bits of logic l are shifted to the nth shift register 301-. shifted to n). When the latch LAT signal is sent to the driving circuit 203-1, the latch registers 303-1 to 303-n latch the scan data of the image #K. The drive buffer device then drives the LEDs 309-1 to 309-n according to the data latched in the latch registers 303-1 to 303-n. In this example, the scan data is n bits (01 ... 1), so the first LED 209-1 is turned off after the scan data is latched by the latch registers 303-1 through 303-n, The second LED 309-2 is turned on and the nth LED 309-n is turned on.

The detection device 307 can detect the state of the LEDs 309-1 to 309-n displaying the image #K here. It should be noted that the results of status detection are meaningful only for those LEDs that are lit. Assume the second LED 309-2 is abnormal. The detection device 307 will find that the second LED 309-2 is abnormal and stores an abnormal status bit, for example a bit of logic 0, in the second bit of the state data. For clarity, the state data corresponding to the state of the LED when displaying image #K is here referred to as state data #K.

When the n bit scan data of the next image, Image # K + 1, is transferred to the shift registers 301-1 through 301-n, the latch LAT signal is transmitted back to the driving device 203-1. When the latch LAT signal is received by the drive device 203-1, the detection device 307 will load the state data #K into the shift registers 301-1 through 301-n. In this example, the second bit of state data #K, which is logic 0, is loaded into the second shift register 301-2. When the next n-bit scan data for image # K + 2 has been transferred to the shift registers 301-1 through 301-n, the status data #K in the shift registers 301-1 through 301-n is controlled. Will be shifted to 201.

The controller 201 may compare the scan data of the state data #K and the image #K to determine which LED is abnormal. Logic 1 bit of the scan data indicates that the corresponding LED is turned on and the result of the status detection of that LED is meaningful. In this example, the second bit of scan data of image #K is logic 1 while the second bit of state data #K is logic zero. Therefore, the control unit 201 recognizes that the second LED 309-2 is abnormal.

From the foregoing, no mode switch circuit and additional control terminals are needed for LED state detection. Since LED status data is collected while the LED displays the image without obstruction, so-called real time monitors are implemented. Further, by comparing the state data and the scan data, the position of the abnormal LED can be pinpointed.

It should be noted that, although the above-described embodiment is a possible structure of the present invention for LED state detection, various modifications and variations are possible to those skilled in the art without departing from the scope or spirit of the present invention. It will be apparent that the structure may be implemented. That is, any invention that refreshes registers with state data and compares state data and scan data to determine whether pixels in a flat panel display are abnormal is within the scope or spirit of the present invention.

In the following, more embodiments will be described, and those skilled in the art can easily construct the present invention.

5 is a structural diagram of a display driver for LED state detection with a smart detection function according to a second embodiment of the present invention. Referring to FIG. 5, the display driver includes a controller 501 and m driving circuits 503-1 to 503-m. The m drive circuits 503-1 to 503-m are cascaded. If each of the driving circuits 503-1 to 503-m can drive n LEDs, the display driver of FIG. 5 can drive m x n LEDs. Each drive circuit 503-1 to 503-m has a data input (DAI) terminal and a data output (DAO) terminal. Shift registers in each of the driving circuits 503-1 to 503-m may shift the input data bit by bit from the data input (DAI) terminal toward the data output (DAO) terminal. The data input terminal of the first driving circuit 503-1 is connected to the scan data terminal of the controller 501. The data output terminal of the first driving circuit 503-1 is connected to the data input terminal of the second driving circuit 503-2, and the data output terminal of the second driving circuit 503-2 is connected to the third driving circuit ( To a data input terminal (not shown in FIG. 3) and continues in the same manner. The data output terminal of the last driving circuit 503-m is connected to the receiving terminal of the control unit 501. Scan data transferring data of the image to be displayed is continuously transmitted by the control unit 501 to the driving circuits 503-1 to 503-m through the scan data terminal, and one bit of the scan data is set every clock ( CLK).

Smart detection (SDT) signals are used in FIG. 5. The smart detection process is initiated when the smart detection (SDT) signal sent by the controller 501 is received by the drive circuits 503-1 to 503-m, and the first latch (LAT) following the smart detection signal. ) Signal ends when it is received by the drive circuits 503-1 through 503-m. The drive buffer devices of the drive circuits 503-1 to 503-m drive and turn on all LEDs when the smart detection (SDT) signal is received by the drive circuits 503-1 to 503-m, and the drive is turned on. The buffer device reduces the brightness of all LEDs as they brighten them all up, so that the human eye cannot detect any disturbances of the images being displayed on the display device and so-called invisible detection is realized when smart detection is in progress. . The detection device in the drive circuits 503-1 to 503-m will detect the state of the LEDs when all the LEDs light up, and the shift registers in the drive circuits 503-1 to 503-m will change the LED state. It will load the state data that carries data for it. The LED state data is shifted in synchronization with the clock CLK signal following the smart detection signal DTT continuously to the control unit 501 through the data output (DAO) terminal of the driving circuits 503-1 to 503-m. Will be printed. Since the state data of the LEDs are continuously shifted to the controller 501 in synchronization with the clock CLK signal, the controller 501 can count the clock CLK signal to pinpoint the exact location of such abnormal LEDs. .

6 is a structural diagram of an internal connection of a driving circuit having a smart detection function according to the second embodiment of the present invention, for example, 503-1 of FIG. Referring to FIG. 6, the driving circuit 503-1, for example, the driving circuit for driving n LEDs includes n shift registers 601-1 through 601-n and n latch registers 601-1 through. 603-n), drive buffer device 605, LED state detection circuit 607, data input (DAI) terminal, data output (DAO) terminal, clock (CLK) input terminal, latch (LAT) input terminal, and smart And a detection (SDT) input terminal.

For n shift registers 601-1 through 601-n, the data output terminal of the i th shift register is connected to the data input terminal of the (i + 1) th shift register, where i is greater than 0 and less than n. Is an integer.

For the n latch registers 603-1 to 603-n, the output terminal of the jth latch register is connected to the drive buffer device 605 to drive the jth LED, and the input terminal of the jth latch register is j And j is an integer greater than 0 and less than n.

For the drive buffer device 605, its input terminals are connected to the output terminals of the n latch registers 603-1 to 603-n, and the output terminals are connected to the n LEDs.

For detection device 607, its input terminals are connected to LEDs, and its output terminals are connected to n shift registers 601-1 to 601-n.

The data input (DAI) terminal of the driving circuit 501-1 is connected to the input terminal of the first shift register 601-1. The data output DAO terminal of the driving circuit 503-1 is connected to the output terminal of the nth shift register 601-n. The clock CLK input terminal provides a clock signal to the driving circuit 503-1. The latch (LAT) input terminal is connected to the n latch registers 603-1 through 603-n. The smart detection (SDT) input terminal is connected to the detection device 607.

CLK, LAT, and SDT signals are transmitted from the control unit to the driving circuit 503-1.

Also in FIG. 6, the smart detection process is initiated when a smart detection (SDT) signal is received by the drive circuit 503-1, and the first latch (LAT) signal is followed by the drive circuit 503-after the smart detection signal. When received by 1). The drive buffer device 605 will drive and turn on all n LEDs 609-1 through 609-n when the smart detection (SDT) signal is received by the drive circuit 503-1. The detection device 607 can directly control the drive buffer device 605 to drive and turn on all the LEDs 609-1 to 609-n, or the detection device 607 can detect all n LEDs. For example, all 1's may be loaded into n shift registers 601-1 through 601-n to control the drive buffer device 605 to drive and turn on 609-1 through 609-n. . When the drive buffer device 605 illuminates the n LEDs 609-1 through 609-n under smart detection, the drive buffer device 605 turns on the brightness of all n LEDs 609-1 through 609-n. Therefore, the human eye does not detect any interference with the images on the display device when smart detection is in progress. The detection device 607 detects the state of the n LEDs 601-1 to 609-n when all n LEDs light up, and n in the n shift registers 601-1 to 601-n. Will load the status data of the two LEDs. The LED state data will be shifted and output following the smart detection (SDT) signal in synchronization with the clock (CLK) signal continuously through the data output (DAO) terminal.

7 is a flowchart illustrating a method for LED state detection with a smart detection function according to a second embodiment of the present invention. Referring to FIG. 7, first, the controller transmits a smart detection signal to a detection device (S701). Subsequently, the detection device controls the driving buffer device to drive and turn on all LEDs (S703). The detection device may detect the states of all the LEDs in order to obtain the state data (S705). Next, the detection device refreshes the shift register with the state data (S707). Finally, the state data is shifted to the control unit, and the control unit may determine which LED is in an abnormal state according to the state data (S709).

8 is a timing diagram of a smart detection process according to the second embodiment of the present invention. Clock CLK, data input DAI, latch LAT, smart detection SDT, and data output DAO signals are shown in a timing diagram. Referring to FIG. 8, a driving circuit capable of driving eight LEDs is used as an example. The smart detection process starts when a smart detection (SDT) signal is received by the drive circuit and ends when the first latch (LAT) signal is received by the drive circuit following the smart detection (SDT) signal.

When the SDT signal is received by the drive circuit, all eight LEDs are turned on and the state of all eight LEDs is detected. The status data of the eight LEDs will then be loaded into eight shift registers for being shifted and output via the DAO signal to the next device, which may be a control or other drive circuit. The DAO signal is synchronized with the rising edge of the clock CLK signal as shown in FIG. If logic "1" indicates a normal LED state and logic "0" indicates an abnormal LED state, the DAO signal of FIG. 8 indicates that the second LED and the fifth LED are abnormal, where the order of the eight LEDs is the driving circuit. The order is from the data input (DAI) terminal to the data output (DAO) terminal.

Although the above embodiment of the present invention uses the LED display as an example, it should be noted that the method and display driver disclosed in the present invention can be applied to any kind of flat panel display.

It will be apparent to those skilled in the art that various modifications and variations can be made in the structure of the present invention without departing from the scope and spirit of the invention. As stated above, the present invention includes modifications and variations of the present invention that result in the scope of the following claims and their equivalents.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of the invention. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

1 is a structural diagram of a traditional display driver for pixel state detection.

2 is a structural diagram of a display driver for detecting a LED state according to a first embodiment of the present invention.

3 is a structural diagram of internal connection of the LED driving circuit according to the first embodiment of the present invention.

4 is a flowchart illustrating a method for LED state detection according to a first embodiment of the present invention.

5 is a structural diagram of a display driver for LED state detection with a smart detection function according to a second embodiment of the present invention.

6 is a structural diagram of an internal connection of an LED driving circuit having a smart detection function according to a second embodiment of the present invention.

7 is a flowchart illustrating a method for LED state detection with a smart detection function according to a second embodiment of the present invention.

8 is a timing diagram of a smart detection process according to a second embodiment of the present invention.

Claims (15)

A method for detecting a pixel state of a flat panel display, the flat panel display comprising a display driver comprising n shift registers, the method for driving a pixel of a flat panel display, Providing scan data to the n shift registers; Inputting the scan data to drive the pixel; Detecting the pixel state to obtain state data; Refreshing the n shift registers with the status data; And Comparing the state data with the scan data to determine whether the pixel is in an abnormal state. The method of claim 1, The n shift registers are for driving n pixels, the n shift registers are connected in series, and each of the shift registers includes a data input terminal, a data output terminal, and a clock terminal, and i th The data output terminal of the shift register is connected to the data input terminal of the (i + 1) th shift register, all clock terminals of the n shift registers receive a clock signal, and the data input terminal of the first shift register is Receiving the scan data; and detecting pixel status of a flat panel display. The method of claim 2, wherein detecting the pixel state to obtain the state data comprises: Detecting an active pixel state among all the n pixels; And and when the kth pixel is in an abnormal state and is detected, storing the abnormal state in the kth bit of the state data, wherein k is a natural number greater than 0 and less than or equal to n. A method for detecting a pixel state of a. The method of claim 3, wherein the refreshing of the n shift registers with the state data comprises: Refreshing a k-th shift register with a k-th bit of the state data. The method of claim 1, And said pixel is a light emitting diode. A method of detecting a pixel state of a flat panel display, the flat panel display comprising n pixels having n shift registers and n latch registers for storing scan data to drive the n pixels. Including a display driver, The method, Activating the n pixels by the driver by inputting scan data into the n pixels; detecting the state of the n pixels to obtain n bits of state data; Refreshing the n shift registers with the n bits of status data; And Determining which of the n pixels is in an abnormal state according to the n bits of state data, wherein n is a natural number. The method of claim 6, Each of the n shift registers includes a data input terminal, a data output terminal, and a clock terminal, wherein the data output terminal of the i th shift register is connected to the data input terminal of the (i + 1) th shift register, A clock signal is received by all the clock terminals of the n shift registers, and the data input terminal of the first shift register sequentially receives n bits of scan data during n-clock cycles. How to detect the pixel state of the. The method of claim 6, wherein detecting the states of the n pixels to obtain the n bits of state data includes: and when the k-th pixel is in an abnormal state and is detected, storing the abnormal state bit in the k-th bit of the n-bit state data, wherein k is a natural number greater than 0 and less than or equal to n. To detect a pixel state of a flat panel display. The method of claim 8, wherein the refreshing of the n shift registers with the n bits of status data comprises: And refreshing a k-th shift register with the k-th bit of the n-bit status data. The method of claim 6, And said n pixels are light emitting diodes. In the display driver connected to a plurality of pixels of the display, the driver, including m driving circuits, Each of the m driving circuits, Data input terminal; A data output terminal, wherein the data output terminal of the i-th driving circuit is connected to the data input terminal of the (i + 1) th driving circuit; n driving terminals, each of n driving terminals connected to n pixels in the plurality of pixels; n shift registers, each of the n shift registers comprising an input terminal and an output terminal, wherein the output terminal of the i th shift register is coupled to an input terminal and an i th driving terminal of the (i + 1) th shift register; N shift registers, wherein m, n, and i are natural numbers and i is greater than 0 and less than or equal to n; And A detection device, comprising n detection terminals and n output terminals, wherein the n detection terminals of the detection device are each connected to the n driving terminals, and the n output terminals of the detection device are the n A detection device connected to the n shift registers, respectively, for detecting a state of the n pixels and outputting n bits of status data to the n shift registers, A control unit, comprising: a receiving terminal and a scan data terminal, wherein the scan data terminal is connected to the data input terminal of a first driving circuit, and the receiving terminal is driving the mth to sequentially receive the n bits of status data. Connected to the data output terminal of the circuit, the data input terminal of the first driving circuit sequentially receives n bits of scan data from the scan data terminal of the controller in accordance with a clock signal, and And the data output terminal comprises a control unit for transmitting the state data to the receiving terminal of the control unit. The method of claim 11, further comprising n latch registers, each of the n latch registers, Latch input terminal; Latch output terminal; And A latch enable terminal, comprising: a latch enable terminal for receiving a latch enable signal, and when the latch enable signal is received, each of the n latch registers latches the data received from the latch input terminal to the latch output terminal. and, The latch output terminal of the j th latch register is coupled to the j th driving terminal, the output terminal of the j th shift register is coupled to the j th driving terminal through the j th latch register, and j is greater than 0 Display driver, characterized in that the natural number less than n. The method of claim 12, A driving buffer coupled between the j th latch register and the j th driving terminal, the j th latch register coupled to the j th driving terminal through the driving buffer, and the j th shift register being j And the j th driving terminal through the first latch register and the driving buffer. The method of claim 11, The detection device receives, from a corresponding pixel, a detection signal that is compared with the n bits of scan data associated with each of the n pixels to output the n bits of status data to the n shift registers, respectively. Including a detection terminal, The n shift registers activate the n pixels by the n bits of scan data, and the detection device detects the n pixels and outputs the n bits of status data to the n shift registers. Display driver, characterized in that. The method of claim 11, And the plurality of pixels are a plurality of light emitting diodes.

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