KR100936790B1 - Semiconductor memory device - Google Patents

Abstract

In the semiconductor memory device of the present invention, in the arrangement design of the highly integrated semiconductor memory device, the memory cell blocks having different sizes share the furnace decoder required for the furnace selection, thereby reducing the layout area and reducing the operating current. It is an object of the present invention to provide a semiconductor memory device that is reduced.

In order to achieve the above object, the present invention provides a plurality of lower unit memory blocks including N unit memory cells, a plurality of unit cells forming one unit memory block, and storing or outputting data according to a row selection signal and a column selection signal. ; A row decoder configured to receive an address signal to generate the row selection signal, and to share the row selection signal to a part of the plurality of lower unit memory blocks in a shared manner; A column decoder for generating the column selection signal; A plurality of pads serving as input / output paths of the address signals, input data, output data, and external control signals; And a controller configured to receive and transmit the address signal through the plurality of pads.

Memory, SDRAM, Banks, Decoders

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}             

1 is a layout view showing a conventional memory block;

2 is a circuit diagram illustrating a raw decoder mounted in a conventional memory block;

3 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention;

4 is a circuit diagram illustrating a furnace decoder mounted in a semiconductor memory device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

310: lower unit memory block 320: to decoder

330: column decoder 340: a plurality of pads

350: control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device in which memory cell blocks having different sizes share a row decoder required for a row selection in an arrangement design of a highly integrated semiconductor memory device.

1 is a layout view of a conventional memory block, which includes a unit memory block 110 composed of M unit memory cells; A row decoder (X-decoder) 120 performing row selection of the unit memory block 110; A column decoder (Y-decoder) 130 for performing column selection of the unit memory block 110; A plurality of pads 140 serving as input / output paths of address signals, input data, and output data for selecting unit memory cells; And a controller 150 that processes the external control signal and the address signal to control the semiconductor device to operate according to a required mode. Here, four unit memory blocks 110 constitute memory banks Bank A, Bank B, Bank C, and Bank D which perform independent data input / output, and four memory banks Bank A, Bank B, Bank C, and Bank D) constitutes one memory chip.

Referring to the operation of the conventional memory block described above, the control signal and the address signal for selecting the unit memory cell required for the operation of the semiconductor device are input from the outside of the semiconductor device through the plurality of pads 140. In addition, according to an operation mode, data to be stored in the unit memory cell is input through the plurality of pads 140 in the read mode, and data of the unit cell is output to the outside through the plurality of pads 140 in the read mode. . At this time, the controller 150 controls the unit memory cell to be in a state capable of storing or outputting data.

FIG. 2 is a circuit diagram illustrating a raw decoder 120 mounted in a conventional memory block. The raw decoder 120 includes a decoder 210 for receiving and decoding an address signal; A driver 220 for driving the output of the decoder 210; And a plurality of signal paths 230 that deliver the output of the driver 220 to the memory block 110.

However, according to the conventional technology described above, since the number of components mounted in the low decoder 120 is considerable, there is a problem that the overall chip size is increased.

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a layout design of a highly integrated semiconductor memory device, in which memory cell blocks having different sizes share a row decoder required for a row selection, thereby reducing layout area and Another object is to provide a semiconductor memory device which reduces the operating current.

In order to achieve the above object, the semiconductor memory device of the present invention is composed of N unit memory cells, and a plurality of units form a unit memory block, and a plurality of units for storing or outputting data according to a row selection signal and a column selection signal. Lower unit memory blocks; A row decoder configured to receive an address signal to generate the row selection signal, and to share the row selection signal to a part of the plurality of lower unit memory blocks in a shared manner; A column decoder for generating the column selection signal; A plurality of pads serving as input / output paths of the address signals, input data, output data, and external control signals; And a control unit configured to receive and transmit the address signal through the plurality of pads.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

First, FIG. 3 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention. The semiconductor memory device of the present invention may include a lower unit memory block 310, a low decoder (X-decoder) 320, And a column decoder (Y-decoder) 330, a plurality of pads 340, and a controller 350.

The plurality of lower unit memory blocks 310 may be configured of N unit memory cells, and the plurality of lower unit memory blocks 310 may form a unit memory block, and may store or output data according to a row selection signal and a column selection signal. Here, according to the embodiment of FIG. 3, N = 0.25 × M (M: number of unit memory cells included in a conventional unit memory block), and the lower unit memory block 310 includes five unit memory units. A block is composed of six or a unit memory block. In addition, these unit memory blocks gather to form memory banks Bank A, Bank B, Bank C, and Bank D, and four memory banks Bank A, Bank B, Bank C, and Bank D form one memory chip. Configure. As shown in FIG. 3, when the memory density is 512 Mbit, M = 32 Mbit, and one memory bank is composed of 128 Mbit.

In addition, the row decoder (X-decoder) 320 receives the address signal, generates the row selection signal for performing the row selection of the lower unit memory block 310, and transmits the row selection signal to the plurality of lower levels. Some of the unit memory blocks 310 are shared.

The column decoder (Y-decoder) 330 may receive the address signal and generate the column selection signal for performing column selection of the lower unit memory block 310.

In addition, the plurality of pads 340 serve as input / output paths of the address signals, input data, output data, and external control signals for selecting unit memory cells.

The controller 350 receives the external control signal and the address signal through the plurality of pads 340, controls the semiconductor device to operate according to a required mode according to the external control signal, and controls the address signal. To output the raw decoder (X-decoder) 320 and the column decoder (Y-decoder) 330.

FIG. 4 is a circuit diagram illustrating a raw decoder (X-decoder) 320 mounted in a semiconductor memory device according to an embodiment of the present invention.

The decoder 410 receives the address signal and decodes the same through a logical operation.

The driver 420 also drives the output of the decoder 410.                     

Meanwhile, the plurality of shared signal paths 430 simultaneously transmits outputs of the driver 420 to a plurality of unit memory blocks.

In addition, the plurality of signal paths 440 transfers the output of the driver 420 to the unit memory block.

The operation of the semiconductor memory device of the present invention described above is as follows.

First, an address signal for selecting a control signal and a unit memory cell required for the operation of the semiconductor device are input from the outside of the semiconductor device through the plurality of pads 340. In this case, in the case of the SDRAM, some pads of the plurality of pads 340 may be used for power, control signal and address signal input only, and the other pads may be used as power and data input / output pads.

In addition, according to an operation mode, data to be stored in a unit memory cell is input through a plurality of pads 340 in a read mode, and data of a unit cell is output to the outside through a plurality of pads 340 in a read mode. .

In this case, the controller 350 controls the unit memory cell to be in a state capable of storing or outputting data, and the controller 350 also controls the raw decoder (X-decoder) 320. In this case, the driver 420 mounted in the raw decoder 320 is shared by the plurality of unit memory blocks at the same time through the plurality of shared signal paths 430.                     

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited to the drawings shown.

According to the present invention, in the arrangement design of a highly integrated semiconductor memory device, the memory cell blocks having different sizes share the furnace decoder required for the furnace selection, thereby reducing the layout area and reducing the operating current. .

Claims (3)

A plurality of lower unit memory blocks including N unit memory cells, a plurality of unit cells forming one unit memory block, and storing or outputting data according to a row selection signal and a column selection signal; Generating the row selection signal by receiving an address signal and sharing the row selection signal to a row decoder to share the row selection signal to some of the plurality of sub-unit memory blocks. Means that the same furnace selection signal is transmitted to different memory blocks; A column decoder for generating the column selection signal; A plurality of pads serving as input / output paths of the address signals, input data, output data, and external control signals; And Control unit for receiving and transmitting the address signal through the plurality of pads A semiconductor memory device comprising a. The method of claim 1, In a memory bank including a plurality of unit memory blocks, the number of the lower unit memory blocks included in the unit memory block is different for each unit memory block. A semiconductor memory device, characterized in that. The method of claim 1, wherein the raw decoder, A decoder which receives and decodes the address signal; A driver to drive the output of the decoder A plurality of shared signal paths for simultaneously delivering outputs of the driver to the plurality of lower unit memory blocks; And A plurality of signal paths to deliver the output of the driver to the unit memory block A semiconductor memory device comprising a.

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