KR100933684B1 - Semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a SERDES method of a semiconductor device in which an operation speed changes according to an external clock frequency, wherein the second pulse is activated in response to activation of a first pulse corresponding to a column command. An activation time controller for controlling the activation time of the second pulse in response to a value (CL). An activation section changer for varying an activation section of the first and second pulses in response to the cas latency (CL) value, and data corresponding to a plurality of first data lines; Provided is a semiconductor device including a data transfer unit for dividing a predetermined number in an activation period into a plurality of second data lines, which are smaller than the plurality of first data lines.

SERDES method, CAS latency, activation time, activation interval

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to semiconductor design technology, and more particularly, to a suder (SERializer / DESerializer: SERDES) method of a semiconductor device. SERDES) method.

In general, the term "serializer / deserializer" means converting serialized data into serialized data and outputting the serialized data and converting the serialized data into parallelized data.

That is, the SERDES method refers to a method of dividing a predetermined number by serially outputting a plurality of pieces of data in parallel, or when a plurality of pieces of data are serially inputted by a predetermined number. It means a method of collecting a plurality of input data and outputting in parallel.

For example, the SERDES method is a method in which a plurality of data in parallel is inputted once and then divided into four pieces and outputted in series. When eight pieces of data in parallel are eight, eight data are divided by four. Will output twice in series.

On the contrary, if the SERDES method is a method in which a plurality of pieces of data are inputted twice in series by a predetermined number and outputted in parallel, four pieces of serial data inputted at one time are four. It receives 8 data twice and outputs 8 data collected in parallel.

In order to perform the above-described operation, the apparatus using the actual SERDES scheme generates a input enable signal and an output enable signal and uses a method of arranging the relationship between the input data and the output data.

That is, in the case of the SERDES method of converting the parallelized data and outputting the serialized data, the output enable signal is toggled many times when the input enable signal toggles once. .

For example, the SERDES method is a method in which a plurality of data in parallel is inputted once and then divided into four and output in series. Eight inputs in parallel in response to toggling of the input enable signal once Eight data are input at once, and eight data are output twice in series in response to two toggles of the output enable signal.

On the contrary, in the case of the SERDES method of converting serialized data and outputting the parallelized data, the output enable signal is toggled once when the input enable signal is toggled many times. do.

For example, if the SERDES method is a method in which a plurality of serial data are inputted twice and outputted in parallel, four data are generated in response to the input enable signal toggling twice. A total of eight data inputs, two inputs of four times, are output at once in parallel in response to the output enable signal toggling once.

FIG. 1 is a block diagram illustrating a configuration of a semiconductor device using a SUDES method.

First, the diagram shown in FIG. 1 is an input / output sense amplifier (IOSA) in which a SERDES method is used among the components of a DDR3 SDRAM (Double Date Rate 3 Synchronous Dynamic Random Access Memory). And a block diagram illustrating a pipeline circuit (PIPE LINE CIRCUIT).

Specifically, the input / output sense amplification circuit IOSA includes eight local data L_DATA0, L_DATA1, L_DATA2, which are loaded on eight local input / output lines LIO0, LIO1, LIO2, LIO3, LIO4, LIO5, LIO6, LIO7. The L_DATA3, L_DATA4, L_DATA5, L_DATA6, and L_DATA7 are divided into four and loaded into four global input / output lines GIO0, GIO1, GIO2, and GIO3 as global data (G_DATA0, G_DATA1, G_DATA2, and G_DATA3).

At this time, eight local input / output lines (LIO0, LIO1, LIO2, LIO3, LIO4, LIO5, LIO6, LIO7) include eight local data (L_DATA0, L_DATA1, L_DATA2, L_DATA3, L_DATA4, L_DATA5, L_DATA6, L_DATA7). In response to the column command YEN, which is an input enable signal, toggling, the input / output sense amplification circuit IOSA is reached. At the same time, the SERDES circuit 100A receives the column command YEN, which is an input enable signal. In response to toggling), the first enable pulse EN1 and the second pulse EN2, which are output enable signals, are generated at predetermined time intervals.

Due to the operation of the SERDES circuit 100A, the input / output sense amplifier circuit (IOSA) allows four of eight local input / output lines (LIO0, LIO1, LIO2, LIO3, LIO4, LIO5, LIO6, LIO7). Four local input / output lines (LIO0, LIO1, LIO2, LIO3) loaded on four local data (L_DATA0, L_DATA1, L_DATA2, L_DATA3) in response to the first pulse (EN1), four global input / output lines (GIO0, Load the GIO1, GIO2, GIO3 as global data (G_DATA0, G_DATA1, G_DATA2, G_DATA3), and load the four local data (L_DATA4, L_DATA5, L_DATA6) on the remaining four local input / output lines (LIO4, LIO5, LIO6, LIO7). , L_DATA7 is loaded on the four global input / output lines GIO0, GIO1, GIO2, and GIO3 as global data G_DATA0, G_DATA1, G_DATA2, and G_DATA3 in response to the second pulse EN2.

As such, when the plurality of data formed in parallel are inputted to the input / output sense amplification circuit (IOSA), the SUDES circuit 100A may be output in series at a predetermined time interval by dividing the plurality of data by a predetermined number. It acts as a generator of pulses that can be controlled.

In addition, the pipeline circuit (PIPE LINE CIRCUIT) receives four global data (G_DATA0, G_DATA1, G_DATA2, G_DATA3) twice in succession from four global input / output lines (GIO0, GIO1, GIO2, GIO3). Eight pipe data (P_DATA0, P_DATA1, P_DATA2, P_DATA3, P_DATA4, P_DATA5, P_DATA6, and P_DATA7) are loaded into eight pipelines (P_LINE0, P_LINE1, P_LINE2, P_LINE3, P_LINE4, P_LINE5, P_LINE6, and P_LINE7).

At this time, the four global data (G_DATA0, G_DATA1, G_DATA2, G_DATA3) on the four global input / output lines (GIO0, GIO1, GIO2, GIO3) are toggling the input control signal (PEN), which is an input enable signal. Correspondingly, the pipeline circuit (PIPE LINE CIRCUIT) is reached, and at the same time, in the SERDES circuit (100B), the input control signal (PEN), which is an input enable signal, is another input enable signal. The transmission control signal PINSTB is controlled to toggle continuously at a predetermined time interval. That is, the first pulse section and the second pulse section are generated in the transmission control signal PINSTB.

Due to the operation of the SERDES circuit 100B, in the pipeline circuit PIPE CIRCUIT, four global input / output lines GIO0, GIO1, GIO2, and GIO3 in the first pulse section of the transmission control signal PINSTB. The first four global data (G_DATA0, G_DATA1, G_DATA2, G_DATA3), which are included in the), are received, and four global input / output lines (GIO0, GIO1, 4) in the second pulse section of the transmission control signal (PINSTB) after a predetermined time interval. The second four global data (G_DATA0, G_DATA1, G_DATA2, G_DATA3) in GIO2, GIO3) are received.

In addition, the pulse output unit 120 may include a first storage control pulse PIN <0> corresponding to the first pulse section of the transmission control signal PINSTB and a second pulse section corresponding to the second pulse section of the transmission control signal PINSTB. A storage control pulse (PIN <1>) is generated, and the first storage control pulse (PIN <0>) is the first applied to the pipeline circuit (PIPE LINE CIRCUIT) in the first pulse section of the transmission control signal (PINSTB). The fourth four global data G_DATA0, G_DATA1, G_DATA2, and G_DATA3 are stored in the first storage space P_LATCH1, and the second storage control pulse PIN <1> is the second pulse of the transmission control signal PINSTB. The second four global data G_DATA0, G_DATA1, G_DATA2, and G_DATA3 applied to the pipeline circuit PIPE LINE CIRCUIT in the section are stored in the second storage space P_LATCH2.

In this manner, eight global data stored in the first and second storage spaces P_LATCH1 and P_LATCH2 are output to eight pipelines P_LINE0, P_LINE1, P_LINE2, in response to the output control signal POUT, which is an output enable signal, toggles. P_LINE3, P_LINE4, P_LINE5, P_LINE6, and P_LINE7 are loaded as eight pipe data (P_DATA0, P_DATA1, P_DATA2, P_DATA3, P_DATA4, P_DATA5, P_DATA6, and P_DATA7).

As such, when the plurality of data is input to the pipeline circuit PIPE LINE CIRCUIT in series by a predetermined number, the SERDES circuit 100B may be applied in a predetermined number and stored in an independent space. It plays the role of generating the controlling pulse.

FIG. 2 is a circuit diagram illustrating in detail a SERDES circuit according to the related art among components of a semiconductor device using the SERDES method illustrated in FIG. 1.

Referring to FIG. 2, of the components of a semiconductor device using a SERDES method, the <SERDES circuit used in an input / output sense amplification circuit (IOSA) according to the related art is a column command ( In response to the activation of the first pulse EN1 corresponding to YEN, the second pulse EN2 is activated, and at the scheduled time of the activation time of the first pulse EN1 and the activation time of the second pulse EN2, And a pulse activator 200 having a delay delay interval, and an activation interval extension portion 220 for extending the activation interval of the first pulse EN1 and the second pulse EN2 by a predetermined time Delay2. .

In addition, among the components of the semiconductor device using the SERDES method, the <SERDES circuit used in the PIPE LINE CIRCUIT> according to the prior art corresponds to the input control signal PEN. The second pulse section of the transmission control signal PINSTB is generated in response to the first pulse section of the transmitted control signal PINSTB, and the time point and the second pulse section of the transmission control signal PINSTB are generated. Extending the pulse width of the pulse generator 210 and the first pulse section and the second pulse section of the transmission control signal PINSTB so that the generated time point has a predetermined time Delay1 interval by the predetermined time Delay2. It has a pulse width extension 230 for.

For reference, referring only to FIG. 1, among the components of a semiconductor device using a SERDES method, a <SERDES circuit used in an input / output sensing amplification circuit (IOSA) according to the related art and the related art <SERDES circuit used for PIPE LINE CIRCUIT> should have a different configuration. In other words, the two signals EN1 and EN2 are output from the SERDES circuit used for the input / output sense amplification circuit IOSA, whereas the signal used for the pipe line circuit is used. In the case of the SERDES circuit, there is a difference in that one signal PINSTB is output, and thus its configuration also needs to be changed. However, referring to FIG. 2, <SERDES circuit used for input / output sense amplification circuit (IOSA)> and <SERDES circuit used for pipe line circuit (PIPE LINE CIRCUIT)> It can be seen that it has the same circuit.

FIG. 3 is a timing diagram illustrating an operation waveform of a SERDES circuit according to the related art among components of a semiconductor device using the SERDES method illustrated in FIG. 2.

First, referring to FIG. 3, an operating waveform of a <SERDES circuit used in an input / output sense amplification circuit (IOSA)> according to the prior art among components of a semiconductor device using a SERDES method is described. In operation, the first pulse EN1 is activated in response to the activation of the column command YEN. At this time, the input / output sense amplification circuit (IOSA) has four local data (L_DATA <of eight local data (L_DATA <0: 7>) included in eight local input / output lines (LIO <0: 7>). 0: 3>) are loaded into four global input / output lines GIO <0: 3> as global data G_DATA <0: 3>.

In addition, when a predetermined time Delay1 passes after the column command YEN is activated, the second column command YEN2 is activated, and in response to the activation of the second column command YEN2, the second pulse EN2 is activated. Is activated. At this time, the input / output sense amplification circuit (IOSA) has the remaining four local data (L_DATA) among the eight local data (L_DATA <0: 7>) contained in the eight local input / output lines (LIO <0: 7>). <4: 7> is loaded into four global input / output lines GIO <0: 3> as global data G_DATA <0: 3>.

When the predetermined time Delay2 passes after the column command YEN is deactivated, the first pulse EN1 is deactivated, and when the predetermined time Delay2 passes after the second column command YEN2 deactivates, the second pulse As the EN2) is deactivated, the first pulse EN1 and the second pulse EN2 have a longer activation period than the column command YEN and the second column command YEN2, respectively, which is an input / output sense amplification. The time when the circuit IOSA is operating, that is, the local data L_DATA <0: 7> contained in the local input / output lines LIO <0: 7> is the global input / output line GIO <0: 3>. This is to ensure sufficient time required to be loaded as global data (G_DATA <0: 3>).

That is, the operation of generating the first pulse EN1 and the second pulse EN2 during the operation of the SUDES circuit used in the input / output sense amplification circuit IOSA is performed in parallel with the local data L_DATA. <0: 7>) is for converting the serial global data G_DATA <0: 3>, and extending the activation period of the first pulse EN1 and the second pulse EN2 is necessary for data transmission. It is to secure time.

Referring to FIG. 3, an operation waveform of a <SERDES circuit used for a pipe line circuit> according to the prior art among components of a semiconductor device using a SERDES method will be described. In response to the activation of the input control signal PEN, the first pulse section ① of the transmission control signal PINSTB is started. At this time, the pipeline circuit PIPE LINE CIRCUIT stores four global data G_DATA <0: 3> in four global input / output lines GIO <0: 3> in the first storage space P_LATCH1. Stored as pipe data P_DATA <0: 3>.

In addition, when a predetermined time Delay1 passes after the input control signal PEN is activated, the second input control signal PEN2 is activated, and in response to the activation of the second input control signal PEN2, the transmission control signal PINSTB is activated. The second pulse section (2) of) starts. At this time, the pipeline circuit PILINE CIRCUIT stores four global data G_DATA <0: 3> stored in four global input / output lines GIO <0: 3> in the second storage space P_LATCH2. Stored as pipe data (P_DATA <4: 7>).

After the input control signal PEN is deactivated and the predetermined time Delay2 passes, the first pulse section ① of the transmission control signal PINSTB ends, and the second input control signal PEN2 is deactivated and scheduled time. After (Delay2) flows, the second pulse section (②) of the transmission control signal (PINSTB) ends, whereby the first pulse section (①) and the second pulse section (②) of the transmission control signal (PINSTB) are respectively controlled. It has a longer pulse activation time than the signal PEN and the second input control signal PEN2, which is the time that the pipeline circuit PIPE CIRCUIT operates, that is, the global input / output line GIO <0: This is to ensure sufficient time required for the global data G_DATA <0: 3> listed in 3>) to be stored in the predetermined storage spaces P_LATCH1 and P_LATCH2 in the pipeline circuit PIPE LINE CIRCUIT.

That is, the first pulse section ① and the second pulse section ② of the transmission control signal PINSTB are generated during the operation of the <SERDES circuit used for the PIPE LINE CIRCUIT>. The operation is for controlling an operation of storing a plurality of serially inputted global data G_DATA <0: 3> in the predetermined storage spaces P_LATCH1 and P_LATCH2, respectively, and the first pulse section of the transmission control signal PINSTB ( The operation of extending the pulse activation time of ①) and the second pulse section ② is a time required for storing a plurality of serially inputted global data G_DATA <0: 3> in the predetermined storage spaces P_LATCH1 and P_LATCH2, respectively. To secure.

At this time, in the above-described <SERDES circuit used for the input / output sense amplifier circuit IOSA>, the first pulse EN1 and the column command YEN that correspond directly to the column command YEN are directly. The first delay element Delay1 having a fixed value is used as to how many time intervals the uncorresponding second pulses EN1 and EN2 have. In addition, a second delay element Delay2 having a fixed value is used for how many activation periods the first pulse EN1 and the second pulse EN2 have.

Similarly, the <SERDES circuit used for the PIPE LINE CIRCUIT> also includes the first pulse section and the input control signal PEN of the transmission control signal PINSTB directly corresponding to the input control signal PEN. The first delay element Delay1 having a fixed value is used as to how much time interval the second pulse section of the transmission control signal PINSTB does not directly correspond to. Also, a second delay element Delay2 having a fixed value is used for how long the pulse activation time of the first pulse section and the second pulse section of the transmission control signal PINSTB is maintained.

Here, the delay value of the first delay element Delay1 and the second delay element Delay2 is fixed to a value set at the time of design, but does not mean that the semiconductor device has a constant value regardless of any semiconductor device.

That is, in the conventional semiconductor device using the SERDES method, the first delay device Delay1 and the second delay device Delay2 directly related to the operation of the SERDES circuit according to the operating speed of the semiconductor device. By setting a delay value of), a SERDES circuit capable of performing the above-described operation regardless of the type of semiconductor device is implemented.

For example, a relatively fast operation speed of a semiconductor device means that a frequency of a clock applied from the outside is relatively high, which means that a data input / output speed is fast, and thus a semiconductor device. When the operation speed of R is relatively fast, the SERDES circuit capable of performing the above-described operation may be implemented by relatively decreasing the delay values of the first delay element Delay1 and the second delay element Delay2. .

On the contrary, the relatively slow operation speed of the semiconductor device means that the frequency of the clock applied from the outside is relatively low, which means that the input / output speed of the data is slow. When R is relatively slow, the SERDES circuit capable of performing the above-described operation may be implemented by relatively increasing the delay values of the first delay element Delay1 and the second delay element Delay2.

However, when the delay values of the first delay element Delay1 and the second delay element Delay2 are set based on the operation speed of the semiconductor element as described above, the same semiconductor element is used by varying the operation speed according to the option. In this case, at the operating speed used as a reference, a SERDES circuit capable of performing the above-described operation correctly may be implemented, but at the operating speed not used as a reference, the suede may not be performed correctly. There is a problem that the (SERDES) circuit is implemented.

In fact, DDR3 SDRAMs can operate at 1.066Ghz depending on options, but can also operate at 1.333Ghz. Therefore, if the delay values of the first delay element Delay1 and the second delay element Delay2 are set in the SERDES circuit based on when the DDR3 SDRAM operates at 1.333Ghz, the option is changed to the DDR3 SDRAM. When operating at 1.066 Ghz, the time for transmitting data input / output through the operation of the SERDES circuit, for example, the global line GIO <0: 3 on the local line LIO <0: 7> The transfer time to>) may be insufficient, which may cause data to not be input / output normally in DDR3 SDRAM.

In the opposite case, if the delay values of the first delay element Delay1 and the second delay element Delay2 are set in the SERDES circuit based on when the DDR3 SDRAM operates at 1.066 Ghz, the option is changed. When the DDR3 SDRAM is operating at 1.333Ghz, the time for transferring data input / output through the operation of the SERDES circuit, for example, in the global line GIO <0: 3>, the pipeline P_LINE < 0: 7>) provides more time than necessary to transfer, which can cause data to not be input / output normally in DDR3 SDRAM.

The present invention has been proposed to solve the problems of the prior art as described above, in a semiconductor device using the Serdes method, the sustain speed is changed according to the frequency of the external clock input to the semiconductor device (SERDES) Circuit-When the output (input) interval and output (input) interval of serialized data is long when converting the parallelized (serialized) data to serialized (parallelized) data based on the SERDES circuit. The operating speed of the SERDES circuit is slow, and the output (input) interval of the serialized data when converting the parallelized (serialized) data into the serialized (parallelized) data based on the SERDES circuit. And a short output (input) section means that the operation speed of the SERDES circuit is high.

According to an aspect of the present invention for achieving the above object, to activate the second pulse in response to the activation of the first pulse corresponding to the column command, in response to the cas latency (CL) value Activation time control means for controlling the activation time of two pulses; Activation period changing means for varying activation periods of the first and second pulses in response to the cas latency CL value; And dividing data corresponding to the plurality of first data lines by a predetermined number in the activation period of each of the first and second pulses and loading the plurality of second data lines, which are smaller than the plurality of first data lines. Provided is a semiconductor device having data transmission means for the same.

According to another aspect of the present invention for achieving the above object, to activate the second pulse in response to the first pulse corresponding to the column command is activated, in response to the cas latency (CL) value Activation time control means for controlling the activation time of two pulses; Activation period changing means for varying activation periods of the first and second pulses in response to the cas latency CL value; And storing data corresponding to a plurality of first data lines in different predetermined spaces in respective activation sections of each of the first and second pulses, and simultaneously storing the stored data in a plurality of second data lines-the plurality of first data. Provided is a semiconductor device having data transmission means for mounting on a larger number than a line.

According to another aspect of the present invention for achieving the above object, generating a second pulse section of the transmission control signal in response to the first pulse section of the transmission control signal corresponding to the input control signal, Generation time control means for controlling a time point at which a second pulse section of the transmission control signal is generated in response to a latency CL value; Activation time changing means for varying a pulse activation time corresponding to the first and second pulse sections in accordance with the cas latency (CL) value; And dividing data corresponding to the plurality of first data lines by a predetermined number in the first and second pulse sections, respectively, to load the plurality of second data lines, which are smaller than the plurality of first data lines. Provided is a semiconductor device having a transmission means.

According to another aspect of the present invention for achieving the above object, generating a second pulse section of the transmission control signal in response to the first pulse section of the transmission control signal corresponding to the input control signal, Generation time control means for controlling a time point at which a second pulse section of the transmission control signal is generated in response to a cas latency (CL) value; Activation time changing means for varying a pulse activation time corresponding to the first and second pulse sections in accordance with the cas latency (CL) value; And storing data corresponding to the plurality of first data lines in different predetermined spaces in the first and second pulse sections, respectively, and storing the stored data simultaneously in the plurality of second data lines-more than the plurality of first data lines. It provides a semiconductor device having a data transmission means for loading the number.

According to the present invention, a semiconductor device using a SERDES method includes a sustained signal whose operating speed changes by using a cascade latency (CL) value whose value changes according to the frequency of an external clock input to the semiconductor device. SERDES) circuit can be implemented.

As a result, even when the operation speed of the semiconductor device changes, a data input / output error occurs because the data input / output operation can be performed with a sufficient margin by performing a stable SUDES operation. There is an effect that can be prevented.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.

FIG. 4 is a circuit diagram illustrating in detail a SERDES circuit according to an exemplary embodiment of the present invention among components of a semiconductor device using the SERDES method illustrated in FIG. 1.

Referring to FIG. 4, among the components of a semiconductor device using a SERDES method, the <SERDES circuit used in an input / output sense amplification circuit (IOSA) according to an embodiment of the present invention may be described as follows. In response to the activation of the first pulse EN1 corresponding to the column command YEN, the second pulse EN2 is activated, but in response to the cas latency values CL7, CEN9 and CEN11, the second pulse EN2 is activated. Activation section variation for activating the activation section of the first pulse (EN1) and the second pulse (EN2) in response to the activation time control unit 400 for controlling the activation time, and the cascade latency (CL7, CEN9, CEN11) The unit 420 is provided.

Here, the activation point control unit 400 is configured to activate the first pulse EN1 for activating the first pulse EN1 in response to the activation point of the column command YEN, and at the activation point of the column command YEN. A second pulse activator 404 is provided for activating the second pulse EN2 at a time delayed by the first time Delay1 corresponding to the CAS latency CL7, CEN9, CEN11.

In addition, the second pulse activator 404 of the components of the activation time controller 400 has a predetermined delay amount, respectively, in a chain form to delay the column command YEN and output the second pulse EN2 as a delay. A plurality of delay units 404A, 404B, 404C, and 404D are controlled on / off in response to the connected multiple delay units 404A, 404B, 404C, and 404D and the cascade latency CL7, CEN9, and CEN11 values. Delay unit 404E, 404F, 404G for varying the total delay amount of delay units 404A, 404B, 404C, and 404D.

4 does not include any components in the first pulse activator 402. That is, a method of receiving the column command YEN and outputting the same as it is, in which case the first pulse EN1 is activated before the second pulse EN2 in any case in preparation for the configuration of the second pulse activation unit 404. In order to express the fact that it is, it may actually include a configuration such as a repeater.

In addition, the activation section changing unit 420 sets the activation section length of the first pulse EN1 corresponding to the activation section length of the column command YEN to the second time Delay2 corresponding to the cas latency CEN9 and CEN11 values. Corresponds to the cas latency (CEN9, CEN11) values of the activation period length of the second pulse EN2 corresponding to the activation period length of the column command (YEN) And a second pulse activation section changer 424 for extending by a second time Delay2.

The first pulse activation section changing section 422 among the components of the activation point changing section 420 has a predetermined delay amount and has an activation section length corresponding to the activation section length of the column command YEN. Delays corresponding to the values of cascade latency CEN9 and CEN11 and a plurality of delay units 422A, 422B and 422C connected in a chain form to delay one pulse EN1 and output it as the section control pulse CON_PUL1. Delay amount changing sections 422D and 422E for changing the total delay amount of the plurality of delay sections 422A, 422B and 422C by turning on / off the sections 422A, 422B and 422C, and the column command YEN. A first pulse EN1 having an activation period longer than the activation period length of the column command YEN by receiving the first pulse EN1 and the section control pulse CON_PUL1 having an activation period length corresponding to the activation period length of And a first pulse output unit 422F for outputting the signal.

The second pulse activation section changing section 424, among the components of the activation point changing section 420, has a predetermined delay amount and has an activation section length corresponding to the activation section length of the column command YEN. Delays corresponding to the values of the cascade latency CEN9 and CEN11 and the plurality of delay units 424A, 424B and 424C connected in a chain form to delay two pulses EN2 and output them as the section control pulse CON_PUL2. Delay amount changing sections 424D, 424E, and column command YEN for varying the total delay amount of the plurality of delay sections 424A, 424B, 424C by turning on / off the sections 424A, 424B, 424C. A second pulse EN2 having an activation section longer than the activation section length of the column command YEN by receiving the second pulse EN2 and the section control pulse CON_PUL2 having an activation section length corresponding to the activation section length of And a second pulse output unit 424F for outputting the signal.

The <SERDES circuit used for the PIPE LINE CIRCUIT> according to the embodiment of the present invention among the components of the semiconductor device using the SERDES method is an input control signal PEN. Generates a second pulse section of the transmission control signal PINSTB in response to the first pulse section of the transmission control signal PINSTB corresponding to the &lt; Desc / Clms Page number 11 &gt;), but responds to the cascade latency CL7, CEN9 and CEN11 values. Generation point control unit 410 for controlling the time point at which the second pulse section is generated, and the pulse widths of the first pulse section and the second pulse section of the transmission control signal PINSTB. Pulse width fluctuation part 430 for fluctuating according to the value of?).

Here, the generation point control unit 410 toggles the transmission control signal PINSTB in response to the toggle of the input control signal PEN to generate a first pulse section of the transmission control signal PINSTB. The transmission control signal PINSTB is applied when the interval generating unit 412 and the first control period Delay1 corresponding to the cascade latency CL7, CEN9 and CEN11 are delayed at the time of toggling the input control signal PEN. The second pulse section generating unit 414 is provided for generating a second pulse section of the transmission control signal PINSTB by toggling.

In addition, the second pulse section generating unit 414, among the components of the generation point controller 410, has a predetermined delay amount, and receives the input control signal PEN and is delayed from the toggling point, the transmission control signal. A plurality of delay units 414A, 414B, 414C, 414D connected in a chain form to generate the second pulse section of PINSTB, and the respective delay units corresponding to the cascade latency CL7, CEN9, CEN11 values. Delay amount changing sections 414E, 414F, and 414G for varying the total delay amount of the plurality of delay sections 414A, 414B, 414C, and 414D by turning on / off the 414A, 414B, 414C, and 414D. .

4 does not include any components in the first pulse section generator 412. In other words, the toggling of the input control signal PEN is output as it is as the first pulse section of the transmission control signal PINSTB, which is transmitted in any case in preparation for the configuration of the second pulse section generating unit 414. This is to express that the first pulse section of the control signal PINSTB is generated before the second pulse section of the transmission control signal PINSTB, and may actually include a configuration such as a repeater.

In addition, the pulse width fluctuation unit 430 corresponds to the cascade latency CEN9 and CEN11 values of the first pulse section of the transmission control signal PINSTB having a length corresponding to the toggling section of the input control signal PEN. The second pulse section of the transmission control signal PINSTB having a length corresponding to the toggling section of the first pulse section changing unit 432 and the input control signal PEN for extending by the second time Delay2 is cascaded. A second pulse section changer 434 is provided for increasing the second time Delay2 corresponding to the latency CEN9 and CEN11 values.

Further, among the components of the pulse width fluctuation part 430, the first pulse period fluctuation part 432 has a predetermined delay amount and a transmission control signal having a length corresponding to the toggling length of the input control signal PEN. Corresponding to the cascade latency CEN9 and CEN11 values and a plurality of delay units 432A, 432B and 432C connected in a chain so as to delay the first pulse section of PINSTB and output them as the section control pulse CON_PUL1. Delay amount changing units 432D and 432E for varying the total delay amount of the plurality of delay units 432A, 432B and 432C by turning on / off the respective delay units 432A, 432B and 432C, and input control. The first pulse section and the section control pulse CON_PUL1 of the transmission control signal PINSTB having a length corresponding to the toggling length of the signal PEN are input and have a length longer than the toggling length of the input control signal PEN. And a first pulse section extension section 432F for outputting a first pulse section of the transmission control signal PINSTB.

The second pulse section changing unit 434 of the components of the pulse width changing unit 430 has a predetermined delay amount and has a length corresponding to the toggling length of the input control signal PEN. In response to the cascade latency CEN9 and CEN11 values and a plurality of delay units 434A, 434B and 434C connected in a chain form to delay the second pulse section of PINSTB and output it as the section control pulse CON_PUL2. Delay amount changing sections 434D and 434E for varying the total delay amount of the plurality of delay sections 434A, 434B and 434C by turning on / off the respective delay sections 434A, 434B and 434C, and input control. The second pulse section and the section control pulse CON_PUL2 of the transmission control signal PINSTB having a length corresponding to the toggling length of the signal PEN are input and have a length longer than the toggling length of the input control signal PEN. And a second pulse section extension section 434F for outputting a second pulse section of the transmission control signal PINSTB.

For reference, in the configuration of the SERDES circuit according to the embodiment of the present invention, the cascade latency (CL7, CEN9, CEN11) value is a semiconductor device including the SUDES circuit according to the embodiment of the present invention. Means that the time taken from the moment the column command YEN-READ or WRITE-is applied until the semiconductor device operates to output or store data-minimum time required due to physical limitations This is determined by counting the number of toggles corresponding to an externally applied clock. At this time, since the number of toggling of the clock applied from the outside is a value corresponding to the operating speed of the semiconductor device, the cas latency (CL7, CEN9, CEN11) values correspond to the operating speed of the semiconductor device.

For example, in the case of a semiconductor device having a relatively high operating speed, since the number of times of toggling of the clock applied externally-frequency-will be relatively high, the column command YEN-READ or WRITE-is applied. The number of times the frequency of toggling of the external clock required until the semiconductor device operates to output or store data is relatively high. On the contrary, in the case of a semiconductor device having a relatively slow operation speed, since the number of toggling of the clock applied from the outside will be relatively small, the semiconductor device starts from the moment when the column command YEN-READ or WRITE-is applied. The number of toggling of the external clock required to operate and output or store data is relatively small.

FIG. 5 is a timing diagram illustrating an operation waveform of a SUDES circuit according to an embodiment of the present invention among the components of the semiconductor device using the SUDES method illustrated in FIG. 4.

First, referring to FIG. 5, among the components of the semiconductor device using the SERSES method, the <SERSES circuit used in the input / output sense amplification circuit (IOSA) according to the embodiment of the present invention> Referring to the operation waveform, the first pulse EN1 is activated in response to the activation of the column command YEN. At this time, the input / output sense amplification circuit (IOSA) is the four local data (L_DATA <0: 7>) of the eight local data (L_DATA <0: 7>) contained in the eight local input / output lines (LIO <0: 7>) L_DATA <0: 3> is loaded on four global input / output lines GIO <0: 3> as global data G_DATA <0: 3>.

After the first pulse EN1 is activated by the column command YEN, when the first time Delay1 determined corresponding to the cascade latency CL7, CEN9, and CEN11 passes, the second column command YEN2 is activated. In response to activating the second column command YEN2, the second pulse EN2 is activated. At this time, the input / output sense amplification circuit (IOSA) has the remaining four local data (L_DATA) among the eight local data (L_DATA <0: 7>) contained in the eight local input / output lines (LIO <0: 7>). <4: 7> is loaded into four global input / output lines GIO <0: 3> as global data G_DATA <0: 3>.

In addition, when the second time Delay2 determined corresponding to the cascade latency CEN9 and CEN11 passes after the column command YEN is deactivated, the first pulse EN1 is deactivated and the second column command YEN2 is deactivated. After the second time Delay2 determined corresponding to the cas latency CEN9 and CEN11 passes, the second pulse EN2 is deactivated, so that the first pulse EN1 and the second pulse EN2 are respectively the column command YEN. And a longer activation period than the second column command (YEN2), which is carried on the time when the input / output sense amplification circuit (IOSA) operates, that is, on the local input / output line (LIO <0: 7>). This is to ensure sufficient time required for the existing local data L_DATA <0: 7> to be loaded as the global data G_DATA <0: 3> of the global input / output lines GIO <0: 3>.

That is, the operation of generating the first pulse EN1 and the second pulse EN2 during the operation of the SUDES circuit used in the input / output sense amplification circuit IOSA is performed in parallel with the local data L_DATA. <0: 7>) is for converting the serial global data G_DATA <0: 3>, and extending the activation period of the first pulse EN1 and the second pulse EN2 is necessary for data transmission. It is to secure time.

In addition, the time interval between the time when the first pulse EN1 is activated and the time when the second pulse EN2 is activated may be changed corresponding to the cas latency values CL7, CEN9, and CEN11. The time Delay1 changes in response to the cascade latency CL7, CEN9, and CEN11 values. In the drawing, the <Delay1 variable time>-enables local data L_DATA <0: 7> to be generated in parallel. The timing of switching to the global data G_DATA <0: 3> may vary depending on the operation speed of the semiconductor device.

Then, the interval in which the activation intervals of the first pulse EN1 and the second pulse EN2 are extended may be varied in response to the cascade latency CL7, CEN9, CEN11, that is, the second time Delay2. It is possible to vary the time required for data transfer in accordance with the operating speed of the semiconductor device by allowing the variation-<Delay2 variable time>-in the drawing to correspond to the value of the cascade latency CL7, CEN9, CEN11.

Referring to FIG. 3, the operation waveforms of the <SERDES circuit used for a PIPE LINE CIRCUIT> according to the prior art among the components of a semiconductor device using the SERDES method will be described. In response to the control signal PEN being activated, the first pulse section ① of the transmission control signal PINSTB is started. At this time, the pipeline circuit PIPE LINE CIRCUIT stores four global data G_DATA <0: 3> in four global input / output lines GIO <0: 3> in the first storage space P_LATCH1. It is stored as pipe data (P_DATA <0: 3>).

In addition, when the first time Delay1 determined corresponding to the cascade latency CL7, CEN9, CEN11 passes after the input control signal PEN is activated, the second input control signal PEN2 is activated, and the second input control signal is activated. In response to the activation of PEN2, the second pulse section ② of the transmission control signal PINSTB starts. At this time, the pipeline circuit PILINE CIRCUIT stores four global data G_DATA <0: 3> stored in four global input / output lines GIO <0: 3> in the second storage space P_LATCH2. Stored as pipe data (P_DATA <4: 7>).

Then, after the input control signal PEN is deactivated and the second time Delay2 determined corresponding to the cascade latency CL7, CEN9, CEN11 has passed, the first pulse section ① of the transmission control signal PINSTB ends. After the second input control signal PEN2 is deactivated and the second time Delay2 determined corresponding to the cascade latency CL7, CEN9, CEN11 has passed, the second pulse section ② of the transmission control signal PINSTB ends. Thus, the first pulse section ① and the second pulse section ② of the transmission control signal PINSTB have a longer pulse activation time than the input control signal PEN and the second input control signal PEN2, respectively. That is, the global data G_DATA <0: 3> stored in the global input / output line GIO <0: 3> is the time when the pipeline circuit PIPICUIT operates, that is, the pipeline circuit PIPE. This is to ensure sufficient time required for storage in the predetermined storage spaces P_LATCH1 and P_LATCH2 in the LINE CIRCUIT.

That is, the first pulse section ① and the second pulse section ② of the transmission control signal PINSTB are generated during the operation of the <SERDES circuit used for the PIPE LINE CIRCUIT>. The operation is for controlling an operation of storing a plurality of serially inputted global data G_DATA <0: 3> in the predetermined storage spaces P_LATCH1 and P_LATCH2, respectively, and the first pulse section of the transmission control signal PINSTB ( The operation of extending the pulse activation time of ①) and the second pulse section ② is a time required for storing a plurality of serially inputted global data G_DATA <0: 3> in the predetermined storage spaces P_LATCH1 and P_LATCH2, respectively. To secure.

In addition, the time interval between the time when the first pulse section ① of the transmission control signal PINSTB is generated and the time when the second pulse section ② of the transmission control signal PINSTB is generated is the CAS latency CL7, CEN9, CEN11) value, which means that the first time Delay1 can change in response to the cascade latency CL7, CEN9, CEN11 value, in the drawing, < Delay1 variable time > Timings in which a plurality of global data G_DATA <0: 3> input in series are stored in predetermined storage spaces P_LATCH1 and P_LATCH2 may be changed and applied according to an operation speed of a semiconductor device.

The interval in which the first pulse section ① of the transmission control signal PINSTB and the second pulse section ② of the transmission control signal PINSTB extends can be changed in correspondence with the cas latency CEN9 and CEN11 values. In other words, the second time Delay2 can be changed in correspondence with the values of the CAS latency CEN9 and CEN11-in the drawing, < Delay2 variable time > The time required for storing the plurality of global data G_DATA <0: 3> in the predetermined storage spaces P_LATCH1 and P_LATCH2 may be varied.

As described above, according to the embodiment of the present invention, in the semiconductor device using the SERDES method, the cascade latency CL whose value changes according to the frequency of an external clock input to the semiconductor device The value may change the operating speed of the SERDES circuit according to the operating speed of the semiconductor device.

In this case, the change in the operating speed of the SERDES circuit means that the output of the serialized data when converting the parallelized (serialized) data into the serialized (parallelized) data based on the SERDES circuit ( If the interval between input and output (input) is long, the operation speed of SERDES circuit is slow. Conversely, when converting parallelized (serialized) data to serialized (parallelized) data based on the SERDES circuit, if the output (input) interval and output (input) interval of the serialized data is short, SERDES) The operation speed of the circuit is high.

As a result, even when the operation speed of the semiconductor device changes, a stable SERDES operation may be performed to ensure sufficient margin for data input / output operations. That is, an error may be prevented from occurring during data input / output operations.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

For example, referring to the configuration of the SUDERS circuit in the above-described embodiment, a configuration for generating the first pulse EN1 and the second pulse EN2 by receiving the column command YEN is presented first. Subsequently, a configuration for extending the activation period of the first pulse EN1 and the second pulse EN2 will be presented later. In the present invention, a configuration for extending the activation period of the column command YEN is presented first, and then thereafter. This also includes the case where a configuration for generating the first pulse EN1 and the second pulse EN2 is presented later.

Similarly, a configuration for generating the first pulse section and the second pulse section of the transmission control signal PINSTB by receiving the input control signal PEN is presented first, and thereafter, the first pulse of the transmission control signal PINSTB. A configuration for extending the section and the second pulse section will be presented later. In the present invention, a configuration for extending the activation section of the input control signal PEN is presented first, and the first pulse section and the first pulse section of the transmission control signal PINSTB are presented. This also includes the case where a configuration for generating a two-pulse interval is presented later.

In addition, in the above-described embodiment, the signal CL7 is activated when the cas latency value is 7, the signal CL9 is activated when the cas latency value is 9, as a signal for controlling the operation speed of the SUDES circuit. The signal CL11 that is activated when the cascade latency value is 11 is used. The present invention is a signal for controlling the operation speed of the SUDES circuit. The signals CL1, CL2, CL3, CL4, This includes the case where CL5, CL6, CL8, CL10, CL12, ...) are used.

In addition, the logic gate and the transistor illustrated in the above-described embodiment should be implemented in different positions and types depending on the polarity of the input signal.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the configuration of a semiconductor device using a SERDES scheme.

FIG. 2 is a circuit diagram showing in detail a SERDES circuit according to the prior art among the components of a semiconductor device using the SERDES method shown in FIG.

FIG. 3 is a timing diagram showing an operation waveform of a SERDES circuit according to the prior art among the components of the semiconductor device using the SERDES method shown in FIG.

FIG. 4 is a circuit diagram showing in detail a SERDES circuit according to an embodiment of the present invention among the components of a semiconductor device using the SERDES method shown in FIG.

FIG. 5 is a timing diagram showing an operating waveform of a SERDES circuit according to an embodiment of the present invention among the components of the semiconductor device using the SERDES method shown in FIG. 4; FIG.

* Explanation of symbols for main parts of the drawings

200: pulse activation unit 400: activation time control unit

210: pulse generator 410: generation point controller

220: activation section expansion unit 420: activation section change unit

230: pulse width expansion unit 430: pulse width fluctuation unit

Claims (23)

Activation time control means for activating the second pulse in response to the activation of the first pulse corresponding to the column command, and controlling the activation time of the second pulse in response to a cas latency (CL) value; Activation period changing means for varying activation periods of the first and second pulses in response to the cas latency CL value; And The data corresponding to the plurality of first data lines is divided by a predetermined number in each of the activation periods of the first and second pulses and loaded on the plurality of second data lines, which are smaller than the plurality of first data lines. Data transmission means A semiconductor device comprising a. The method of claim 1, The activation point control means, A first pulse activator for activating the first pulse in response to an activation time of the column command; And a second pulse activator for activating the second pulse when the first time corresponding to the cas latency (CL) value is delayed at the time of activation of the column command. The method of claim 2, The second pulse activator, A plurality of delay units each having a predetermined delay amount and connected in a chain to delay and output the column command as a second pulse; And And a delay amount change section for varying the total delay amounts of the plurality of delay sections by turning on / off each of the delay sections in correspondence with the cas latency (CL) value. The method of claim 2, The activation section changing means, A first pulse activation section changer for extending the length of the activation section of the first pulse corresponding to the length of the activation section of the column command by a second time corresponding to the cas latency (CL) value; And And a second pulse activation section variation unit for extending the length of the activation section of the second pulse corresponding to the activation section length of the column command by a second time corresponding to the cas latency (CL) value. device. The method of claim 4, wherein The first pulse activation section change unit, A plurality of delay units each having a predetermined delay amount and connected in a chain form to delay and output the first pulse having an activation interval length corresponding to the activation interval length of the column command as an interval control pulse; A delay amount change unit for varying the total amount of delays of the plurality of delay units by turning on / off each of the delay units in response to the CAS latency CL value; And Receiving the first pulse having the activation section length corresponding to the activation section length of the column command and the section control pulse and outputting the first pulse having an activation length longer than the activation section length of the column command; A semiconductor device comprising one pulse output section. The method of claim 4, wherein The second pulse activation section change unit, A plurality of delay units each having a predetermined delay amount and connected in a chain form to delay and output the second pulse having an activation interval length corresponding to the activation interval length of the column command as an interval control pulse; A delay amount change unit for varying the total amount of delays of the plurality of delay units by turning on / off each of the delay units in response to the CAS latency CL value; And A second pulse for receiving the second pulse having the activation section length corresponding to the activation section length of the column command and the section control pulse and outputting the second pulse having an activation length longer than the activation section length of the column command; A semiconductor device comprising two pulse output units. The method of claim 1, And the plurality of first data lines is twice as many as the plurality of second data lines. The method of claim 4, wherein The data transmission means, A first transmitter configured to load, on the plurality of second data lines, data loaded on one or two first lines of the plurality of first data lines in response to the first pulse; And A second for loading data on 1/2 of a total number of the plurality of first data lines, the second lines not overlapping the first line, in response to the second pulse; A semiconductor device comprising a transfer unit. Activation time control means for activating the second pulse in response to the activation of the first pulse corresponding to the column command, and controlling the activation time of the second pulse in response to a cas latency (CL) value; Activation period changing means for varying activation periods of the first and second pulses in response to the cas latency CL value; And Data corresponding to a plurality of first data lines are respectively stored in different predetermined spaces in an activation period of each of the first and second pulses, and the stored data are simultaneously stored in a plurality of second data lines-the plurality of first data lines. More-Data transfer for loading on A semiconductor device comprising a. The method of claim 9, The activation point control means, A first pulse activator for activating the first pulse in response to an activation time of the column command; And a second pulse activator for activating the second pulse when the first time corresponding to the cas latency (CL) value is delayed at the time of activation of the column command. The method of claim 10, The activation section changing means, A first pulse activation section changer for extending the length of the activation section of the first pulse corresponding to the length of the activation section of the column command by a second time corresponding to the cas latency (CL) value; And And a second pulse activation section variation unit for extending the length of the activation section of the second pulse corresponding to the activation section length of the column command by a second time corresponding to the cas latency (CL) value. device. The method of claim 9, And the plurality of second data lines is twice as many as the plurality of first data lines. The method of claim 12, The data transmission means, A first transmission unit for loading data carried on the plurality of first data lines in half of the total number of the plurality of second data lines in response to the first pulse; And A second for loading data loaded on the plurality of first data lines in response to the second pulse, on a second half of the total number of the plurality of second data lines, which do not overlap the first line; A semiconductor device comprising a transfer unit. A second pulse section of the transmission control signal is generated in response to a first pulse section of the transmission control signal corresponding to an input control signal, and a second pulse section of the transmission control signal is generated in response to a cas latency (CL) value. Generation time control means for controlling a time point at which it is generated; Pulse width changing means for changing the pulse width of the first and second pulse sections according to the cas latency (CL) value; And Data transmission for loading data corresponding to a plurality of first data lines into a plurality of second data lines, which are smaller than the plurality of first data lines, by dividing the data corresponding to the plurality of first data lines by a predetermined number in the first and second pulse sections, respectively. Way A semiconductor device comprising a. The method of claim 14, The generation point control means, A first pulse section generating unit for generating a first pulse section of the transmission control signal by toggling the transmission control signal in response to toggling of the input control signal; And A second pulse section generating unit for generating a second pulse section of the transmission control signal by toggling the transmission control signal at a time delayed by a first time corresponding to a cas latency value at the time of toggling the input control signal; A semiconductor device characterized in that it comprises. The method of claim 15, The pulse width fluctuation means, A first pulse section changer for extending a first pulse section of the transmission control signal having a length corresponding to a toggling section of the input control signal by a second time corresponding to a cascade latency value; And And a second pulse section changer for increasing a second pulse section of the transmission control signal having a length corresponding to a toggling section of the input control signal by the second time corresponding to a cascade latency value. device. The method of claim 14, And the plurality of first data lines is twice as many as the plurality of second data lines. The method of claim 17, The data transmission means, A first transmitter configured to load, on the plurality of second data lines, data loaded on one or two first lines of the plurality of first data lines in a first pulse section of the transmission control signal; And Loading data contained in the second half of the total number of the plurality of first data lines in the second pulse section of the transmission control signal, and not overlapping the first line, on the plurality of second data lines. And a second transfer unit for the semiconductor device. A second pulse section of the transmission control signal is generated in response to a first pulse section of the transmission control signal corresponding to an input control signal, and a second pulse section of the transmission control signal is generated in response to a cas latency (CL) value. Generation time control means for controlling a time point at which it is generated; Activation time changing means for varying a pulse activation time corresponding to the first and second pulse sections in accordance with the cas latency (CL) value; And Store data corresponding to a plurality of first data lines in different predetermined spaces in the first and second pulse sections, respectively, and simultaneously store the stored data in a plurality of second data lines-more than the plurality of first data lines. Data transmission means for loading on A semiconductor device comprising a. The method of claim 19, The generation point control means, A first pulse section generating unit for generating a first pulse section of the transmission control signal by toggling the transmission control signal in response to toggling of the input control signal; And A second pulse section generating unit for generating a second pulse section of the transmission control signal by toggling the transmission control signal at a time delayed by a first time corresponding to a cas latency value at the time of toggling the input control signal; A semiconductor device characterized in that it comprises. The method of claim 20, The activation time varying means, A first pulse section changer for extending a first pulse section of the transmission control signal having a length corresponding to a toggling section of the input control signal by a second time corresponding to a cascade latency value; And And a second pulse section changer for increasing a second pulse section of the transmission control signal having a length corresponding to a toggling section of the input control signal by the second time corresponding to a cascade latency value. device. The method of claim 19, And the plurality of second data lines is twice as many as the plurality of first data lines. The method of claim 22, The data transmission means, A first transmission unit for loading data carried on the plurality of first data lines in a first pulse section of the transmission control signal into one half of a total number of the plurality of second data lines; And Loading data carried on the plurality of first data lines in a second pulse section of the transmission control signal on a second half of the total number of the plurality of second data lines, which do not overlap the first line. And a second transfer unit for the semiconductor device.

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