KR100933675B1 - Delayed fixed loop and semiconductor device including same - Google Patents

Abstract

The present invention relates to a delay-fixed loop having improved jitter characteristics and a semiconductor device including the same. The semiconductor device according to the present invention includes a circuit which is driven using a second voltage as an operating voltage and uses an internal clock; And a delay lock loop configured to output the internal clock by delaying the input clock with a delay value determined in response to the comparison result of the input clock and the feedback clock and the second voltage. do.

Delay lock loop, semiconductor device, memory device

Description

Delay locked loop and a semiconductor device including the same {Delay Locked Loop and Semiconductor Device including the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay locked loop and a semiconductor device including the same, and more particularly, jitter characteristics even when a voltage of a circuit outside the delay locked loop using the output clock of the delay locked loop changes. A delay locked loop for generating this excellent clock and a semiconductor device including the same.

In general, a clock is used as a reference for timing an operation in a system or a circuit, and may be used to ensure faster operation without an error. When a clock input from the outside is used internally, a time delay caused by an internal circuit, which is called skew, occurs, and a delay locked loop (DLL) is used to compensate for this time delay so that the internal clock has the same phase as the external clock. : Delay Locked Loop) is used.

On the other hand, delay locked loops are less susceptible to noise than conventional phase locked loops (PLLs), so they are synchronous including SDRAM (Synchronous DRAM) and DDR SDRAM (Double Data Rate Synchronous DRAM). Widely used in semiconductor memory. In this delay lock loop, there are a digital delay lock loop and an analog delay lock loop according to a method of controlling the delay amount.

1 is a block diagram showing a circuit for outputting data using an output clock of a conventional delay locked loop and a delay locked loop.

The delay lock loop is a delay value determined by the delay value determining unit 110 and the delay value determining unit 110 for adjusting the delay value of the delay unit 120 by comparing the input clock clkin with the fed back clock fbclk. The delay unit 120 outputs the internal clock clkout by delaying the input clock and delays the internal clock clkout by the modeling value of the delay locked loop external circuit 150 to output the feedback clock. It is configured to include a replica delay unit (130).

That is, the delay lock loop models the delay value generated in the data output path and delays the input clock by a predetermined value to output the internal clock clkout. Therefore, the data (or signal) output circuit 150 using the internal clock clkout may output data (or signal) in synchronization with the external clock Extclk.

The delay unit 120 and the delay value determiner 110 have different internal configurations depending on whether the delay lock loop is an analog or digital method. In the case of the analog system, the delay unit 120 includes a voltage control delay line (VCDL), and the delay value determination unit 110 includes a phase detector and a charge pump. The loop filter unit is configured to adjust the delay value of the voltage control delay line VCDL by using the output voltage. In addition, in the digital method, the delay unit 120 includes a plurality of unit delay stages, and the delay value determination unit 110 compares an internal clock and a feedback clock through a phase comparator to determine several unit delay stages. You decide whether to use Delay units. In the digital method, the delay value determiner 110 includes a phase comparator, a shift register controller, a shift register, and the like, which is disclosed in Korean Patent Registration No. 10-0631156. Although there is only a difference in the internal structure, the basic concept that the analog type digital method compares the input clock clkin and the feedback clock fbclk to determine the delay value of the delay unit 120 is the same. The configuration method of the delay unit 120 and the delay value determination unit 110, whether analog or digital, corresponds to techniques well known to those skilled in the art.

The circuit 150 outside the delay lock loop outputs data to the outside of the semiconductor device by using an internal clock clkout output from the delay lock loop. Since the internal clock clkout with a delay value is used, data can be output in synchronization with the external clock extclk. In the case of a semiconductor memory device, such a circuit is called a DOUT buffer or an output driver.

2 is a view showing the configuration of a delay unit 120 of the conventional analog method.

The analog delay unit 120 is composed of a voltage controlled delay line (VCDL), which is a loop of the inverters 210 and the delay value determination unit 110 connected in series as shown in the figure. The transistor 220 includes a transistor 220 that adjusts an amount of current flowing through the inverters 210 by a control voltage Vctrl output from a filter. The analog clock (the delay value is continuously adjusted) delays the input clock (clkin) and outputs the internal clock (clkout).

3 is a view showing the configuration of a conventional digital delay unit 120.

The digital delay unit 120 includes n delay stages UD1,..., UDn. Each of the delay stages UD1, ..., UDn uses the input clock clkin as one input and outputs the delay selection signals Reg_1, ... Reg_n-3, Reg_n-2, which are output from the delay value determining unit 110. The first NAND gate NAND100 having Reg_n-1 and Reg_n as the type force, respectively, and the second NAND gate having the output of the unit delay stage of the previous stage as the other input with the output of the first NAND gate NAND100 as one input. NAND101 and an inverter INV100 that accepts an output of the second NAND gate NAND101. However, since the first delay stage UD1 has no delay stage at the front end, the first delay stage UD1 receives the power supply voltage VDDL instead of the output of the previous delay stage.

Taking the delay stage UD4 as an example, when the delay selection signal Reg_n-3 has a logic level 'high', the first NAND gate NAND100 is enabled to invert the input clock clkin and output the second signal. The NAND gate NAND101 and the inverter INV100 delay and output the input clock clkin for a predetermined time. On the other hand, when the delay selection signal Reg_n-3 has a logic level 'low', the first NAND gate NAND100 is disabled to block the input clock clkin, and the output of the first NAND 100 logic is output. Since the level 'high' is maintained, the second NAND gate NAND101 and the inverter INV100 delay and output the output of the delay stage UD3 at the front end for a predetermined time.

That is, the number of delay stages UD1, UD2, UD3, UD4, ... UDn is determined by the delay selection signals Reg_1, ... Reg_n-3, Reg_n-2, Reg_n-1, Reg_n. The total delay value of the delay unit 120 is determined.

FIG. 4 is a diagram illustrating the interior of two NAND gates of the delay stage UD1 of FIG. 3.

FIG. 4 is a diagram illustrating the interior of two NAND gates in the delay stage UD1. The internal structure of the NAND gates composed of PMOS transistors and NMOS transistors can be confirmed.

Referring again to Figure 1 looks at the problem of the delay lock loop according to the prior art.

The starting point of the external clock (extclk) into the delay locked loop is n * t0 (t0 is one cycle of the clock, n is an arbitrary integer), and the delay amount in the input buffer 100 is d1 and the delay unit 120. The delay amount at dx is referred to as dx, the delay amount at driver 140 is d2, and the delay amount at data output circuit 150 is referred to as do. In addition, since the clock output from the data output circuit 150 should be aligned with the external clock extclk, the clock (intclk + do) should be m * t0 (m is an arbitrary integer). To sum them up, n * t0 + d1 + dx + d2 + do = m * t0, which means dx = k * t0-do-d1-d2 (k is any integer). In this case, the replica delay unit 130 models the delay value dr = l * t0 + do + d1 + d2 (l is an arbitrary integer).

The delay locked loop has a delay as described above and is locked. Since the delay locked loop generally uses a separate stable power supply, VDDL, the delay value dx does not change over time. However, the delay value of the circuit 150 of the data output path is greatly affected by the power supply situation. For example, an output driver, which is a data output circuit 150 of a semiconductor memory device, uses VDDQ as its power source. When a plurality of data are output at one time by a burst cas operation, the VDDQ value is unstable. As a result, the delay value of the data output circuit 150 changes. Due to the momentary fluctuation of the VDDQ value, there is a problem that jitter occurs with the external clock extclk when the internal output clkout, which is the output clock of the DLL, is used in the data output circuit 150.

In summary, since the delay locked loop uses a separate stable voltage VDDL, the delayed loop always maintains a constant delay value after locking, but the circuit 150 using the output clock (clkout) of the delay locked loop has its own power supply ( If VDDQ) is shaken, its delay value is also changed, resulting in jitter with an external clock.

The present invention has been proposed to solve the above problems of the prior art, and has an object of eliminating jitter components caused by an unstable power supply voltage of a circuit using an internal clock that is an output clock of a delay locked loop.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a circuit driven using a second voltage as an operating voltage and using an internal clock; And a delay lock loop configured to output the internal clock by delaying the input clock with a delay value determined in response to the comparison result of the input clock and the feedback clock and the second voltage. do.

That is, since the delay value of the delay lock loop is changed by receiving the second voltage, which is the power supply voltage of the circuit using the internal clock output from the delay lock loop, the jitter component does not occur even if the second voltage changes.

The delay lock loop according to the present invention is configured to delay the input clock with a delay value determined in response to a comparison result between the input clock and the feedback clock and the output voltage of the internal clock-output clock of the delay locked loop. It includes a delay unit.

That is, since the delay lock loop changes its delay value in response to the power supply voltage of the external circuit, no jitter component occurs even if the power supply voltage of the external circuit changes.

The delay locked loop and the semiconductor device including the same according to the present invention monitor the power supply voltage variation of the circuit using the internal clock, which is the output clock of the delay locked loop, and reflect the internal clock to the delay value of the delay locked loop. There is an advantage that the jitter component can be prevented even if the power supply voltage of the circuit used is changed.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

5 is a diagram illustrating a configuration of a delay locked loop and a semiconductor device including the same according to an embodiment of the present invention.

As shown in the figure, the semiconductor device according to the present invention includes a circuit 510 which is driven with the second voltage VDDQ as the operating voltage and uses an internal clock clkout; And the input clock clkin with the delay value determined in response to the comparison result of the input clock clkin and the feedback clock fbclk and the second voltage VDDQ. And a delay lock loop 520 for delaying and outputting an internal clock clkout.

The circuit 510 using the internal clock clkout means a circuit inside the semiconductor device using the internal clock clkout, which is an output clock of the delay locked loop 520. The circuit 510 outputs a signal or data synchronized with the external clock extclk to the outside of the semiconductor device using the internal clock clkout. When the semiconductor device is a memory device, the circuit 510 becomes an output driver (also called a DOUT buffer). The circuit 510 using the internal clock (clkout) shows a case in which the second voltage VDDQ and the 510 circuit, which are different from the delay locked loop 520, are output drivers and use VDDQ as the power source. ).

The delay locked loop 520 according to the present invention is a power supply of an external circuit 510 using a comparison result of an input clock clkin and a feedback clock fbclk and an internal clock clkout-an output clock of a delay locked loop. And a delay unit 523 for delaying the input clock with a delay value determined in response to the voltage VDDQ. The delay unit (120 of FIG. 1) of the conventional delay lock loop simply delays the input clock (clkin) with a delay value determined according to a comparison result of the input clock (clkin) and the feedback clock (fbclk). However, the delay lock loop 520 of the present invention receives a second voltage VDDQ, which is a power supply voltage of the external circuit 510 (which is external to the delay lock loop, not the outside of the semiconductor device), and accordingly receives the feedback. The delay value of the delay unit 523 is changed.

The delay locked loop 520 uses the first voltage VDDL as its operating voltage because it is necessary to use an isolated power supply due to the need for stable operation.

The delay lock loop 520 may compare the input clock clkin with the feedback clock fbclk in addition to the delay block 523 as described above, and adjust the delay value 522 (as described in the related art). Similarly, the configuration depends on whether it is analog or digital); And a replica delay unit 524 for outputting a feedback clock fbclk by delaying the internal clock clkin by the modeling value of the circuit 510. Since the delay value determining unit 522 and the replica delay unit 524 have been described in the above-described prior art, further description will be omitted here.

In summary, according to the present invention, the delay unit 523 of the delay lock loop 520 adjusts its delay value in response to the change in the power supply voltage VDDQ of the delay lock loop external circuit 510. Therefore, even if the delay value in the external circuit 510 is changed due to the change in the power supply voltage VDDQ of the external circuit 510, the jitter component is compensated because the delay lock loop 520 compensates for the change in the delay value. It can suppress occurrence.

Hereinafter, embodiments of the delay unit 523 will be described.

FIG. 6 is a diagram illustrating an embodiment of the delay unit 523 when the delay lock loop 520 is a digital delay lock loop.

The digital delay unit 523 may include a plurality of delay stages (see FIG. 3), and FIG. 6 illustrates two NAND gates in the delay stage in detail (corresponding to conventional FIG. 4). Shows the configuration)

As shown in the figure, the delay unit 523 has an amount of current flowing in the NAND gate in response to the power supply voltage VDDQ_D of the external circuit in addition to the basic NAND gate configuration (P01, P02, P03, N01, N02, N03, N04). And a transistor (P05) for adjusting the voltage. Therefore, when the power supply voltage VDDQ of the external circuit changes, the amount of current flowing inside the NAND gate changes, which changes the delay value of the delay stage.

In detail, the transistor P05 is inputted by the voltage distribution VDDQ_D of the power supply voltage VDDQ of the external circuit, which is used to change the range of the voltage VDDQ_D inputted to change the amount of current of the transistor P05. To adjust according to the characteristics. In order to achieve the object of the present invention, not all delay stages in the delay unit 523 need to include a transistor P05 for adjusting the amount of current according to the power supply voltage VDDQ of an external circuit. Even if only some of the plurality of delay stages in the delay unit 523 include the transistor P05, the object of the present invention can be achieved.

When the delay unit 523 is configured as described above, the delay value determiner 522 determines how many delay stages are used, but the delay values of the delay stages are the power supply voltage VDDQ of the external circuit. Determined by Accordingly, it is possible to reflect the change in the delay value caused by the change in the power supply voltage VDDQ of the external circuit to the delay unit 523.

In the case of using the PMOS transistor as the transistor P05, since the delay value of the external circuit 510 increases when the power supply voltage VDDQ of the external circuit decreases, the delay value of the delay unit 523 must be controlled to be smaller. Because. In addition, since the delay value of the external circuit 510 is reduced when the power supply voltage VDDQ of the external circuit is increased, the delay value of the delay unit 523 must be controlled to be increased (as described above, dx). (Delay value of delay part) = k * t 0 -do (delay value of external circuit) -d1-d2 is related).

FIG. 7 is a diagram illustrating an embodiment of the delay unit 523 when the delay lock loop 520 is an analog delay lock loop (shown in FIG. 2).

As shown in the drawing of the analog delay unit 523, a voltage control delay line (VCDL) including a plurality of delay stages 710, 720, 730, 740, and 750 has a basic configuration. Transistors 711, 721, 731, 741, and 751 for varying the amount of current flowing in response to the power supply voltage VDDQ.

Like the transistors P05 of FIG. 6, the transistors 711, 721, 731, 741, and 751 adjust the amount of current flowing in the delay unit 523 according to the power supply voltage VDDQ of the external circuit, thereby supplying power to the external circuit. It is possible to reflect the change in the delay value caused by the change in the voltage VDDQ to the delay unit 523.

Of course, as in FIG. 6, all of the delay stages 710, 720, 730, 740, and 750 may include transistors 711, 721, 731, 741, and 751 that adjust the amount of current in response to a power supply voltage of an external circuit. There is no need, and even if only some of the delay stages include such a transistor, the object of the present invention can be achieved.

The delay unit 523 of FIGS. 6 and 7 has only a difference between an analog method and a digital method, and adjusts the amount of current flowing in the delay unit 523 according to a change in the power supply voltage VDDQ of the external circuit 510. The basic concept of changing the solution delay is the same.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments are possible within the scope of the technical idea of the present invention.

In particular, it is natural that there are various methods of changing the delay value in the delay unit of the delay locked loop according to the power supply voltage of the external circuit using the output clock of the delay locked loop.

1 is a block diagram showing a circuit for outputting data using a conventional delay locked loop and an output clock of a delay locked loop.

2 is a view showing the configuration of a conventional analog delay unit 120.

3 is a view showing the configuration of a conventional digital delay unit 120.

4 is a view illustrating the interior of two NAND gates of the delay stage UD1 of FIG. 3.

5 is a configuration diagram of an embodiment of a delay locked loop and a semiconductor device including the same according to an embodiment of the present invention.

6 is a diagram illustrating an embodiment of the delay unit 523 when the delay lock loop 520 is a digital delay lock loop.

FIG. 7 illustrates an embodiment of the delay unit 523 when the delay lock loop 520 is an analog delay lock loop.

Claims (17)

A circuit which is driven with the second voltage as an operating voltage and uses an internal clock; And A delay locked loop which is driven using a first voltage as an operating voltage and delays the input clock with a delay value determined in response to a comparison result of an input clock and a feedback clock and a voltage level of the second voltage. Semiconductor device comprising a. The method of claim 1, The delay lock loop, A delay unit for adjusting a delay value of the input clock, The amount of current flowing through the delay unit is adjusted in response to the second voltage. The method of claim 2, The delay unit includes a plurality of delay stages, All or some of the plurality of delay stages includes a transistor configured to adjust an amount of current flowing between the first voltage and the ground voltage in response to the second voltage. The method of claim 3, wherein The transistor, And dividing the second voltage into a voltage inputted to its gate. The method of claim 2, The delay lock loop, And a delay value determiner for comparing the input clock and the fed back clock to adjust the delay value. The method of claim 5, The delay lock loop, And a replica delay unit delaying the internal clock by a modeling value of the circuit and outputting the feedback clock. The method of claim 1, The circuit, And a circuit for outputting a signal or data to the outside of the semiconductor device in synchronization with the internal clock. The method of claim 1, The semiconductor device is a semiconductor memory device, The circuit is an output driver, And the first voltage is a delay locked loop voltage (VDDL) and the second voltage is VDDQ. The method of claim 1, The delay lock loop, And the delay value increases as the second voltage increases, and the delay value decreases as the power supply voltage of a circuit using the internal clock decreases. A delay unit for delaying the input clock with a delay value determined in response to a comparison result of the input clock and the feedback clock and the voltage level of the power supply voltage of the external circuit using the internal clock-output clock of the delay locked loop. Delay fixed loop comprising a. The method of claim 10, And the power supply voltage of the external circuit and the power supply voltage of the delay lock loop are different voltages. The method of claim 11, The amount of current flowing through the delay unit is delayed fixed loop, characterized in that the control in response to the power supply voltage of the external circuit. The method of claim 12, The delay unit includes a plurality of delay stages, All or some of the plurality of delay stages includes a transistor configured to adjust an amount of current flowing between a power supply voltage and a ground voltage of the delay locked loop in response to a power supply voltage of the external circuit. The method of claim 13, The transistor, Delay fixed loop, characterized in that the power supply voltage of the external circuit is divided by voltage and input to its gate. The method of claim 12, The delay lock loop, And a delay value determining unit for comparing the input clock and the fed back clock to adjust the delay value. The method of claim 15, The delay lock loop, And a replica delay unit configured to delay the internal clock by a modeling value of the circuit and output the feedback clock. The method of claim 10, The delay unit, And the delay value increases when the power supply voltage of the external circuit increases, and the delay value decreases when the power supply voltage of the external circuit decreases.

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