KR100933594B1 - Active Voltage Level Bus Switch (or Pass Gate) Translator - Google Patents

Abstract

A bidirectional voltage level switch for connecting the high voltage circuit 27 to the low voltage circuit 29 without using a one-way signal is disclosed. The drive circuits 22, 24 for the gate of the MOS switch 20 operate to clamp the low voltage side of the conversion switch to limit the low voltage to a level compatible with the low voltage circuit connected to the low voltage side. Pull-up circuit 28 is connected to the high voltage side of the switch and defines a threshold lower than the low voltage. When the signal reaches the threshold, the pullup circuit pulls up the high voltage side to high voltage. Again, driving the gate of the switch 20 prevents the high voltage from reaching the low voltage side. If the low voltage side drives the high voltage side 'low' through the switch, the pullup circuit is designed to be overwhelmed by the low voltage driving circuit, thereby making the high voltage side 'low'. When the threshold is lowered, the pullup circuitry is disabled.

Bidirectional Voltage Level Translation, Pullup Circuit, High Voltage Transceiver, Impedance Path, Low Voltage Drive Circuit

Description

ACTIVE VOLTAGE LEVEL BUS SWITCH (OR PASS GATE) TRANSLATOR}

<Related application>

This application is filed on November 27, 2001 and claims priority to US Provisional Patent Application No. 60 / 335,650, the name of which is the same as the inventor of this application. This provisional application is incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to bus switches, and more particularly to bus switches that convert one voltage to another.

Microprocessor and application specific integrated circuits and other such large scale integrated circuits often break chip communication through solid state imaging switches, called so-called bus switches. Due to the various circuit types available, such as, for example, TTL, LVTTL (or known as low level logic signal LVLS), and even ECL, voltage conversion is often combined or required in these bus switches.

1 shows a known bus switch 2 which connects a high voltage node 4 to a low voltage node 6. Gate 8 of bus switch 2 is driven by PMOS 10 and NMOS 12 in a push / pull configuration. The source 14 of the PMOS is connected to Vcc via a diode 16. The gates of PMOS 10 and NMOS 12 are connected with true enable 18 in the 'low' state. When the enable signal 18 is 'high', the NMOS 12 is 'on' and the PMOS 10 is 'off'. In this state, the gate 8 of the bus switch 2 goes 'low' to keep the NMOS bus switch 2 'off' and disconnect the node 4 from the node 6. When signal 18 is 'low', NMOS 12 is 'off', PMOS 10 is 'on' and P-rail voltage is generated at gate 8 of bus switch 2 and the bus The switch 2 is turned on and the nodes 4 and 6 are connected. According to the design parameters of the bus switch 2, the p-rail voltage is at its gate and the highest voltage is clamped at the low voltage node 6 when the bus switch is 'on'. In other examples, a reference voltage can be applied to the p-rail and the clamped voltage at low voltage node 6 can be programmed by changing the reference voltage. The PMOS 10, NMOS 12, composed of one input and output, is a logic inverter having a threshold defined by structural parameters of the MOSFET, as known to those skilled in the art. For example, the threshold of the PMOS 10, NMOS 12 circuit may be set to approximately + 2.5V.

Other conversion transceivers that pass signals in both directions are known to those skilled in the art, but these circuits require one-way signals. The direction input allows the conversion switch to pass the signal in a specific direction.

There is a need for a bidirectional bus switch that converts from high voltage to low voltage and from low voltage to high voltage and operates in either direction without requiring a one-way signal.

<Summary of invention>                 

The present invention provides a bidirectional voltage level conversion switch excluding one direction signal. The voltage level shift switch includes an NMOS device in which the drain is connected to the high voltage circuit and the source is connected to the low voltage level circuit, although the voltages may be approximately the same in any application.

The enable signal, through the control circuitry, turns the gate of the NMOS device on or off. The voltage level supplied to the gate by the control circuit limits or clamps the voltage level at the source to any voltage compatible with the low voltage circuit regardless of the voltage at the drain.

The pullup circuit is connected to the drain of the NMOS switch and provides a connection to a high voltage power supply. Threshold is set for a pullup circuit lower than the low voltage signal level. When the switch is 'on' and the low voltage circuit drives the drain above the threshold, the pullup circuit activates to drive the drain to high voltage. Again, the source is clamped through the gate control circuit. If the drain is driven lower than the threshold, the pullup circuitry is disabled. When the conversion switch is 'on' and the low voltage circuit drives the drain 'low' through the conversion switch, the pull up circuit is designed to allow the low voltage drive circuit to overpower this pull up circuit capability to drive the drain high. Similarly, the high voltage drive circuitry overpowers the pullup circuitry capability to drive the drain 'high'.

The pullup circuit can be connected to the source of the NMOS transistor to improve its speed. The circuit is likely to be similar to a pullup circuit connected to the drain, but is connected between the source and the Vccl (low voltage power supply).                 

The ability of a high and low drive circuit to drive the pullup circuit 'low' and overwhelm this pullup circuit can be achieved through the design of a MOS transistor switch in the preferred embodiment of the pullup circuit. The physical size of the MOS switch can be small enough to be overwhelmed by the drive circuitry as known to those skilled in the art.

In another preferred embodiment, the pull up circuits may include a low impedance path to a high voltage power source, but the low impedance path is present for a predetermined time and then designed to provide a high impedance path. The high impedance path is designed to be driven in a 'low' state by being overwhelmed by drive circuits connected to both sides of the switch.

1 is a circuit schematic diagram of a conversion bus switch of the prior art.

2A and 2B are schematic views of a circuit showing a preferred embodiment of the present invention.

3A and 3B are circuit schematic diagrams of circuits that may be used for the gates of bus switches.

4 is a schematic diagram of a circuit that may be used in connection with a high voltage node.

5 is another schematic circuit diagram that may be used in place of FIG.

6 is a block diagram of a computer system using the present invention.

2A and 2B are preferred embodiments of the present invention. Fig. 2A is in block diagram form, and Fig. 2B shows a more detailed circuit configuration. Bus switch 20 and logic inverter 22 operate as in FIG. The Vref circuit 24 is connected to an inverter 22 that drives the gate of the NMOS 20. In FIG. 2B, the P-rail (generated from the Vref circuit 24) is called a down translation clamp circuit and operates to clamp the low voltage node 34 when the NMOS 20 is 'on'. do. Pull-up circuits 28 and 31, referred to as pull-up auxiliary circuits, are connected to high voltage node 26 and low voltage node 34, respectively, and operate to accelerate pull-up of each of these nodes.

Referring to FIG. 2B, the pullup support circuit 28, in a push / pull configuration, drives an PMOS 32 and includes an inverter 30 of NMOS 40 and PMOS 42. The PMOS 32 source is connected to the drain to the high voltage node 26 and the Vcch rail. Case 1 considers that bus switch 20 is biased 'on' and NAND gate 27 drives node 26 from ground towards Vcch. Inverter 30 turns on upon reaching its threshold and turns on PMOS 32, which supports driving node 26 to Vcch. However, as discussed below, the + Vcch voltage is not transmitted to the low voltage node 34 because the low voltage node 34 is clamped by the circuit at the gate of the bus switch 36. When node 26 is driven 'low' past the threshold, inverter 30 drives PMOS 32 high and turns off PMOS 32 such that a low voltage is lowered through the bus switch. Sent to node 34. The circuitry driving node 26 low overwhelms the drive capability designed into PMOS 32.

Case 2 considers that bus switch 20 is biased 'on' and NAND 29 drives node 34 from ground towards Vccl. The inverter 30 drives the gate of the PMOS 32 low when the threshold is reached. In a preferred embodiment the threshold is designed to be approximately one half of the Vccl voltage. Inverter 30 turns on PMOS 32, which drives node 26 to Vcch. Again, Vcch at node 26 does not flow back back to node 34 because the node 34 voltage is clamped by the gate 36 voltage. The example described to emphasize this operation provides a low voltage transition from Vccl Volts to + Vcch without a unidirectional signal to the bus switch.

In a preferred embodiment, the present invention converts between any virtual logic power levels. Vcch and Vccl are combinations of hypothetical high and low potentials, for example, Vcch at +5.0 V or +3.3 V, or +2.5 V, and Vccl at +3.3 V or +2.5 V, or 1.8 V. It can be selected from a combination of and is not limited to these. The present invention can be connected between approximately the same logic power levels.

The pull-up circuit 29 shown only in FIG. 2A is powered from the Vccl power source and connected to the low voltage node 34 and operates similar to the circuit 28 and in the same manner.

When node 34 is driven in a 'low' state by three-phase inverter 29, its drive capability overwhelms the pull-up capability of PMOS 32 and node 26 is driven towards ground. It is known to those skilled in the art to design the size and other characteristics of PMOS 32 to operate in this manner. When node 26 reaches the threshold, the inverter is turned off and both nodes 34 and 26 are driven to a 'low' state.

In one example, the three-phase inverter circuits 27 and 29 that drive and receive signals through the NMOS 20 are lowered by more than 1 milliamp at low logic voltages, and the PMOS 32 is approximately 1/2 dB or less. Is designed to be overwhelmed. Other values may be designed in other preferred embodiments and other applications. It is also known to those skilled in the art that other bipolar semiconductors may be used in place of the MOSFET shown, and that other semiconductors may be used in place of other active and passive circuit elements.

Inverter 3, NMOS 40 and PMOS 42 are designed with thresholds within the voltage range indicated by the low voltage signal range, as will be appreciated by those skilled in the art and as discussed above. In other preferred embodiments, the thresholds of the NMOS and PMOS may be varied to exhibit any other level of triggering and / or other advantageous properties, which are known to those skilled in the art.

Referring to FIG. 2B, when the enable signal 23 is 'low', the bus switch is 'on' and the high voltage at node 34 is p− on the gate of bus switch 20 through PMOS 44. Clamped by rail voltage. That is, the high voltage at node 26 will not be transmitted to low voltage node 34 due to p-rail clamping. The p-rail may be connected to an external reference voltage (not shown) or dropped from Vcch as diode D2. The p-rail voltage may be designed by the designer to be compatible with the low level inverter driver 29 connected to the node 34 as is known to those skilled in the art.

Referring to FIG. 2B, the remaining circuit elements 24 of D1, RC1, comparator 48 and current source or clamp 50 serve to protect the low voltage node 34 from exceeding the transient voltage. Comparator 48 compares its voltages at inputs A and B, and at stop or steady state output C of the comparator commands the current source 5 to be 'off'. However, if a high transient voltage appears at node 26, it will be connected to gate 36 through the drain / gate capacitance of relatively large bus switch 20. When the PMOS 44 is 'on', its transient voltage is connected to the p-rail and the input B to the comparator. This allows the comparator to turn on the current clamp 50, which absorbs energy in the transient state, and to lower the voltage on the gate 36 to almost prevent the transient voltage appearing at the node 34.

In the circuit shown in Fig. 2B, the input A to the comparator is diode D1, which is dropped into the R1C1 circuit at + Vcch. C1 may be a reverse biased junction diode. R1C1 provides a time delay that prevents any transient voltage present at Vcch from occurring at the A input, but allows the transient voltage to appear at the B input. In another embodiment, the A input voltage may be formed by a reference diode, a series of forward biased diodes, or any other known low voltage reference circuit. In some cases, if a transient voltage appears at Vcch, the B or p-rail will be driven 'high', the A input will remain at least for some time, and the comparator turns on the current clamp again so that the transient voltage is p Act to prevent the rail from being completely present at node 34.

In a preferred embodiment, Vcch is supplied and Vccl and reference voltage are derived from Vcch. Also in other preferred embodiments, Vcch, Vccl and the reference voltage are generated on the chip or they are all supplied externally.

3A shows another circuit example suitable for driving the gate 36 of the bus switch 20. Here, the PMOS (44 in FIG. 2) is replaced by logic equivalent to the inverter 45 driving the bipolar NPN transistor 47. When the 'low' state is active or true enable (true enable: 23) is 'low', NPN 37 is 'on' and Vref turns on bus switch 20 and high level at node 34. Will be present in the gate 36 clamping. The resistor 51 and the NMOS 49 operate as a bias current source for the NPN transistor 47. When the 'true' true enable 23 signal is 'high', the NMOS 46 is 'on' to turn off the switch 20.

In a preferred embodiment, the reference voltage is set to the threshold of the Vcc potential plus pullup circuit 28.

3B is another circuit that drives the gate of the switch 20. When the true EN signal in the 'low' state goes 'low' and the NPN and PMOS transistors are turned on below Vref, the base emitter drop of the NPN transistor is applied to the gate 36 turning on the switch, as before. . When the EN signal is 'high', the PMOS is turned off and the NMOS 46 is turned on and then the switch 20 is turned off in turn.

4 shows another preferred embodiment in place of the circuit 28 of FIG. 2. In FIG. 4, when node 26 is lowered or grounded, NMOS 50 is 'off' and PMOS 52 is biased on. The drain of the PMOS 52 and the gate of the PM0S 54 are biased off the PMOS 54 at Vcc. The output of the last inverter I3 of the three inverters I1, I2 and I3 is 'low', and the PMOS 56 is 'on' to drive the source of the PMOS 54 to Vcch. As previously discussed, the threshold of the inverter formed by 50 and 52 can be designed at 2V. When node 26 driven by NAND 29 to +3.3 V reaches a +2.0 V threshold, NMOS 50 is turned on and PMOS 52 is turned off. The gate of PMOS 54 is lowered to ground level to turn on PMOS 54. PMOS 54 helps drive node 26 'high' by the current supplied through PMOS 56. Inverter I1 is designed with approximately the same threshold as the inverters of items 50 and 52. Therefore, the output of the inverter I3 becomes 'high' after the delay of the three inverters turns off the PMOS 56. As a result, PMOS 56 provides high current drive to help drive node 26 'high' only for a period of time before the output of I3 goes 'high'. After the delay, R2 keeps node 26 at Vcch. As discussed above, if node 26 is driven 'low' by NAND 29, the drive signal may lower the current from R1 and drive node 26 'low'. Upon reaching the threshold of the inverters again, PMOS 54 is turned off before PMOS 56 is turned on, and the system drive current may drive node 26 'low'. The threshold of the I1 inverter is designed to be at different levels from the PMOS 52 and the NMOS 50 to improve delay through the inverter chain as is known to those skilled in the art. In addition, as is known to those skilled in the art, the thresholds of different MOSFETs can be different from each other to improve the operation of the circuit.

Another preferred embodiment that replaces the pull up circuit of FIG. 2A is shown in FIG. 5. Here, the PMOS 32 and the inverter 30 are the same as in FIG. 2 but with a circuit 60 added. Here, PMOS 64 is configured to provide additional current to temporarily help drive node 26 'high'. The circuit 62 is designed with a delay (as in the inverter chain). When the NAND gate 66 threshold is reached, the rising node 26 voltage and the circuit 62 output 68 are at the gate and NAND output of the PMOS 64 for a predetermined amount of time determined by the design of 62. Drives 67 low, and PMOS 64 is then turned off by turning output 68 low. When PMOS 64 is 'off', NAND 29 may overpower pull-up of PMOS 32 and drive drive node 26 low as discussed above. When the input to NAND 66 is 'low' it drives its output 'high' and keeps PMOS 64 'off' regardless of the output of circuit 62. Of course, ensuring that the threshold of the circuit 62 does not turn on the PMOS 64 before driving the node 26 effective to keep the NAND output 67 high. Be careful.

6 shows a block diagram illustrating an electronic system 70 having a bidirectional bus 76 with conversion switches 72 connecting the logic portion of the computer system 70. Connections from the Local System to Other Systems For example, a communication connection to a modem or television system or a remote display, keyboard, power supply, memory, etc. may advantageously use the two-way switch of the present invention.

Regarding the circuit 62, other preferred embodiments may include level sensitive and / or timing circuits in many configurations that advantageously enhance the operation of other circuit elements known to those skilled in the art.

Claims (10)

An active bi-directional voltage level translation switch that connects a high voltage signal first node to a low voltage signal second node. An NMOS switch device having a drain connected to the first node, a source connected to the second node, and a gate connected to a control node, Enable signal, A control circuit having an input connected to the enable signal and an output connected to the control node, the enable signal defining two states, a switch 'on' state and a switch 'off' state, A reference voltage connected to the control circuit, in the switch 'on' state, a reference voltage power is applied to the control node and clamps the source to a voltage compatible with the low voltage signal, and in the switch 'off' state, the A voltage signal for turning off a conversion switch is applied to the control node, and A pull-up circuit connected to the high voltage from the first node and defining a threshold lower than the low voltage, wherein the pull-up circuit directs the first node toward the high voltage when the drain voltage is higher than the threshold. The pull-up circuit is disabled when the voltage at the drain is lower than the threshold voltage. Including, And a low voltage drive circuit overwhelms the pull-up circuit when the conversion switch is 'on' and the low voltage circuit drives the first node 'low' through the conversion switch. 2. The apparatus of claim 1, further comprising a second pull-up circuit connected to the low voltage from the second node and defining a threshold lower than the low voltage, The second pull-up circuit drives the second node towards the low voltage when the source voltage is higher than the threshold, and the second pull-up circuit is disabled when the source is lower than the threshold. Level shift switch. The switch of claim 1, wherein the reference voltage is derived from one of a high voltage power supply (Vcch) or a low voltage power supply (Vccl). The switch of claim 1, wherein the low voltage power supply (Vccl) and the reference voltage are derived from a high voltage power supply (Vcch). 2. The active bidirectional voltage level switch of claim 1, wherein a high voltage power supply (Vcch), a low voltage power supply (Vccl), and the reference voltage are generated at a chip. The active bidirectional voltage of claim 1, wherein the high voltage is selected from the group consisting of +5 V, +3.3 V, and +2.5 V, and wherein the low voltage is selected from the group consisting of +3.3 V, +2.5 V, and +1.8 V. Level shift switch. An active bi-directional voltage level shift switch connecting a high voltage signal first node to a low voltage signal second node, A MOS switch device having a drain connected to the first node, a source connected to the second node, and a gate connected to a control node, Enable signal, A control circuit having an input connected to the enable signal and an output connected to the control node, the enable signal defining two states, a switch 'on' state and a switch 'off' state, A reference voltage connected to the control circuit, in the switch 'on' state, a first voltage power is applied to the control node and clamps the source to a voltage compatible with the low voltage signal, in the switch 'off' state, A voltage signal for turning off the conversion switch is applied to the control node, and A pull-up circuit connected to the high voltage from the first node and defining a threshold lower than the low voltage, wherein the pull-up circuit lowers the first node for a predetermined period of time when the voltage of the drain is higher than the threshold. Through the impedance and then through the high impedance to the high voltage and the pullup circuit is disabled when the voltage at the drain is lower than the threshold voltage. Including, And a low voltage circuit driving high impedance to low by driving the first node low through the changeover switch when the changeover switch is 'on'. 8. The device of claim 7, further comprising a second pull-up circuit connected to the low voltage from the second node and defining a threshold lower than the low voltage, The second pull-up circuit drives the second node towards the low voltage when the source voltage is higher than the threshold, and the second pull-up circuit is disabled when the source is lower than the threshold. Level shift switch. The method of claim 7, wherein the pull-up circuit, A fourth circuit connected from the first node to a third node and defining a threshold lower than the low voltage—when the voltage of the drain is higher than the threshold, the fourth circuit causes the first node to display the first node; Connect to node 3 and the fourth circuit is disabled when the voltage at the drain is lower than the threshold voltage; A second switch connecting said high voltage to a third node, and A delay circuit connected to the second switch and controlling an 'on' / 'off' state of the second switch, the delay circuit turning on the second switch when the first node voltage is lower than the threshold; And the second switch is turned off after a time delay when the first node voltage is higher than the threshold. Active bidirectional voltage level conversion switch comprising a. An electronic system selected from the group consisting of a communication system, a display, a keyboard, a power source, and a memory, the electronic system further comprising a bidirectional voltage conversion switch, The bidirectional voltage conversion switch, A MOS switch device having a drain connected to the first node, a source connected to the second node, and a gate connected to the control node, Enable signal, A control circuit having an input connected to the enable signal and an output connected to the control node, the enable signal defining two states, a switch 'on' state and a switch 'off' state, A reference voltage connected to the control circuit, in the switch 'on' state, a first voltage power is applied to the control node and clamps the source to a voltage compatible with a low voltage signal; in the switch 'off' state, the A voltage signal for turning off a conversion switch is applied to the control node, and A pull-up circuit connected to a high voltage from the first node and defining a threshold lower than a low voltage, wherein the pull-up circuit drives the first node toward the high voltage when the voltage of the drain is higher than the threshold, and the drain The pull-up circuit is disabled when the voltage of is lower than the threshold voltage. Including, And the low voltage drive circuit overwhelms the pull-up circuit when the conversion switch is 'on' and the low voltage circuit drives the first node 'low' through the conversion switch.

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