KR100929676B1 - Liquid crystal display device, thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

The thin film transistor array panel according to the present invention includes an insulating substrate, a gate line and a gate electrode formed long in one direction on the insulating substrate, a gate insulating film formed to cover the gate line and the gate electrode, and a semiconductor formed in a predetermined region of the gate insulating film. A layer, an ohmic contact layer formed on the semiconductor layer, a source electrode, a drain electrode, and a gate line formed to overlap a portion of the ohmic contact layer, a data line defining a pixel region, and a contact hole exposing the drain electrode. Formed on the passivation layer, the passivation layer, the pixel electrode connected to the drain electrode through the contact hole, a support layer formed on the pixel electrode and having an acid and valley formed thereon, and an alignment layer formed along the acid and valley when formed on the support layer. It includes.

Description

Liquid crystal display, thin film transistor display panel and manufacturing method thereof

1 is a schematic cross-sectional view of a liquid crystal display according to the present invention.

2 to 5 are diagrams for describing an operation of the liquid crystal display according to the exemplary embodiment of the present invention.

6A is a layout view of a color filter display panel according to a first exemplary embodiment of the present invention.

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A.

7A is a layout view of a thin film transistor array panel according to a first exemplary embodiment of the present invention.

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A.

8A to 12B are layout and cross-sectional views illustrating a method of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention in the order of process.

13A is a cross-sectional view of a thin film transistor array panel according to a second exemplary embodiment of the present invention.

13B and 13C are cross-sectional views taken along lines XIIIb-XIIIb 'and XIIIc-XIIIc' of FIG. 13A, respectively.

14 and 15 are cross-sectional views of a thin film transistor array panel according to third and fourth embodiments of the present invention, respectively.

※ Explanation of symbols on main parts of drawing ※

11, 21: alignment film 101: support film

110, 210: insulating substrate 140: gate insulating layer

121: gate line 123: gate electrode

125: gate pad 131: sustain electrode line

133: sustain electrode 171: data line

173 Source electrode 175 Drain electrode

177: electrode for holding capacitance 179: date pad

180: protective layer 190: pixel electrode

220: black matrix 270: common electrode

The present invention relates to a thin film transistor substrate and a method of manufacturing the same.

A thin film transistor (TFT) display panel is used as a circuit board for driving each pixel independently in a liquid crystal display device or an organic electroluminescence (EL) display device, and includes a gate line and an image signal for supplying a scan signal to the thin film transistor. Wiring such as a data line for supplying the circuit is formed. In addition, the color filter display panel includes a color filter, a black matrix, a common electrode, and the like for forming color.

The liquid crystal display may be classified into a TN mode, a VA mode, and an IPS mode according to the alignment characteristics of the filled liquid crystal.

TN mode is generally used twisted nematic (hereinafter referred to as TN) liquid crystal. TN liquid crystal molecules have a long, thin rod shape, have a constant pitch, twist in a spiral shape, and have a twisted structure in which the long-axis alignment direction of the liquid crystal molecules is continuously changed.

In a liquid crystal display device using a TN liquid crystal, the incident polarized light exhibits different optical viewing angle characteristics according to the arrangement of the long axis and the short axis of the molecule. Since the viewing angle of the liquid crystal display device is formed along the long axis of the liquid crystal molecules of the spiral structure, the long axis of the molecule changes according to the viewing angle. Such a liquid crystal display has a symmetrical viewing angle with respect to the horizontal direction and an asymmetrical viewing angle with respect to the vertical direction. In particular, a gray level phenomenon occurs in a direction in which the liquid crystal tilt direction and the viewing angle at the center of the cell coincide with each other. Therefore, the light transmittance is distributed relatively symmetrically with respect to the viewing angle in the horizontal direction, but the light transmittance is distributed asymmetrically with respect to the up and down directions.

The liquid crystal mode having the wide viewing angle characteristic improved therefrom includes an in-plane-switching (hereinafter referred to as IPS) mode and a vertically aligned mode (hereinafter referred to as VA) mode.                         

The IPS mode is a structure in which the common electrode and the pixel electrode are spaced apart from each other on the same substrate by a predetermined interval, and the change of the refractive index of the liquid crystal molecules is small depending on the direction viewed by the transverse electric field distributed between the pixel electrode and the reference electrode, thereby improving the viewing angle. . However, in the transverse electric field mode, since the reference electrode and the pixel electrode are simultaneously formed on a single pixel, the aperture ratio of the liquid crystal panel is reduced, the luminance characteristic is poor, and the response speed is slow.

The VA mode facilitates symmetrical arrangement of liquid crystals and has fast response characteristics. The vertical alignment mode may be used to form a multi-domain such as patterned vertical alignment (PVA) to improve viewing angle characteristics, but the process for forming the domain is complicated and the structure of the pixel is complicated. In addition, since the use of negative liquid crystals requires high voltage driving, the aperture ratio is low, and the resiliency of the liquid crystal itself is used even at the response speed.

As described above, each mode has advantages and disadvantages for each characteristic, and thus, research for overcoming each disadvantage is required.

Accordingly, an object of the present invention is to provide a thin film transistor array panel and a method of manufacturing the same for minimizing the disadvantages of the thin film transistor array panel.

The thin film transistor array panel according to the present invention for achieving the above object is an insulating substrate, the gate line and the gate electrode formed long in one direction on the insulating substrate, the gate insulating film formed to cover the gate line and the gate electrode, the gate insulating film A semiconductor layer formed in a predetermined region, an ohmic contact layer formed on the semiconductor layer, a data line and a drain electrode defining a pixel region by crossing a source electrode, a drain electrode, and a gate line formed by overlapping a portion of the ohmic contact layer. A protective film including a contact hole for exposing the light source, a pixel electrode formed on the protective film and connected to the drain electrode through the contact hole, a support film formed on the pixel electrode and having an acid and valley formed thereon, It includes an alignment film formed along the bone.

The data line, the source electrode, and the drain electrode are preferably formed in the same pattern as the ohmic contact layer, and the ohmic contact layer is preferably formed in the same pattern as the semiconductor layer except for a predetermined region between the source electrode and the drain electrode. .

In addition, the peaks and valleys are preferably formed by diagonal lines symmetrical with respect to the line dividing the pixel region into two, and the support film is preferably formed by a photosensitive film.

Another thin film transistor array panel according to the present invention for achieving the above object is an insulating substrate, a gate insulating film formed to cover the gate line and the gate electrode formed in one direction on the insulating substrate, the gate insulating film, the gate insulating film A semiconductor layer formed in a predetermined region of the semiconductor layer, an ohmic contact layer formed on the semiconductor layer, a data line defining a pixel region intersecting with a source electrode, a drain electrode, and a gate line formed partially overlapping the ohmic contact layer; A pixel formed on the line, the source electrode, and the drain electrode and including a contact hole exposing the drain electrode, the protective film having an acid and valley on the upper side, and a pixel formed along the acid and valley on the upper portion of the protective layer and connected to the drain electrode through the contact hole An electrode, an alignment film formed on the pixel electrode, The alignment film is formed in the form of a hill and a valley.

The data line, the source electrode, and the drain electrode are preferably formed in the same pattern as the ohmic contact layer, and the ohmic contact layer is preferably formed in the same pattern as the semiconductor layer except for a predetermined region between the source electrode and the drain electrode. .

In addition, the peaks and valleys are preferably formed by diagonal lines symmetrical with respect to the line dividing the pixel region into two, and the support film is preferably formed by a photosensitive film.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, the method comprising: forming a gate line and a gate electrode in one direction on an insulating substrate, forming a gate insulating layer on the gate line and the gate electrode, and a gate insulating layer Forming a semiconductor layer over the semiconductor layer, forming a resistive contact layer over the semiconductor layer, forming a data line, a source electrode, and a drain electrode overlapping a portion of the resistive contact layer and crossing the gate line to define a pixel region; Forming a passivation film having a contact hole exposing the drain electrode on the line, the source electrode and the drain electrode, forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer, and forming a support layer having an acid and a valley on the pixel electrode Forming, forming an alignment layer on the support layer It includes.

The support layer may include forming a photoresist film on the pixel electrode, and exposing and developing the photoresist film through a photomask, and the photomask may include a slit pattern or a translucent film.

According to another aspect of the present invention, there is provided a color filter display panel including a first insulating substrate, a thin film transistor formed on the first insulating substrate, and a thin film transistor array panel including a pixel electrode connected to the thin film transistor. A color filter display panel including a second insulating substrate facing the display panel and a common electrode formed on the second insulating substrate, a liquid crystal filled between the thin film transistor array panel and the color filter display panel, and a thin film transistor display panel in contact with the liquid crystal A first alignment layer having a valley and a hill, and a second alignment layer formed on one surface of the color filter display panel in contact with the liquid crystal and rubbing in a predetermined direction, wherein the liquid crystal is formed on the surface of the first alignment layer with respect to the first alignment layer. It is oriented vertically.

It is preferable that the liquid crystal has a negative dielectric constant here, and the valley and the hill preferably extend in a direction different from a predetermined direction.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Now, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[First Embodiment]

1 is a schematic cross-sectional view of a liquid crystal display according to a first exemplary embodiment of the present invention.

As shown in the figure, the thin film transistor array panel 1 and the color filter display panel 2 face each other, and the liquid crystal 3 is filled between the two display panels 1 and 2. The liquid crystals 3 adjacent to the color filter display panel 2 are aligned in a horizontal manner with respect to the color filter display panel 2, and the liquid crystals 3 adjacent to the thin film transistor array panel 1 are vertically aligned. Herein, the liquid crystal 3 has negative dielectric anisotropy.

Since the alignment layer is formed on the thin film transistor array panel 1 and the color filter display panel 1, the liquid crystal 3 is aligned in a constant shape according to the rubbing direction or surface shape of the alignment layer. In the present invention, since the alignment film (not shown) formed on the color filter display panel 1 is rubbed in a direction parallel to the gate line 121, the liquid crystal 3 adjacent to the color filter display panel 1 is a color filter display panel ( Is oriented horizontally with respect to 2). Since the alignment film (not shown) formed on the thin film transistor array panel 2 is formed to have an acid and a valley, the liquid crystal 3 is aligned along the acid and valley so as to have a pretilt angle.                     

In addition, a spacer (not shown) for maintaining a gap between the color filter display panel 2 and the thin film transistor array panel 1 and a sealing material (not shown) for sealing the liquid crystal are further formed.

The operation of the liquid crystal display will be described with reference to FIGS. 2 to 5. 2 to 4 schematically show the alignment of liquid crystals when the voltage is 0, when the voltage is V1, and when the voltage is V2. FIG. 5 is a pixel area of the liquid crystal display according to the present invention. Figure is a schematic diagram.

First, as shown in FIG. 2, in the initial alignment state where no voltage is applied, the liquid crystal 3 is aligned parallel to the display panels 1 and 2 at a position adjacent to the color filter display panel 2, but the thin film transistor display panel 1 The angle closer to the display panels 1 and 2 becomes larger as the N is closer to), and is oriented so as to be substantially perpendicular to the surface of the thin film transistor array panel 1. Since the alignment film 21 of the color filter display panel 2 is rubbed, the liquid crystal adjacent to the color filter display panel 2 is aligned in parallel with the rubbing direction of the alignment film 21. The alignment layer 11 of the thin film transistor array panel 1 is not rubbed, and the alignment layer 11 has acid and valleys. Therefore, the liquid crystal 3 is aligned so as to have a pretilt angle according to the shape of the peak and the valley.

As shown in FIG. 3, when the voltage V1 is applied to the liquid crystal display, the liquid crystal 3 having negative dielectric anisotropy becomes smaller than the pretilt angle of the liquid crystal 3 when the liquid crystal 3 is initially aligned. Here, since the pretilt directions of the liquid crystals 3 in the domain 1 and the domain 2 are opposite to each other, two domains are formed. In this case, the liquid crystal moves only on a plane in which the directors of the liquid crystal are arranged in the initial alignment state.

4 and 5, when the applied voltage is increased to V2 (> V1), the pretilt angle of the liquid crystal becomes almost zero. At this time, the liquid crystal begins to undergo azimuthal twisting torque. This torque occurs because the liquid crystal present on the x-y plane tries to lower the surface energy by contacting a larger area with the surface (micro-groove theory).

After that, when the torque is higher than the bulk twist threshold energy obtained by Equation 1 (minimum energy for maintaining the state parallel to the substrate), the liquid crystal is twisted.

[Equation 1]

When the liquid crystal starts to twist as described above, two domains are formed because the twist directions in the A region A and the B region B are opposite. Therefore, the four domains can be formed by the two domains formed at this time and the two domains formed at the initial orientation.

The color filter display panel will be described in more detail with reference to FIGS. 6A and 6B as follows. 6A is a layout view of a color filter panel according to a first exemplary embodiment of the present invention, and FIG. 6B is a cross-sectional view taken along line VIb-VIb ′ of FIG. 6A.

In the color filter display panel 2 according to the present invention, a black matrix 220 defining a pixel area in a matrix form is formed on the transparent first insulating substrate 210. The red, green, and blue color filters 230R, 230G, and 230B are formed on the pixel area, and the common electrode 270 is formed to cover the color filters 230R, 230G, and 230B. An alignment layer 21 is formed on the common electrode 270. The alignment layer 21 is rubbed in the same direction as the gate line 121.

Next, the thin film transistor array panel will be described in more detail with reference to FIGS. 7A and 7B. FIG. 7A is a layout view of a thin film transistor according to a first exemplary embodiment of the present invention, and FIG. 7B is a cross-sectional view taken along line VIIb-VIIb ′ of FIG. 7A.

In the thin film transistor array panel 1, a gate line 121 extending in one direction is formed on the transparent second insulating substrate 110. The gate electrode 123 is formed in a portion or a branch of the gate line 121. One end 125 of the gate line 121 may be formed wider than the width of the gate line 121 to receive a signal transmitted from a gate driving circuit (not shown). In this case, in order to increase the storage capacitance of the pixel region, a portion of the gate line 121 is enlarged to overlap the conductive capacitor conductor 177 formed on another layer and connected to the pixel electrode 190. If the storage capacitor is sufficient, it may not be formed. If the storage capacitor is insufficient, a storage electrode line (not shown) formed in parallel with the gate line 121 may be added.                     

The gate insulating layer 140 is formed on the gate line 121 and the gate electrode 123 to cover them. A semiconductor layer 154 made of polycrystalline silicon is formed directly on the gate insulating layer 140 corresponding to the gate electrode 123. In addition, a source ohmic contact layer region 163 and a drain ohmic contact region 165 are formed on the semiconductor layer 154. The source and drain ohmic contact regions 163 and 165 are formed at a predetermined distance from the predetermined region of the semiconductor layer 154. The predetermined region is a channel region that forms a channel between the source electrode 173 and the drain electrode 175.

The data line 171 crossing the gate line 121 is formed on the gate insulating layer 140. A source electrode 173 is formed as a branch of the data line 171 and overlaps a portion of the source portion ohmic contact 163. A drain electrode 175 is formed to face the source electrode 173 at a predetermined distance and overlap a portion of the drain portion ohmic contact 165. In addition, a conductor pattern 177 for a storage capacitor is formed to overlap with a portion of the gate line 121 to increase the storage capacitance. One end portion 179 of the data line 171 may be formed larger than the data line 171 to receive an external signal.

The passivation layer 180 is formed on the entire surface of the substrate including the data line 171, the source electrode 173, the drain electrode 175, and the conductive pattern 177 for the storage capacitor. In the passivation layer 180, a first contact hole 181 exposing the drain electrode 175 and a second contact hole 182 exposing the conductive capacitor pattern 177 for the storage capacitor are formed. The pixel electrode 190 connected to the drain electrode 175 is formed on the passivation layer 180 through the first contact hole 181 and the second contact hole 182.

In addition, auxiliary contact members 95 and 97 may be further formed to compensate for adhesion with an external circuit device and to protect one end of the gate line 121 and the data line 171 to which an external signal is applied. Their application is optional. The auxiliary contact members 95 and 97 may pass through the third and fourth contact holes 183 and 184 exposing one ends 125 and 179 of the gate line 121 and the data line 171. 179).

The support layer 101 is formed to cover the pixel electrode 190 and the auxiliary contact members 95 and 97. A valley and an acid are formed on the support film 101. When the valley and the hill are divided into two parts of the pixel area (upper and lower area A and B), the valley and the hill formed in the area A are in the diagonal direction descending from the upper right to the lower left. The mountain is formed in an oblique direction from the upper left to the lower right. The angle of inclination of the valley and the mountain only needs to be inclined enough to determine the direction in which the liquid crystal 3 should be tilted.

The non-rubbing alignment layer 11 is formed on the support layer 101 along the valleys and the mountains formed on the surface of the support layer 101. Therefore, the alignment film 11 is also formed to have a valley and an acid.

A method of manufacturing the thin film transistor array panel according to the first embodiment of the present invention described above will be described in detail with reference to FIGS. 7A to 10B. 7A to 10B are layout and cross-sectional views illustrating a method of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention in a process order.                     

First, as shown in FIGS. 8A to 8B, the conductive layer is formed on the transparent insulating substrate 110 and then patterned by a photolithography process to form the gate line 121 and the gate electrode 123. In order to increase the storage capacitance of the pixel region, one end portion 125 of the gate line 121 is formed to be larger than the width of the gate line 121.

As shown in FIGS. 9A and 9B, the gate insulating layer 140, the amorphous silicon layer 150 which is not doped with impurities, and the amorphous silicon layer 160 which is doped with impurities are disposed on the gate lines 121, 123, and 125. Laminated. Afterwards, the amorphous silicon layer 160 doped with impurities and the amorphous silicon layer 150 without dopants are patterned by a photolithography process so that the ohmic contact layer pattern 160A and the semiconductor layers 151 and 154 where the channel regions are not separated. ).

As shown in FIGS. 10A and 10B, after forming a conductive layer on the ohmic contact layer pattern 160A, the conductive layer is patterned to form a data line 171, a source electrode 173, a drain electrode 175, and a storage capacitor. The former conductor pattern 177 is formed. Subsequently, a predetermined region of the ohmic contact layer pattern 160A is etched using these 171, 173, and 175 as a mask to complete the ohmic contact layers 161, 163, and 165.

As shown in FIGS. 11A and 11B, the passivation layer 180 is formed to cover the data line 171, the source electrode 173, and the drain electrode 175. The first contact hole exposing the drain electrode 175 and the second contact hole 182 exposing the one end 125 of the gate line 121 and the one end portion of the data line 121 are exposed by a photolithography process. A third contact hole 183 exposing 179 and a fourth contact hole 184 exposing the conductor pattern 177 for the holding capacitor are formed.

Thereafter, a transparent conductive layer such as indium zinc oxide (IZO), indium tin oxide (ITO), or the like is formed on the passivation layer 180 and then patterned to form a drain electrode 175 through the first and fourth contact holes 181 and 184, respectively. ) And an auxiliary contact connected to one end of the gate line 121 and the data line 171 through the pixel electrode 190 and the second and third contact holes respectively connected to the conductive pattern 177 for the storage capacitor. The members 95 and 97 are formed.

12A and 12B, a support film 101 having peaks and valleys is formed on the pixel electrode 190 and the auxiliary contact members 95 and 97. The supporting film 101 is formed by forming a photoresist film on the pixel electrode 190 and then exposing the photo film with a photomask pattern having a slit pattern. In addition to the slit pattern, it may be formed using a grid pattern or a photomask pattern including a translucent film. Or it can form by the reflow method etc. which make a part of photosensitive film flow down.

After that, the alignment layer 11 is formed of polyimide on the support layer 101 (see FIGS. 1A and 1B). The alignment film 11 is formed along the peaks and valleys of the support film 101.

Second Embodiment

FIG. 13A is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIG. 13B is a cross-sectional view taken along lines XIIIb-XIIIb 'and XIIIc-XIIIc' of FIG. 13A.

As shown, the data line 171, the source electrode 173 and the drain electrode 175 and the ohmic contact layers 161, 163, and 165 of the second embodiment are formed in the same pattern. The ohmic contacts 161, 163, and 165 are formed in the same pattern except for a predetermined region of the semiconductor layers 151 and 154. The predetermined region is a channel region that forms a channel between the source electrode 173 and the drain electrode 175. Except for the parts described above, they are formed in the same structure as in the first embodiment.

Such a structure uses the semiconductor layer 151, 154, the ohmic contact layers 161, 163, and 165 and the data wirings 171, 173, and 175 at one time using a single photomask having a transparent region, a translucent region, and an opaque region. It appears because it is formed through a photographic process.

[Examples 3 and 4]

14 and 15 are cross-sectional views of thin film transistor array panels according to third and fourth embodiments of the present invention, respectively.

As shown, unlike the first and second embodiments, the third and fourth embodiments form valleys and valleys in the passivation layer 180 without forming the support layer 101. That is, the pixel electrode 190 and the alignment layer 11 are formed along the peaks and valleys formed in the passivation layer 180. In this case, the hills and valleys formed on the passivation layer 180 may be formed to have a step larger than the hills and valleys formed on the support layers 101 of the first and second embodiments. This is because the step difference between the peaks and valleys formed in the passivation layer 180 is reduced due to the pixel electrode 190 formed on the passivation layer 180.

As described above, when the alignment layer formed on the TFT panel has acid and valleys, four domains can be easily formed, and thus a wide viewing angle can be obtained. In addition, in the present invention, the liquid crystal in the A region (A) is twisted counterclockwise, and the liquid crystal in the B region (B) is clockwise. Since it is twisted in the direction, the disclination exists only at one boundary portion between the regions A and B. In addition, since the liquid crystal is initially aligned to have a linear angle, the direction in which the liquid crystal should be tilted when the voltage is applied to the liquid crystal display is already specified, so that the response time of the liquid crystal is fast.

Since the liquid crystal adjacent to the thin film transistor array panel is oriented in the vertical direction, retardation does not occur. And although the liquid crystal adjacent to the color filter display panel is aligned in the horizontal direction, retardation does not occur when the long axis of the liquid crystal is arranged in parallel with the polarization axis of the first polarizing plate. At this time, the polarization axis of the second polarizing plate facing the first polarizing plate parallel to the long axis is formed to intersect the polarization axis of the first polarizing plate perpendicularly.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, when the alignment layer is formed to have an acid and a valley, the liquid crystal is aligned along the acid and the valley, thereby easily forming two domains. Further, by dividing the pixel area into two parts and forming the hill and valleys in a symmetrical diagonal direction, two other domains can be obtained in addition to the two domains of the hills and valleys.

Therefore, when the four domains are formed according to the present invention, a wide viewing angle can be easily obtained, thereby providing a high-quality liquid crystal display device.

Claims (13)

Insulation board, A gate line and a gate electrode formed to extend in one direction on the insulating substrate; A gate insulating film formed to cover the gate line and the gate electrode; A semiconductor layer formed on the gate insulating film, An ohmic contact layer formed on the semiconductor layer, A data line crossing the source electrode, the drain electrode, and the gate line overlapping the ohmic contact layer; A protective film including a contact hole exposing the drain electrode; A pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole; A support layer formed on the pixel electrode and having a linear acid and valley formed thereon to determine the alignment of the liquid crystal; And a alignment layer formed on the support layer and formed along the acid and valleys. In claim 1, The data line, the source electrode and the drain electrode are formed in the same pattern as the ohmic contact layer. The ohmic contact layer overlapping the data line is formed in the same pattern as the semiconductor layer overlapping the data line. The method of claim 1 or 2, And the peaks and valleys are formed with diagonal lines symmetrical with respect to a line dividing the pixel region. The method of claim 1 or 2, The support film is a thin film transistor array panel formed of a photosensitive film. Insulation board, A gate line and a gate electrode formed to extend in one direction on the insulating substrate; A gate insulating film formed to cover the gate line and the gate electrode; A semiconductor layer formed on the gate insulating film, An ohmic contact layer formed on the semiconductor layer, A data line crossing the source electrode, the drain electrode, and the gate line overlapping the ohmic contact layer; A protective film formed on the data line, the source electrode and the drain electrode and including a contact hole exposing the drain electrode, and having a linear acid and a valley on the upper part to determine the alignment of the liquid crystal; A pixel electrode formed along the peaks and valleys on the passivation layer and connected to the drain electrode through the contact hole; An alignment layer formed on the pixel electrode, The thin film transistor array panel of which the alignment layer is formed to have an acid and a valley. In claim 5, The data line, the source electrode and the drain electrode are formed in the same pattern as the ohmic contact layer. The ohmic contact layer overlapping the data line is formed in the same pattern as the semiconductor layer overlapping the data line. In claim 5 or 6, And the peaks and valleys are formed with diagonal lines symmetrical with respect to a line dividing the pixel region. In claim 5 or 6, The support film is a thin film transistor array panel formed of a photosensitive film. Forming a gate line and a gate electrode in one direction on the insulating substrate, Forming a gate insulating film on the gate line and the gate electrode; Forming a semiconductor layer on the gate insulating film, Forming an ohmic contact layer over the semiconductor layer; Forming a data line, a source electrode and a drain electrode overlapping the ohmic contact layer and crossing the gate line; Forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a contact hole exposing the drain electrode; Forming a pixel electrode on the passivation layer, the pixel electrode being connected to the drain electrode through the contact hole; Forming a support layer having linear peaks and valleys that determine the alignment of the liquid crystal on the pixel electrode; A method of manufacturing a thin film transistor array panel including forming an alignment layer on the support layer. In claim 9, Forming a photoresist film on the pixel electrode; Exposing the photoresist film through a photomask and then developing the photoresist film; The photomask is a manufacturing method of a thin film transistor display panel comprising a slit pattern or a translucent film. A thin film transistor array panel including a first insulating substrate, a thin film transistor formed on the first insulating substrate, and a pixel electrode connected to the thin film transistor; A color filter display panel including a second insulating substrate facing the thin film transistor array panel and a common electrode formed on the second insulating substrate; A liquid crystal filled between the thin film transistor array panel and the color filter panel; A first alignment layer formed on one surface of the thin film transistor array panel in contact with the liquid crystal and having a valley and a hill, A second alignment layer formed on one surface of the color filter display panel in contact with the liquid crystal and rubbing in a predetermined direction; And the liquid crystal is vertically aligned with respect to the first alignment layer on the surface of the first alignment layer. In claim 11, Liquid crystal display device having a negative dielectric constant. In claim 11, And the valley and the hill extend in a direction different from the rubbing direction.

Images