KR100929234B1 - Espiabridge, packet processing apparatus and method - Google Patents

Abstract

The present invention relates to an Spia bridge, a packet processing apparatus, and a method thereof, wherein the SPI bridge is configured to hardware-support Ethernet FCS removal and packet mode, and the packet processing apparatus including the SPI is configured for each use. It is possible to process a packet using a single line card without having to design it individually, thereby reducing manufacturing costs and maximizing efficiency due to the use of a network processor, thereby significantly improving performance.

SPI, Bridge, Ethernet, Packet, bridge, Ethernet, FCS

Description

SPI bridge, packet processing apparatus and method thereof {SPI bridge, packet processing apparatus and method of bridge for ethernet packet processing}

The present invention provides a packet processing performance of a network by configuring a packet processing apparatus including a SPI bridge for converting packets for packet processing transmitted to a packet over sonnet (POS) line card, a packet mode, and the SPI bridge. An improved spia bridge, a packet processing apparatus, and a method thereof are provided.

The present invention is derived from the research conducted as part of the IT growth engine technology development of the Ministry of Information and Communication and the Ministry of Information and Telecommunication Research and Development. [Task Management No .: 2006-S-061-02, Task name: IPv6 based Qos service and terminal mobility Support router technology development].

Due to the rapid spread of the Internet, data traffic has exploded as the Internet became popular, and new types of services have emerged based on the wired / wireless Internet integration.

However, compared to the increase in traffic due to the popularization of the Internet and the emergence of new services, the existing network equipment does not have much progress in packet processing capacity and performance, thereby showing a limitation in its processing.

As a solution to this, network processors have emerged, but network devices using these network processors use two network processors for ingress and egres to increase performance, or integrate ingres and egres in terms of cost efficiency rather than performance. We designed a line card using one network processor.

In addition, in order to receive an Ethernet frame and transmit it to a POS line card through a switch fabric, there is a problem that a function of processing an Ethernet FCS that is not used in a POS, in addition to a function of a network processor for transmitting on a downlink, is required.

Due to these problems, in the past, different types of line cards have to be designed. Therefore, the simple SPI bridge function is used to increase the number of physical ports or to support only the switching function. Only the physical port capacity can be increased within the limit and there is a problem of increasing the complexity of microcoding of a network processor to support this.

 In addition, when the packet is transmitted from the Ethernet line card to the POS line card through the switch fabric, the micro code for the network processor of each line card has to perform different packet processing, and there is a problem that the manufacture of an additional device is required. .

SUMMARY OF THE INVENTION An object of the present invention is to process packets transmitted to a Packet Over Sonet (POS) line card without any additional device, and to support packet modes in hardware, thereby reducing costs and maximizing the efficiency of using a network processor. The present invention provides an SPI bridge, a packet processing apparatus, and a method for improving performance.

According to an embodiment of the present invention, an SPIABridge selects a packet mode of a received packet, removes a preamble of the packet corresponding to the selected packet mode, and analyzes a header of the packet to determine a destination address. A frame analyzer for extracting and searching the extracted destination address by a key value to check whether the packet is forwarded to the uplink or downlink, and the result is generated as an index and transmitted to the frame analyzer. An LU controller, an FCSChop controller for removing the FCS of the packet or filtering the packet in response to the index value, and an SPI transmitter for transmitting the packet.

In addition, the packet processing apparatus according to the present invention comprises a framer for generating and restoring an Ethernet packet frame; An SPI bridge that receives the framer's packet and converts the packet by removing the preamble of the packet or removing the FCS; The SPI bridge, comprising a first network processor and a second network processor, using only one of the first network processor and the second network processor, or using both the first and second network processors; A network processor for performing a single packet processing for ingress and egress and processing each packet for ingress or egress for a packet input from the network; A switch connected to the network processor and configured to interface with a switch fabric; And a processor controlling the SPI bridge and the network processor.

In addition, according to the present invention, the packet processing method of the spiabridge removes the preamble of the packet corresponding to the packet mode of the received packet, extracts a destination address by analyzing the header of the packet, and extracts the extracted destination address. Retrieving a key value, generating an index according to the result, removing the FCS of the packet or filtering the packet corresponding to the value of the index, and transmitting the packet.

According to the present invention, the spiabridge, the packet processing apparatus and the method support the Ethernet FCS removal and packet mode for the packet processing transmitted to the POS line card through the switch fabric in hardware, thereby enabling the micro code of the network processor to be used. The design efficiency of the network processor is maximized even if the design is not done differently, and it is configured to process the packet using a single line card, thereby reducing the cost of manufacturing and greatly improving the performance.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram referred to for the description of the configuration of the spiabridge according to an embodiment of the present invention.

Referring to FIG. 1, the SPI bridge 310 according to the present invention includes an SPI receiver 311, a mode selector 312, a frame analyzer 313, an LU controller 314, an FCSchop controller 315, and a skid buffer ( 316, the SPI first and second transmitters 317 and 318, and the control state raster 319.

The SPI receiver 311 receives a packet input through a data link interface with the framer 320. At this time, the SPI receiver 311 receives a packet and an ingress packet input through an SPI interface from a 1 Gigabit Ethernet or 10 Gigabit Ethernet Media Access Control (MAC) chip to a 64-bit internal bus. And generate various data control signals.

The mode selector 312 converts the SPI interface into an internal bus for internal logic to recognize and selects whether the interface is in burst mode or framing mode.

The mode selector 312 selects a mode whether the input packet is a burst mode or a framing mode according to the control of the control state register 319 and adjusts a start point of a packet (SOP) accordingly. At this time, the framing mode is a mode in which an Ethernet preamble is included and constructed and transmitted as a complete frame. When the framing mode is selected, the mode selector 312 removes the Ethernet preamble and adjusts the SOP position.

The frame analyzer 313 analyzes the header of the input packet to check whether the packet is forwarded to the uplink Packet over Sonet (POS) line card or the downlink. At this time, the frame analyzer 313 analyzes the header to perform layer 2 related processing including padding removal, extracts the destination address, and transmits the extracted destination address to the LU controller 314. In addition, the frame analyzer 313 transmits the resulting index to the FCS chop controller 316 after the lookup of the LU controller 314.

The LU controller 314 looks up the destination address extracted from the frame analyzer 313 as a key value, checks whether it is forwarded to the uplink POS or transmitted to the downlink Ethernet, and generates a control signal accordingly. At this time, an index is generated as a search result.

The FCSChop controller 315 determines whether to remove the Ethernet FCS according to the result generated from the LU controller 314 and adjusts an end of packet (EOP). At this time, the FCSChop controller 315 changes the End of Packet (EOP) when the FCS is removed. In this case, the FCS is a field included in the header of the packet, and is a portion in which the order of data is recorded.

In addition, when the FCS is maintained, the FCSChop controller 315 checks and marks an FCS error and filters the packet based on the Maximum Receive Unit (MRU) packet size, Ethernet destination address filtering, source port, VLAN ID, and Ethernet source address. Perform Ethernet Source Address filtering.

The Skid buffer 316 performs the back pressure processing by the buffer control when the back pressure for each port is generated by the FIFO control inside the receiving end of the external network processor or the SPI first and second transmitters 317 and 318. Save it.

The SPI first and second transmitters 317 and 318 convert the 64-bit internal data bus and control signals into an SPI interface, and transmit the processed packet to an external network processor or processor.

The control state register unit 319 updates the internal lookup table and provides an interface with the register control and the processor 340. At this time, the control status register unit 319 has a memory access such as a read / write register and a dual port RAM (DPRAM) and an interface with an external processor, and decodes an input address to chip select and read / write the register of each module. Generates the enable signal.

2 is a block diagram referred to for the description of the configuration of the packet processing apparatus including the spiabridge according to the embodiment of the present invention.

Referring to FIG. 2, the packet processing apparatus 300 configures a line card including the SPI bridge 310 of FIG. 1.

The packet processing apparatus 300 performs single packet processing for the framer 320, the SPI bridge 310, ingress and egress, which generate and restore Ethernet packet frames, or each packet for ingress or egress. First and second network processors 331 and 332 to perform processing, a switch 350 to interface with a switch fabric of a system, and a processor 340 to control a packet processing apparatus.

In this case, the packet processing apparatus 300 may process the packet using both the first and second network processors 331 and 332, or may process the packet using only one.

When the packet is processed using only the first network processor 331, the packet in the physical link is input to the SPI bridge 310 via the framer 320. The SPI bridge 310 processes the packet through the configuration as shown in FIG. 1 and outputs the packet to the first network processor 331. The first network processor 331 applies the packet to the switch 350 to be sent. Meanwhile, the packet received by the switch 350 is delivered to the framer 320 through the first network processor 331 and transmitted to the physical link.

When both the first and second network processors 331 and 332 are used, a packet of a physical link is delivered to the framer 320, and the framer 320 inputs the packet to the SPI bridge 310. The SPI bridge 310 transmits the first and second network processors 331 and 332 through the SPI first and second transmitters 317 and 318. Packets processed by the network processor are transmitted to the outside through the switch 350. In this case, the packet input to the second network processor 332 is re-input to the first network processor 331 and transmitted to the outside through the switch 350.

The packet received through the switch 350 is transmitted to the framer 320 through the first network processor 331 and to the physical link through the framer.

3 is a diagram referred to for the description of the first embodiment of packet conversion of the SPI bridge according to the embodiment of the present invention.

In the SPI bridge of FIG. 1 described above, the conversion of the Ethernet (IP over Ethernet) packet is determined whether the preamble is removed depending on whether the interface type with the framer 320 supports the burst mode or the framing mode. Packet conversion also depends on whether or not to remove the Ethernet FCS 4 bytes to support the interface with the POS line card.

Referring to FIG. 3, FIG. 3A is a diagram illustrating packet conversion of an Untagged IP-over-Ethernet, and FIG. 3B is a VLAN tagged Ethernet packet. -VLAN-tagged Ethernet packet conversion.

At this time, the mode selector 312 of the SPI bridge selects whether an input packet is a burst mode or a framing mode. In the framing mode, the preamble is removed, and thus the packet start position is changed to adjust the SOP.

The untagged Ethernet packet shown in (a) of FIG. 3 is determined by a value of 0x0800 in the type field of the Ethernet header, and the VLAN tagged Ethernet packet of (b) of FIG. 3 corresponds to a value of 0x8100 in the type field of the Ethernet header. It is determined by the values 421 and 422 of 0x0800 of the second type field.

Each packet of FIGS. 3 (a) and 3 (b) is configured so that the interface of the framer 320 supports the framing mode and the Ethernet preamble is removed to transmit the interface with the downlink Ethernet line card. The packet is converted. As shown in FIGS. 3A and 3B, the preambles 415 and 425 of each packet are removed during packet conversion.

In this case, the untagged Ethernet packet is packet format A, and the VLAN tagged Ethernet packet is packet format B.

4 is a diagram referred to for describing the second embodiment of the packet conversion of the SPI bridge according to an embodiment of the present invention.

FIG. 4A is a diagram illustrating packet conversion of an untagged Ethernet LLC packet (IEEE 802.3 / 802.2), and FIG. 4B is a VLAN tagged LLC packet (IEEE 802.3 / 802.2). Is a diagram illustrating packet conversion.

Referring to Figs. 4A and 4B, the untagged Ethernet LLC packet and the VLAN tagged LLC packet are assigned to the upper layer protocol type based on the defined DSAP values 431, 432, 441 and 443, respectively. Separate.

The frame analyzer 313 and the LU controller 314 determine whether the packet is forwarded to the uplink POS line card or the downlink through the header analysis, and the FCSChop controller 315 determines whether the packet forwarding is performed. Determine if the FCS is removed and adjust the position of End of Packet (EOP).

Untagged Ethernet LLC packets and VLAN tagged LLC packets are packet converted such that the interface of framer 320 is in burst mode and is transmitted by removing the FCS field for interfacing with the POS line card. That is, the FCS fields 435 and 445 are removed by the FCSChop controller 315, and the EOP position is adjusted accordingly.

In this case, the untagged Ethernet LLC packet is packet format C, and the VLAN tagged LLC packet is packet format D.

5 is a diagram referred to for the description of the third embodiment of packet conversion of the SPI bridge according to the embodiment of the present invention.

FIG. 5A illustrates packet conversion of an untagged Ethernet SNAP packet (IEEE 802.3 / 802.2 SNAP), and FIG. 4B illustrates a VLAN tagged LLC packet (IEEE 802.3 / 802.2). A diagram relating to packet conversion of SNAP).

Referring to Figs. 5A and 5B, an untagged Ethernet SNAP packet and a VLAN tagged SNAP packet include a three-byte Organizationally Unique Identifier (OUI) 451 (463) and a two-byte PID (Protocol Identifier). 452, 464, to identify the type of higher layer protocol.

The untagged Ethernet SNAP packet and the VLAN tagged SNAP packet are transmitted by removing the Ethernet preamble and the FCS field for the interface of the framer 320 in framing mode and for interfacing with the POS line card.

Accordingly, the untagged Ethernet SNAP packet and the VLAN tagged SNAP packet are removed from the preambles 455 and 465 and the FCS fields 456 and 466 during packet conversion.

At this time, the untagged Ethernet SNAP packet is packet format E, and the VLAN tagged SNAP packet is packet format F.

At this time, the clock displayed on the right side of each packet format in the above-described Figures 3 to 5 represents 1 tick when the actual internal processing.

Looking at the operation according to an embodiment of the present invention configured as described above are as follows.

6 is a flowchart referred to for describing an operation of a packet processing method of an SPI bridge according to an embodiment of the present invention.

Referring to FIG. 6, an input packet is received from the framer 320 to the SPI receiver 311 (S510). The SPI receiver 311 converts the input packet into a 64-bit bus and transmits the received packet to the mode selector 312.

The mode selector 312 checks whether the packet mode according to the interface with the framer 320 is a burst mode or a framing mode (S520). At this time, the mode selector 312 selects the mode under the control of the control state register 319.

If the packet mode is the framing mode, the mode selector 312 removes the preamble of the packet (S530) and adjusts the position of the start of packet (SOP) accordingly (S540). On the other hand, if the packet mode is burst mode, the separate preamble deletion is not performed.

The frame analyzer 313 receiving the packet extracts the destination address through header analysis and transfers the result to the LU controller 314. At this time, the LU controller 314 searches for the destination address extracted from the frame analyzer 313 as a key value (Lookup) (S550). At this time, the LU controller 314 checks whether the packet is forwarded to the uplink POS or the downlink Ethernet and transmits a signal to the frame analyzer 313. The frame analyzer 313 transmits the index, which is a search result of the LU controller 314, to the FCSChop controller 316.

The FCSChop controller 316 determines whether to remove the FCS according to whether the received index is enabled (S560).

If the index is enabled, the FCS is removed by four bytes for forwarding to the uplink POS line card (570), and the position of the end of packet (EOP) is aligned accordingly (S580).

If the index is not enabled, the packet is filtered because it is transmitted to the downlink Ethernet (S590).

In this case, the packet filtering checks and marks an FCS error, and filtering for a maximum receive unit (MRU) packet size, Ethernet destination address filtering, Ethernet source address filtering based on a source port, a VLAN ID, and an Ethernet source address is performed.

The FCS remove or filtered packet is input to the Skid buffer 316 (S600).

The skid buffer 316 checks whether the back pressure for each port is enabled (S610). In this case, when the back buffer for each port is enabled, the back buffer for each port is generated by the FIFO control of the receiving end of the external network processor or the SPI first and second transmitters 317 and 318. The back pressure process is performed by the buffer control and the input packet is stored to hold the packet data (S620).

On the other hand, if the back buffer per port is not enabled, the Skid buffer 316 transmits the packet to the SPI first and second transmitters 317 and 318 so as to be transmitted (S630).

Therefore, SPIABRIDGE, the packet processing apparatus, and the method thereof support the Ethernet FCS removal and packet mode provided by the framer for packet processing transmitted from the SPI bridge to the POS line card through the switch fabric. Since the packet processing device is configured including the bridge, it is possible to process the packet using a single line card without having to design it individually, thereby reducing the production cost and maximizing the use efficiency of the network processor. Is improved.

As described above, the spiabridge, the packet processing apparatus and the method thereof according to the present invention have been described with reference to the illustrated drawings. However, the present invention is not limited thereto by the embodiments and drawings disclosed herein, and the present invention belongs to It can be applied by those skilled in the art.

1 is a block diagram referred to for description of the configuration of the SPI bridge according to an embodiment of the present invention;

2 is a block diagram referred to for explaining a configuration of a packet processing apparatus including an SPI bridge according to an embodiment of the present invention;

3 is a reference to the description of the first embodiment of packet conversion of the SPI bridge according to the embodiment of the present invention;

4 is a reference to the description of the second embodiment of the packet conversion of the SPI bridge according to the embodiment of the present invention;

5 is a reference to the description of the third embodiment of the packet conversion of the SPI bridge according to the embodiment of the present invention;

6 is a flowchart referred to for describing an operation of a packet processing method of an SPI bridge according to an embodiment of the present invention.

<Explanation of symbols on main parts of the drawings>

310: SPI bridge 311: SPI receiver

312: mode selector 313: frame analyzer

314: LU controller 315: FCSChop controller

316: Skid buffer 317: SPI first transmission unit

318: SPI second transmitter 320: framer

331,332: network processor 340: processor

Claims (14)

A mode selector for selecting a packet mode of the received packet and removing the preamble of the packet corresponding to the selected packet mode; A frame analyzer for analyzing the packet and extracting a destination address; An LU controller searching for the extracted destination address by a key value and checking whether the packet is forwarded to the uplink or transmitted to the downlink Ethernet, and generating the index as an index and delivering the result to the frame analyzer; An FCSChop controller for removing the FCS of the packet or filtering the packet in response to the index value; And, SPI bridge, characterized in that it comprises an SPI transmitter for transmitting the packet. The method of claim 1, It further includes a control status register for updating the LU table, decoding the input address to generate a control signal according to the chip selection, read and write settings in the register of each module, And the mode selector selects whether the packet is a burst mode or a framing mode including a preamble in response to a control signal of the control state register. The method of claim 2, The mode selector removes the Ethernet preamble included in the packet when the packet mode of the packet is a framing mode, and adjusts a start position of a packet (SOP). The method of claim 2, And the frame analyzer extracts a destination address by analyzing the header of the packet and performing processing on Layer 2 including padding removal. The method of claim 1, When the index value generated from the LU controller is enabled, the FCS Chop controller removes the Ethernet FCS of the packet and adjusts an end of packet (EOP) of the packet. Eye Bridge. The method of claim 5, wherein When the FCS of the packet is maintained, the FCS Chop controller checks and marks an FCS error, filters on a Maximum Receive Unit (MRU) packet size, filters an Ethernet destination address, and a source port. Espiai bridge, characterized in that filtering for the Ethernet source address based on the VLAN ID, Ethernet source address (Source Address). The method of claim 1, If the receiving end of the network processor to which the packet is transmitted from the SPI transmitter or the FIFO inside the SPI transmitter is full or a back pressure for each port is generated by control, a back pressure process is performed by a buffer control and the input packet is stored. An Espiai bridge, characterized in that it further comprises a Skid buffer. A framer for generating and restoring an Ethernet packet frame; An SPI bridge that receives the framer's packet and converts the packet by removing the preamble of the packet or removing the FCS; The SPI bridge, comprising a first network processor and a second network processor, using only one of the first network processor and the second network processor, or using both the first and second network processors; A network processor for performing a single packet processing for ingress and egress and processing each packet for ingress or egress for a packet input from the network; A switch connected to the network processor and configured to interface with a switch fabric; And And a processor for controlling the SPI bridge and the network processor. Removing the preamble of the packet corresponding to the packet mode of the received packet; Analyzing a header of the packet to extract a destination address, retrieving the extracted destination address by a key value, and generating an index according to the result; Removing the FCS of the packet or filtering the packet corresponding to the value of the index; And, The packet processing method of the spy bridge, characterized in that it comprises the step of transmitting the packet. The method of claim 9, The preamble removing step further includes selecting a packet mode whether the packet is a burst mode or a framing mode including a preamble. And removing the preamble of the packet if the packet mode is a framing mode and maintaining the burst mode in the burst mode. The method of claim 10, And removing the preamble of the packet, adjusting a packet start position (SOP) of the packet. The method of claim 9, The index generation step further comprises the step of retrieving the destination address by a key value, and checking whether the packet is forwarded uplink or downlink Ethernet. The method of claim 12, After the index generation step, If the packet is forwarded uplink, further comprising setting the index value to enabled; And removing the FCS of the packet by 4 bytes when the index value is enabled, and filtering the packet when the index value is transmitted through the Ethernet which is the downlink. The method of claim 9, The packet transmission step If the back pressure for each port is generated in the transmission means for transmitting the packet to the outside, the packet processing method of the spy bridge further comprising the step of performing the back pressure processing by the buffer control and storing and maintaining the packet. .

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