KR100924633B1 - Method of manufacturing a semiconductor memory device - Google Patents

Abstract

The present invention provides a semiconductor substrate having a device isolation layer and a gate pattern formed thereon, including filling an insulating film between the gate patterns, forming a support layer pattern on the insulating film and the gate pattern, removing the insulating film, and a gate pattern. And forming a capping film along the surface of the semiconductor substrate, and performing an etching process so that the capping film remains on the sidewall of the gate pattern.

Gate pattern, slope, support film, nitride film, insulating film, isotropic etching process, anisotropic etching process

Description

Method of manufacturing a semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device capable of improving the inclination of a gate pattern in a subsequent process by forming a support layer pattern on a gate pattern.

In general, a semiconductor memory device may be divided into an active region where a memory device is formed and an isolation region that isolates the memory devices. Among them, a gate insulating film, a first gate electrode film, a second gate electrode film, and a hard mask pattern are formed on the active region. As the degree of integration of semiconductor devices increases, a semiconductor device having a dual recess structure having a plurality of recess structures in an active region is manufactured to compensate for short channel characteristics. The dual recess structure forms a plurality of (e.g., two) trenches in the active region and forms a gate electrode film pattern on each trench, even if the width of the gate pattern and the gap between the gate patterns become narrow. The channel region may be formed longer than the width.

On the other hand, as the degree of integration of semiconductor devices increases, the width of the gate becomes narrower. As the width of the gate becomes narrower, it becomes difficult to support the gate pattern perpendicularly to the semiconductor substrate. In particular, high temperature heat is applied during the capping film formation process performed after the gate patterning process, and the thin and high gate pattern may be inclined sideways while losing the force supporting the vertical state.

The inclined gate pattern may cause a bridge when adjacent gates come into contact with each other, and may make a subsequent gap fill process difficult by narrowing the upper width between the gate patterns even if they do not contact each other.

According to the present invention, a support layer is formed on the gate pattern so that each gate pattern is supported by the support layer pattern, thereby preventing the gate patterns from tilting during a subsequent high temperature process.

A method of manufacturing a semiconductor memory device according to the present invention provides a semiconductor substrate on which an element isolation film and a gate pattern are formed. An insulating film is filled between the gate patterns. A support layer pattern is formed on the insulating layer and the gate pattern. Remove the insulating film. A capping film is formed along the surface of the semiconductor substrate including the gate pattern. A method of manufacturing a semiconductor memory device comprising performing an etching process such that a capping film remains on sidewalls of a gate pattern.

In the process of performing the etching process so that the capping layer remains, the support layer pattern is also removed, and the forming of the gate pattern includes forming a gate conductive layer, a barrier layer, a gate electrode layer, and a hard mask pattern on the semiconductor substrate on which the device isolation layer is formed. Form. Patterning the gate electrode layer and the barrier layer by performing an etching process according to the hard mask pattern.

An etching process is performed such that the capping film remains on the sidewall of the gate pattern, and the exposed gate conductive film is patterned.

In the step of filling the insulating film, an insulating film is formed on the semiconductor substrate to fill the gap between the gate patterns. Polishing the insulating layer to expose the upper portion of the gate pattern.

The insulating film is formed of an oxide film, and the supporting film pattern forming step forms a supporting film on the insulating film and the gate pattern. An antireflection film and a hard mask pattern are formed on the support film. The antireflection film and the support film are patterned according to the hard mask pattern. Removing the hard mask pattern and the anti-reflection film.

The hard mask pattern has a pattern in which the device isolation region is open, and the support film pattern is formed of a nitride film. At this time, the support film pattern is formed to a thickness of 50 kPa to 100 kPa.

The process of removing the insulating film is performed by an isotropic wet etching process, and the capping film is formed by chemical vapor deposition (CVD).

According to an exemplary embodiment of the present invention, the support pattern may support the gate pattern, thereby preventing the gate pattern from being inclined during a process requiring high temperature, and increasing the degree of integration of the gate pattern. For this reason, bridge | bridging generation between adjacent gate patterns can be suppressed and a gap fill process can be performed easily by preventing the space | interval between gate upper parts becoming narrow.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to the present invention, and FIGS. 2A to 2G are layout views illustrating a method of manufacturing a semiconductor memory device according to the present invention. In particular, FIGS. 1A to 1G are cross-sectional views illustrating a cross section taken along the line AA ′ in FIGS. 2A to 2G.

1A and 2A, a semiconductor substrate 100 is provided in which an active region 100a is defined and an isolation layer 102 of an insulating layer is formed in an isolation region. A trench 103 is formed in the active region 100a. A gate insulating film 104 is formed along the surface of the semiconductor substrate 100 on which the trench 103 is formed. The gate insulating film 104 may be formed of an oxide film, and the gate conductive film 106, the barrier layer 108, the gate electrode film 110, and the hard mask pattern 112 are sequentially formed on the gate insulating film 104. do. The gate conductive film 106 is preferably formed of a polysilicon film, and the barrier layer 108 may be formed using WN or TiN. The gate electrode film 110 may be formed of a metal film. For example, the metal film is preferably formed of tungsten (W).

An etching process is performed according to the hard mask pattern 112 having the gate line pattern to pattern the gate electrode layer 110 and the barrier layer 108 in the form of a gate line. A portion of the gate conductive film 106 is exposed between the gate electrode films 110 by the patterning process. The gate conductive layer 106 is later patterned to reduce abnormal oxidation of tungsten during the etching process.

1B and 2B, an insulating layer 114 is formed to fill all of the hard mask patterns 112. The insulating film 114 may be formed of an oxide film. Specifically, the hard mask pattern 112 may be formed to fill the insulating film 114, and then a chemical mechanical polishing (CMP) process may be performed to remove a portion of the insulating film 114. At the same time as the upper portion of the 112 is exposed, the insulating film 114 remains only on the gate conductive film 106 between the hard mask patterns 112. A support layer 116 is formed on the semiconductor substrate 100 where the hard mask pattern 112 is exposed to prevent the gate pattern from tilting. The support film 116 is preferably formed to have a thickness of 50 kPa to 100 kPa using a nitride film.

Referring to FIGS. 1C and 2C, an anti-reflection film 118 is formed on the support layer 116 for the exposure process, and an open area for removing a portion of the support layer 116 on the anti-reflection layer 118. The mask pattern 120 on which the 120a is formed is formed.

An etchant is supplied when the insulating layer 114 is removed in a subsequent process through the open region 120a of the mask pattern 120, and may open any one of the active region 100a or the device isolation layer 102. . In the drawing, as an example, the mask pattern 120 having the open region 120a formed on the device isolation layer 102 is used.

1D and 2D, an anti-reflection film 118 and a support film 116 are patterned by performing an etching process according to the mask pattern 120. As a result, a portion of the insulating layer 114 and the hard mask pattern 112 formed on the device isolation layer 102 are exposed through the open region 120a of FIG. 2C. Next, the mask pattern 120 and the anti-reflection film 118 are removed. As a result, the support layer pattern 116a remains on the active region 100a. The hard mask pattern 112 and a part of the insulating film 114 are exposed in the open region of the support layer pattern 116a.

1E and 2E, an etching process is performed to remove the insulating film 114 (FIG. 1D) remaining between the hard mask patterns 112. The etching process is preferably performed by a wet etching process having a high etching selectivity with respect to the insulating film. Since the wet etching process is an isotropic etching process, the etching solution is supplied through the open region of the support layer pattern 116a to remove all of the insulating layer 114 (refer to FIG. 1D) formed under the support layer pattern 116a. Therefore, the support layer pattern 116a remains on the hard mask pattern 112 formed in the active region 100a to support the hard mask pattern 112.

1F and 2F, the capping layer 122 is formed along the surface of the semiconductor substrate 100 on which the support layer pattern 116a remains. The capping film 122 is formed to prevent abnormal oxidation of the gate electrode film 110 formed of tungsten (W). The capping film 122 may be formed of a nitride film, and is preferably formed by chemical vapor deposition (CVD). Chemical Vapor Deposition (CVD) has a high step coverage and can easily form a layer between fine patterns. By using this, a capping film (up to the surface of the pattern formed under the support layer pattern 116a) can be formed. 122) can be formed evenly.

In the process of forming the capping layer 122 using chemical vapor deposition (CVD), high temperature heat is applied, and a thin and high gate pattern may be inclined due to the high temperature. However, since the support layer pattern 116a formed on the gate patterns (eg, the hard mask pattern 112) supports the hard mask pattern 112 at the top, it is possible to prevent the gate pattern from tilting. have.

Specifically, referring to FIG. 2E, the support layer pattern 116a supports the hard mask pattern 112 on the top of the hard mask pattern 112, thereby fixing the hard mask patterns 112. Therefore, even in a process requiring a high temperature, the gate pattern may not be inclined and may maintain a vertical structure with the semiconductor substrate 100.

1G and 2G, the gate conductive layer 106 is patterned to form a gate pattern. It is preferable to perform a patterning process by an anisotropic dry etching process. Specifically, an anisotropic dry etching process is performed to remove the remaining capping layer 122 and the support layer pattern 116a of FIG. 1F except for the capping layer 122 on the sidewall of the gate pattern. Next, the exposed gate conductive layer 106 is patterned to expose a portion of the active region 100a and the device isolation layer 102.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to the present invention.

2A to 2G are layout views illustrating a method of manufacturing a semiconductor memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 100a active region

102 device isolation film 104 gate insulating film

106: gate conductive film 108: barrier layer

110: gate electrode film 112: hard mask pattern

114: insulating film 116: support film

118: antireflection film 120: mask pattern

122: capping film

Claims (13)

Providing a semiconductor substrate having a device isolation layer and a gate pattern formed thereon; Filling an insulating film between the gate patterns; Forming a support layer pattern on the insulating layer and the gate pattern; Removing the insulating film; Forming a capping film along a surface of the semiconductor substrate including the gate pattern; And And performing an etching process such that the capping layer remains on sidewalls of the gate pattern. The method of claim 1, And removing the support layer pattern during the etching process such that the capping layer remains. The method of claim 1, wherein the forming of the gate pattern comprises: Forming a gate conductive layer, a barrier layer, a gate electrode layer, and a hard mask pattern on the semiconductor substrate on which the device isolation layer is formed; And And etching the gate electrode layer and the barrier layer by performing an etching process according to the hard mask pattern. The method of claim 3, wherein After performing the step of patterning the barrier layer, And etching the exposed gate conductive layer so that the capping layer remains on sidewalls of the gate pattern. The method of claim 1, wherein the filling of the insulating layer comprises: Forming an insulating film on the semiconductor substrate to fill the gaps between the gate patterns; And And polishing the insulating layer to expose an upper portion of the gate pattern. The method of claim 1, And the insulating film is formed of an oxide film. The method of claim 1, wherein the supporting film pattern forming step, Forming a support layer on the insulating layer and the gate pattern; Forming an anti-reflection film and a hard mask pattern on the support layer; Patterning the anti-reflection film and the support film according to the hard mask pattern; And Removing the hard mask pattern and the anti-reflection film. The method of claim 7, wherein And the hard mask pattern has a pattern in which device isolation regions are open. The method of claim 1, The support film pattern is a semiconductor memory device manufacturing method of forming a nitride film. The method of claim 1, The support film pattern is a semiconductor memory device manufacturing method to form a thickness of 50 ~ 100Å. The method of claim 1, The process of removing the insulating film is a method of manufacturing a semiconductor memory device performed by an isotropic wet etching process. The method of claim 1, The capping film is formed by chemical vapor deposition (CVD). Forming a gate pattern on the semiconductor substrate; Filling an insulating film between the gate patterns; Forming a support layer pattern on the gate pattern and the insulating layer to overlap the gate patterns adjacent to each other and partially expose the insulating layer; And And removing the insulating layer exposed between the support layer patterns while remaining the support layer pattern formed on the gate pattern.

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