KR100923349B1 - Ferroelectric liquid crystal display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field alignment method for ferroelectric liquid crystals and a liquid crystal display device using the same to reduce an excessive load or damage of a driving circuit in a field alignment process performed in a state in which a driving circuit used in normal driving is mounted. A data driving circuit for supplying data to the field, a power supply for generating an electric field alignment voltage, a switch element connected between the data driving circuit and the data line, and a power supply connected between the switch element and the power supply. A voltage on the bus line in response to a voltage on the bus line in an electric field orientation, including a bus line for supplying a voltage from the switch element to the switch element, And a switch circuit for blocking current paths between the data lines.

Description

Ferroelectric liquid crystal display {FERROELECTRIC LIQUID CRYSTAL DISPLAY}

1 is a graph showing voltage vs. transmittance characteristics of a ferroelectric liquid crystal in a V switching mode.

FIG. 2 is a diagram illustrating a phase transition process of ferroelectric liquid crystals in a half V switching mode.

FIG. 3 is a diagram illustrating a change in molecular arrangement according to field alignment in ferroelectric liquid crystals of a half V switching mode.

4A and 4B are graphs showing voltage vs. transmittance characteristics of a half V switching mode.

FIG. 5 is a diagram illustrating a ferroelectric liquid crystal in a half-v switching mode that responds to an electric field during electric field alignment and an electric field applied during driving.

6 is a block diagram illustrating a liquid crystal display according to a first embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating the data driver circuit shown in FIG. 6 in detail.

FIG. 8 is a circuit diagram illustrating a gamma circuit of the gamma circuit chip illustrated in FIG. 6.                 

FIG. 9 is a graph illustrating a gamma voltage output from the gamma circuit chip illustrated in FIG. 6.

FIG. 10 is a circuit diagram illustrating a voltage input to the digital-analog converter shown in FIG. 7.

11 is a block diagram illustrating a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 12 is an arc diagram showing a first embodiment of the electric field orientation / normal drive switch circuit shown in FIG.

FIG. 13 is an arc diagram showing a second embodiment of the electric field orientation / normal drive switch circuit shown in FIG.

FIG. 14 is an arc diagram showing a third embodiment of the electric field orientation / normal drive switch circuit shown in FIG.

         <Explanation of symbols for the main parts of the drawings>

60: timing controller chip 61: gamma circuit chip

62: liquid crystal panel 63: data TCP

64: Data Drive Chip 65: Source PCB

66: gate TCP 67: gate drive chip

68: gate PCB 69: power circuit

65a, 68a: Vcom terminal 65b, 68b: GND terminal

81: first latch 82: shift register                 

83: second latch 84: digital-to-analog converter

85: buffer 100: timing controller

101: data driving circuit 103: gate driving circuit

104: electric field orientation / normal drive switch circuit 105: switch

NT: N type MOS-FET PT: P type MOS-FET

D: Diode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a ferroelectric liquid crystal display device which reduces excessive load or damage of a driving circuit during an electric field alignment process performed in a state where a driving circuit used for normal driving is mounted.

The liquid crystal display device displays an image by applying an electric field to the liquid crystal corresponding to the video signal to control the arrangement of the liquid crystal to adjust the light transmittance according to the video signal. Such a liquid crystal display includes a liquid crystal panel in which liquid crystal is injected between two glass substrates, a light source module (or 'backlight unit') for irradiating light to the liquid crystal panel, and a liquid crystal panel and the light source module integrally. Mechanisms such as a frame and a chassis for fixing, and a printed circuit board (hereinafter, referred to as "PCB") for applying a driving signal to the liquid crystal panel.

The manufacturing process of the liquid crystal display device is divided into substrate cleaning, substrate patterning, substrate bonding / liquid crystal injection, driving circuit mounting process. In the substrate cleaning process, foreign substances contaminated on the surface of the substrate used for the liquid crystal panel are removed using a cleaning agent. In the substrate patterning process, the upper glass substrate is patterned and the lower glass substrate is patterned. A color filter, a common electrode, and a black matrix are formed on the upper glass substrate of the liquid crystal panel, and signal wiring such as data lines and gate lines are formed on the lower glass substrate of the liquid crystal panel, and a thin film is formed at the intersection of the data line and the gate line. A transistor (Thin Film Transistor, hereinafter referred to as "TFT") is formed, and a pixel electrode is formed in the pixel region between the data line and the gate line. The substrate bonding / liquid crystal injection process is a process of coating and rubbing an alignment layer on the substrates of a liquid crystal panel, attaching polarizers having an optical axis orthogonal to each of the upper glass substrate and the lower glass substrate, and using an upper glass by using a sealant. And bonding the substrate and the lower glass substrate, injecting the liquid crystal, and sealing the liquid crystal injection hole. In the driving circuit mounting step, a tape carrier package (hereinafter referred to as "TCP") on which integrated circuits such as a gate drive integrated circuit and a data drive integrated circuit are mounted is connected to a pad portion formed on a lower glass substrate. Such a drive integrated circuit may be directly mounted on the lower glass substrate by a chip on glass (COG) method in addition to the tape automated bonding method using the aforementioned TCP.

When a liquid crystal panel is manufactured by such a manufacturing process, a module assembly process of integrally assembling the liquid crystal panel, the light source module, and the PCB is followed.

In the module assembly process, the PCB, the light source module and the liquid crystal panel are stacked from the bottom of the cavity in the main frame, and the top case is assembled to the main frame so as to surround the side of the main frame and the edge of the liquid crystal panel. In some cases, a bottom case disposed between the main frame and the top case and surrounding the bottom of the main frame is assembled to the main frame. In TCP, the input terminal is connected to the output pad of the PCB and the output terminal is connected to the signal wiring pad of the liquid crystal panel. The light source module includes a cold cathode lamp (CCFL) and a light guide plate, and includes optical sheets such as a prism sheet and a diffusion plate stacked between the light guide plate and the liquid crystal panel.

The liquid crystal injected into the liquid crystal display is an intermediate state between a liquid and a solid having both fluidity and elasticity. The liquid crystal most commonly used in liquid crystal displays until now is the twisted nematic mode (hereinafter referred to as "TN mode").

Such a TN mode has a disadvantage of slow response time and a narrow viewing angle. In contrast, ferroelectric liquid crystals (FLCs) have fast response speeds and have wide viewing angle characteristics, and thus, research on them has been actively conducted in recent years. In detail, the ferroelectric liquid crystal has a layer structure having regions of the same electrical and magnetic properties, and is driven in-plane while rotating along a virtual cone in response to an electric field. Since the ferroelectric liquid crystal has a permanent polarization, that is, spontaneous polarization even without an external electric field, when the external electric field is applied like a magnet-magnet interaction, the ferroelectric liquid crystal rapidly rotates due to the interaction of the external electric field and the spontaneous polarization. The response speed is several hundred times to several thousand times faster than the liquid crystal of other modes. In addition, the ferroelectric liquid crystal may implement a wide viewing angle without the need for a special electrode structure or a compensation film because the liquid crystal itself has an in-plane switching characteristic (In Plane Swithching). The ferroelectric liquid crystal is divided into a V-switching mode and a half V-switching mode according to a characteristic of reacting in response to the polarity of the electric field.

Ferroelectric liquid crystal cell of V switching mode isotropic → Smectic A Phase (S _A ) → Smectic X Phase (Sm X *) → Crystal Thermodynamic phase transition is achieved. Here, in the isotropic phase, the liquid crystal molecules have no orientation and positional order, and the Smectic A phase has liquid crystal molecules separated into a virtual layer, is aligned perpendicular to the virtual layer, and has symmetry above and below. The Smectic X phase is intermediate between the Smectic A phase and the crystalline state. In the V-switching ferroelectric liquid crystal cell in which the liquid crystal molecules are phase-transferred into the Smectic X phase, as shown in FIG. The light transmittance NT is increased.

By the way, ferroelectric liquid crystal cell of V-switching mode has high speed response and wide viewing angle, but because of its high spontaneous polarization value, the capacitance of storage capacitor to maintain high data voltage and high effective power for driving liquid crystal cell This has the disadvantage of getting bigger. Therefore, when the liquid crystal of the V switching mode is applied to the liquid crystal display device, the power consumption of the liquid crystal display device is increased and the electrode area of the auxiliary capacitor is increased, resulting in a decrease in the aperture ratio.

On the other hand, the ferroelectric liquid crystal cell of the half V switching mode not only has high-speed response characteristics and wide viewing angle characteristics, but also has a small capacitance value, which is advantageous for displaying moving images and is more suitable for implementing liquid crystal displays. The ferroelectric liquid crystal cell of the half V switching mode has a temperature below the transition temperature (Tni) that causes a phase transition from an isotropic phase to a nematic phase (N *) and a smectic C phase (N *) as shown in FIG. 2. Smectic C Phase: Sm C *) isotropic as the temperature is lowered to the transition temperature (Tsn) that causes the phase transition to Sm C *) and the transition temperature (Tcs) that causes the phase transition to crystals from the Smectic C phase (Sm C *). ¡Æ the nematic phase (N *) → the Smectic C Phase (Sm C *) → the crystal (Crystal) is a thermodynamic phase transition.

A method of manufacturing a liquid crystal cell of a half V switching mode in relation to the phase transition process of the ferroelectric liquid crystal will be described in detail with reference to FIG. 3. The ferroelectric liquid crystal is injected into the cells oriented in parallel at the initial temperature of the isotropic phase without orientation and position order. When the temperature is lowered from the isotropic phase to a predetermined temperature, the ferroelectric liquid crystal becomes a nematic phase (N *) oriented in parallel with the rubbing direction. When the temperature is gradually lowered in the nematic phase (N *) and a sufficient electric field is applied to the inside of the liquid crystal cell, the ferroelectric liquid crystal of the nematic phase (N *) is phase shifted to the Smectic C phase (Sm C *) and the spontaneous polarization direction of the ferroelectric liquid crystal It is arranged to coincide with the electric field direction formed inside the cell.                         

"는 도면과 수직으로 들어가는 방향으로 일치하는 강유전성 액정의 자발분극 방향과 전기장 방향을 나타낸다. As a result, the ferroelectric liquid crystal in the liquid crystal cell has the same electric field direction and its spontaneous polarization direction applied during the electric field alignment among the two possible molecular alignment directions in the parallel alignment process, and has a uniform alignment state as a whole. On the other hand, if there is no electric field alignment process, two molecular arrangements with different layers appear randomly, with a phase transition from nematic phase (N *) to smectic C phase (Sm C *). When the molecular arrangement of the ferroelectric liquid crystal becomes a random bistable state as described above, the ferroelectric liquid crystal is difficult to be uniformly controlled. For this reason, the ferroelectric liquid crystal cell of the half V switching mode applies a DC voltage of several [V] while decreasing the temperature, thereby converting the ferroelectric liquid crystal from the nematic phase (N *) to the smectic C phase (Sm C *). The phase transition causes the ferroelectric liquid crystals to be arranged in a monostable state. In Figure 3

Indicates the spontaneous polarization direction and the electric field direction of the ferroelectric liquid crystal coinciding in the direction perpendicular to the drawing.

The field alignment of the ferroelectric liquid crystal cell in the V switching mode is performed after the substrate bonding / liquid crystal injection process in the above-described manufacturing process. In the case of the field alignment, a data voltage of the liquid crystal panel is commonly connected to a shorting bar and a voltage is applied thereto. Is approved. The common voltage Vcom is applied to the common electrode of the upper glass substrate. At this time, a DC voltage of several [V] is applied to the ferroelectric liquid crystal by a common voltage applied to the common electrode and a voltage applied to the pixel electrode via the data lines.

4A and 4B are graphs illustrating a change in light transmittance according to voltage in a ferroelectric liquid crystal cell of a half V switching mode.

Referring to FIG. 4A, the ferroelectric liquid crystal cell of the half V switching mode is polarized by incident light only when a positive voltage (+ V) is applied when an electric field is oriented by a negative voltage (−V) or a negative electric field. When the incident light is transmitted by changing the direction by 90 ° and a negative voltage (-V) is applied, the polarized light direction of the incident light is maintained to almost block incident light. The light transmittance is increased in proportion to the intensity of the positive electric field E (+) and is maintained at the maximum value when the intensity of the electric field E (+) becomes larger than a predetermined threshold. On the contrary, if the ferroelectric liquid crystal cell of the half V switching mode is oriented by the positive voltage (+ V) or the positive electric field, the incident light is transmitted only when the negative voltage (-V) is applied as shown in FIG. When a positive voltage (+ V) is applied, the incident light is almost blocked.

This will be described in detail with reference to FIG. 5.

FIG. 5 shows a change in the ferroelectric liquid crystal array when the negative electric field is applied to the ferroelectric liquid crystal cell of the half-v switching mode and the electric field is aligned, and the ferroelectric liquid crystal array when the positive and negative external electric fields are applied.

Referring to FIG. 5, when the ferroelectric liquid crystal cell of the half V switching mode is oriented by the negative external electric field E (−), the spontaneous polarization direction Ps of the ferroelectric liquid crystal is negative external electric field E (− Uniformly oriented in a direction consistent with)). When the positive external electric field (E (+)) is applied to the ferroelectric liquid crystal cell in the half-v switching mode after the electric field alignment, the alignment of the ferroelectric liquid crystal is changed so that the spontaneous polarization direction (Ps) is the positive external electric field (E (+)). ) Will match. At this time, the polarization direction of the incident light incident from the lower plate of the liquid crystal display device is converted into the polarization direction of the polarizer of the upper plate by the ferroelectric liquid crystal whose arrangement is changed, and the incident light is transmitted through the polarizer of the upper plate. On the other hand, when the negative external electric field (E (-)) is applied or the external electric field is not applied to the ferroelectric liquid crystal cell of the half-V switching mode, the array of the ferroelectric liquid crystals maintains the initial arrangement and the incident light maintains the polarization direction. It will not pass through the polarizer of the top plate.

However, the conventional ferroelectric liquid crystal cell has a problem that the initial alignment is easily damaged by physical shock because the cell gap is about 1.2 μm. For this reason, the ferroelectric liquid crystal display device is liable to be damaged in the initial field orientation in a module assembly process in which physical shock occurs frequently. In order to restore the field alignment of the ferroelectric liquid crystal panel in which the initial alignment is damaged, TCP must be separated from the liquid crystal panel, and the field alignment voltage source is reconnected to the signal lines. Therefore, there is no method for restoring the initial alignment of the ferroelectric liquid crystal panel in which the initial alignment is damaged.

Accordingly, an object of the present invention is to provide a ferroelectric liquid crystal display device which reduces excessive load or damage of a driving circuit during an electric field alignment process performed in a state in which a driving circuit used for normal driving is mounted.

In order to achieve the above object, a ferroelectric liquid crystal display device according to an embodiment of the present invention, a data driving circuit for supplying data to the data lines, a power supply for generating an electric field alignment voltage, the data driving circuit and the data A switch element connected between the lines, and a bus line connected between the switch element and the power source for supplying a voltage from the power supply to the switch element, in response to the voltage on the bus line during electric field orientation. And a switch circuit for supplying a voltage on a bus line to the data lines while blocking a current path between the bus line and the data line during normal operation.

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The ferroelectric liquid crystal display device according to the embodiment of the present invention further includes a second switch circuit that cuts off a current path between the power supply and the data driving circuit at the time of electric field alignment.

The switch circuit includes a switch element connected between the data driving circuit and the data line, and a bus line connected between the switch element and the power supply to supply a voltage from the power supply to the switch element.

The switch element includes an N-type MOS-FET.

The switch element comprises a diode.

The second switch circuit includes a switch element connected between the data driving circuit and the data line, and a bus line connected between the switch element and the power supply to supply a voltage from the power supply to the switch element.

The switch element of the second switch circuit cuts off the current path between the data driving circuit and the data line in response to the voltage on the bus line during the electric field alignment, while forming a current path between the data driving circuit and the data line during normal driving. P-type MOS-FET is included.

The ferroelectric liquid crystal display according to the embodiment of the present invention forms a current path between the power supply and the switch circuit in the electric field orientation, while blocking the current path between the power supply and the switch circuit in the normal operation and between the base voltage source and the switch circuit. It further comprises a switch element for forming a current path.

The switch element is mounted on a printed circuit board on which a data driving circuit is mounted.

Other objects and features of the present invention in addition to the above object will be apparent through the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 14.

Referring to FIG. 6, the ferroelectric liquid crystal display according to the first exemplary embodiment of the present invention includes a liquid crystal panel 62 into which ferroelectric liquid crystal is injected, data lines DL1 to DLm, and a source PCB of the liquid crystal panel 62. A data TCP 63 connected between the gates 65 and a gate TCP 66 connected between the gate lines GL1 to GLn of the liquid crystal panel 62 and the gate PCB 68.

In the liquid crystal panel 62, ferroelectric liquid crystal is injected between two glass substrates 71 and 72. Polarizers having polarization directions orthogonal to each other are attached to the light incident surface of the lower glass substrate 71 and the light exit surface of the upper glass substrate 72. The data lines DL1 to DLm and the gate lines GL1 to GLn formed on the lower glass substrate 71 are perpendicular to each other. The gate electrodes of the TFTs are connected to the corresponding gate lines GL1 to GLn, and the source electrodes are connected to the corresponding data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. In addition, a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal panel 62 to maintain the voltage of the liquid crystal cell Clc. The storage capacitor is formed between the liquid crystal cell Clc connected to the k-th gate line (where k is a positive integer between 1 and n) and the k-1 th front gate lines G1 to Gn-1. It may be formed between the liquid crystal cell Clc connected to the k-th gate line and a separate common line. A black matrix, a color filter, and a common electrode 73 (not shown) are formed on the upper glass substrate 72 of the liquid crystal panel 62. The common electrode 73 is formed of a transparent conductive material such as ITO, IZO, or the like so as to transmit light. The common voltage 73 is supplied to the common electrode 73 via an Ag dot 74 formed on the lower glass substrate 72. In addition, an alignment film (not shown) that is parallelly aligned with each other is formed on each of the upper glass substrate 71 and the lower glass substrate 72 of the liquid crystal panel 62.

The timing controller chip 60 and the gamma circuit chip 61 are mounted on the source PCB 65. The timing controller chip 60 receives the vertical / horizontal synchronization signal and the clock signal to generate timing control signals for controlling the data TCP 63 and the gate TCP 66 and transmits the timing control signals to the data TCP 63. Supply to gate TCP 66. The timing controller chip 60 also supplies digital video data on the source TCP via a number of data buses formed on the source PCB 65. The gamma circuit chip 61 divides the high potential common voltage (Vdd) and the low potential common voltage (Vss) to generate six gamma reference voltages, respectively, and divides each gamma reference voltage to subdivide each gray level. Generates positive / negative analog gamma voltage. The analog gamma voltage generated from the gamma circuit chip 61 is supplied to the data TCP 66. Further, on the small TCP 65, a Vcom terminal 65a for supplying the common voltage Vcom to the liquid crystal panel 62 is formed via the data TCP 66, and the timing formed on the source PCB 65. The GND terminal 65b for supplying the ground voltage GND to the controller chip 60, the gamma circuit chip 61, and the data TCP 63 is formed. The Vcom terminal 65a is connected to the silver dot 74 formed on the lower glass substrate 72 via the wiring formed on the source PCB 65 and the source TCP 63 to connect the common voltage 73 to the common electrode 73. Vcom). In addition, a connector (not shown) for supplying a Vcc common power supply of approximately 3.3 V is connected to the power input terminal of the source PCB 65, and a power supply circuit 69 is mounted on the source PCB 65. The Vcc common power is supplied to the timing controller chip 60 to drive the timing controller chip 60, and to the power supply circuit 69 to drive the power supply circuit 69. The power supply circuit 69 includes a DC / DC converter, a pulse width controller, a pulse frequency controller, and the like, a Vdd voltage of 6 V or more from the Vcc common power supply, a common voltage (Vcom) between 2.5 to 3.3 V, and a negative voltage. A polarity Vss power supply, a VGH voltage of approximately 15 V or more that is a high logic voltage of a scan pulse and a VGL voltage of approximately -4 V or less that is a low logic voltage of a scan pulse are generated.

The data drive chip 64 is mounted on the source TCP 63. The input wiring of the source TCP 63 is connected to the output pad of the source PCB 65 and the output wiring of the source TCP 63 is formed on the lower glass substrate 72 by an anisotropic conductive film (ACF). Connected to the data pad. The data drive chip 64 converts the digital video data supplied from the timing controller chip 60 into a positive or negative analog gamma voltage from the gamma circuit chip 61 and supplies the data lines DL1 to DLm. .

Each of the data drive chips 64 may include a shift register 82, a first latch 81, a second latch 83, and a digitally connected between the input line 70 and the data line DL as shown in FIG. 7. -An analog to analog converter (hereinafter referred to as "DAC") 84 and a buffer 85. The shift register 82 shifts the source start pulse SSP from the timing controller chip 60 in accordance with the source shift clock signal SSC to generate a sampling signal. In addition, the shift register 82 shifts the source start pulse SSP to transfer a carry signal CAR to the next stage shift register 82. The first latch 81 samples the digital data according to the sampling signal input from the shift register 82. The second latch 83 latches the digital data input from the first latch 81 and then simultaneously outputs one horizontal line of data in response to the source output signal SOE from the timing controller chip 60. . The DAC 84 converts the low potential DC voltage VL or the high potential DC voltage VH input from the gamma circuit chip 61 during ferroelectric field alignment. In addition, the DAC 84 converts the digital data from the second latch 83 to the positive analog gamma voltage VPG or the negative analog gamma voltage (VOL) according to the polarity signal POL from the timing controller chip 60 during normal driving. VNG). The buffer 85 outputs the analog gamma voltages VPG and VNG input from the DAC 84 to the data lines D1 to Dm without signal attenuation. In FIG. 7, reference numeral Rs denotes a line resistance between the output terminal of the data drive chip 64 and the data lines D1 to Dm.

The gate PCB 68 is supplied with control signals for controlling the common voltage Vcom, the base voltage GND, the VGH voltage, the VGL voltage, and the gate TCP 66 from the source PCB 65. Similar to the source PCB 65, the gate PCB 68 is provided with the Vcom terminal 68a and the GND terminal 68b. A gate TCP 66 is connected between the output wiring of the gate PCB 68 and the gate pads of the lower glass substrate 72.

The gate drive chip 67 is mounted on the gate TCP 66. The input wiring of the gate TCP 66 is connected to the output pad of the gate PCB 68, and the output wiring of the gate TCP 66 is connected to the lower glass substrate 72 by an anisotropic conductive film (ACF). It is connected to the formed gate pad. The gate drive chip 67 sequentially supplies scan pulses to the gate lines GL1 to GLn in response to a control signal supplied from the timing controller chip 60.

The field alignment method of the ferroelectric liquid crystal display device is described as follows. First, the ferroelectric liquid crystal injected into the liquid crystal panel 62 is injected into the liquid crystal panel 12 in which the upper and lower alignment films are aligned in parallel under an initial temperature of about 100 ° C. Subsequently, the isotropic ferroelectric liquid crystal is changed into the nematic phase N * under a transition temperature Tni of approximately 90 ° C. to 100 ° C. which causes the phase transition from the isotropic phase to the nematic phase N *. Subsequently, when the temperature is further lowered to a transition temperature (Tsn) of about 60 ° C. to 80 ° C. which causes a phase transition from the nematic phase to the Smectic C phase (Sm C *), the arrangement of the ferroelectric liquid crystal is a nematic phase (N *). From Smectic C phase (Sm C *). Under this transition temperature Tsn, field alignment of the ferroelectric liquid crystal is carried out.

In the field orientation of the ferroelectric liquid crystal, the VCC voltage is not supplied to the source PCB 65, and the ferroelectric liquid crystal is provided at the Vcom terminals 65a and 68a and the GND terminals 65b and 68b formed on the source PCB 65 and the gate PCB 68, respectively. DC voltage of approximately several V is applied to electric field orientation. Since the Vcc voltage is not supplied to the timing controller chip 60 and the power supply circuit 69, the common voltages for the divided voltages, that is, the Vdd voltage and the Vss voltage are not supplied to the gamma circuit chip 61.

When the Vdd voltage and the Vss voltage are not supplied to the gamma circuit chip 61 as shown in FIG. 8, the input terminal of the voltage divider circuit including the plurality of voltage divider resistors R1 to R5 is in a floating state. At this time, since no current flows through the divided resistors R1 through R5, the output nodes GMA1 through GMA5 of the gamma reference voltages formed between the divided resistors R1 through R5 are input from the GND terminals 65b and 68b. The DC voltages VL and VH and the equipotential voltage are applied. In addition, DC voltages VL and VH input from the GND terminals 65b and 68b and an equipotential voltage are also applied to the output terminals of the voltage dividing circuits for dividing the gamma voltages again to generate a subdivided gamma voltage. Therefore, the analog gamma voltage supplied from the gamma circuit chip 61 to the data drive chip 64 becomes constant regardless of the gray value of the digital video data supplied to the data drive chip 64 as shown in FIG.

In the field alignment method of the ferroelectric liquid crystal according to the embodiment of the present invention, a high potential DC voltage (VH) is applied to the Vcom terminals 65a and 68a and the low potential DC voltage is applied to the GND terminals 65b and 68b when the ferroelectric liquid crystal is aligned. (VL) is applied. In addition, the electric field alignment method of the ferroelectric liquid crystal according to another embodiment of the present invention applies a low potential DC voltage (VL) to the Vcom terminal (65a, 68a) and the high voltage to the GND terminal (65b, 68b) when the field alignment of the ferroelectric liquid crystal Apply the above DC voltage (VH). The voltage difference between the high potential direct current voltage VH and the low potential direct current voltage VL is set to about a few volts so that the ferroelectric liquid crystal can be oriented.

If a high potential DC voltage VH is applied to the Vcom terminals 65a and 68a and a low potential DC voltage VL is applied to the GND terminals 65b and 68b, the liquid crystal cell Clc formed on the upper glass substrate 71 is applied. The high potential DC voltage VH is applied to the common electrode 73 via the Vcom terminals 65a and 68a and the silver dot 74. At the same time, the low potential DC voltage VL is applied to the pixel electrode of the liquid crystal cell Clc facing the common electrode 73 with the ferroelectric liquid crystal interposed therebetween. At this time, since the timing controller chip 69 is not driven to the data drive chip 64, data is not applied or data selected at random is applied. Since the data applied to the data drive chip 94 is '000000' (or '00000000') or data selected at random in gray level is applied, the data drive chip for converting digital data into an analog gamma voltage as shown in FIG. The digital-analog converter 74 of 64 supplies the low potential DC voltage VL applied to the GND terminals 65b and 68b to the data lines DL1 to DLm as shown in FIG.

On the contrary, if the low potential DC voltage VL is applied to the Vcom terminals 65a and 68a and the high potential DC voltage VH is applied to the GND terminals 65b and 68b, the liquid crystal cell formed on the upper glass substrate 71 The low potential DC voltage VL is applied to the common electrode 73 of Clc via the Vcom terminals 65a and 68a and the silver dot 74. At the same time, a high potential DC voltage VH is applied to the pixel electrode of the liquid crystal cell Clc facing the common electrode 73 with the ferroelectric liquid crystal interposed therebetween.

Since the gate high voltage VGH or the gate low voltage VGL are not generated from the power supply circuit 69, the gate lines GL1 to GLm maintain 0V or float during electric field alignment. Therefore, the voltage on the data lines DL1 to DLm during the field alignment is applied to the pixel electrode of the liquid crystal cell Clc as the leakage current of the TFT.

However, the driving circuit of the liquid crystal display device is basically designed based on the normal driving time. For this reason, the data drive chip 64 may be damaged by excessive load when the electric field is applied to the entire panel.

The field alignment method of the ferroelectric liquid crystal according to the second embodiment of the present invention and the liquid crystal display device using the same reduce the excessive load affecting the data drive chip 64 during the field alignment. The field alignment method of the ferroelectric liquid crystal and the liquid crystal display device using the same according to the second embodiment of the present invention will be described in detail with reference to FIGS. 11 to 14.

Referring to FIG. 11, in the ferroelectric liquid crystal display according to the second exemplary embodiment of the present invention, m × n liquid crystal cells Clc are arranged in a matrix type, m data lines D1 to Dm and n gates. The liquid crystal panel 102 where the lines G1 to Gn intersect and a TFT is formed at the intersection thereof, and the data driving circuit 101 for supplying data to the data lines D1 to Dm of the liquid crystal panel 102. And a gate driving circuit 103 for supplying scan pulses to the gate lines G1 to Gn of the liquid crystal panel 102, and connected between the data driving circuit 101 and the data lines D1 to Dm. The electric field orientation / normal drive switch circuit 104, the orientation voltage source 103 for supplying the voltages below the threshold voltage of the TFT to the gate lines G1 to Gn, and the timing for controlling the data driving circuit 101. The controller 100 selects one of the field alignment voltage and the ground voltage GND, and selects And a switch element 105 for supplying a voltage to the field alignment / normal drive switch circuit 104.

The liquid crystal panel 102 is substantially the same as that shown in FIG.

The data driving circuit 101 includes a plurality of data drive chips 64 shown in FIGS. 6 and 7. The data driving circuit 101 converts the digital video data RGB into an analog gamma voltage and supplies the analog gamma voltage to the data lines D1 to Dm under the control of the timing controller 100 during normal driving.

In the electric field alignment of the ferroelectric liquid crystal, no voltage is supplied from the gamma circuit chip 61 and the timing controller 60 to the data driving circuit 101. Therefore, the data driving circuit 101 does not generate any voltage when the ferroelectric liquid crystal is field aligned.                     

The gate driving circuit 103 sequentially supplies scan pulses to the gate lines G1 to Gn under the control of the gate timing controller 100 during normal driving. This gate driving circuit 103 is integrated into the gate drive chip 67 shown in FIG.

In the electric field alignment of the ferroelectric liquid crystal, a voltage between 0 and 1 V is applied to the gate lines G1 to Gn. In addition, the gate lines G1 to Gn during the electric field alignment may maintain a floating state without supplying a voltage from the alignment voltage source 103 during the electric field alignment of the ferroelectric liquid crystal. Thus, when a voltage between 0 to 1 V is applied to the gate lines G1 to Gn or the gate lines G1 to GN remain in a floating state, the TFT is off when the field alignment of the ferroelectric liquid crystal is performed, but the source of the TFT is A leakage current is generated between the terminal and the drain terminal. Due to this leakage current, the voltage on the data lines D1 to Dm is supplied to the pixel electrode via the source terminal and the drain terminal of the TFT.

The field alignment / normal drive switch circuit 104 blocks the current path between the data driving circuit 101 and the data lines D1 to Dm during the electric field alignment of the ferroelectric liquid crystal, and the field alignment voltage source and the data lines D1 to D. The current path between Dm) is conducted to supply a DC voltage, for example, 5V, required for field alignment to the data lines D1 to Dm. On the other hand, during normal driving, the electric field orientation / normal driving switch circuit 104 conducts a current path between the data driving circuit 101 and the data lines D1 to Dm to receive an analog voltage from the data driving circuit 101. Supply to the data lines (D1 to Dm) and cut off the current path between the field-oriented voltage source and the data lines (D1 to Dm).

The switch 105 is connected between the field orientation voltage source 5V, the ground voltage source GND, and the field alignment / normal drive switch circuit 104 to switch the field orientation voltage 5V during the field alignment of the ferroelectric liquid crystal. It supplies to the drive switch circuit 104. On the other hand, the switch 105 supplies the ground voltage GND to the field orientation / normal drive switch circuit 104 at the time of normal driving. This switch 105 may be formed on the source PCB 65 in FIG. 6 or embedded in the timing controller 100.

The timing controller 100 does not operate during the field alignment of the ferroelectric liquid crystal but supplies the digital video data RGG to the data driving circuit 101 during normal driving, and also the vertical / horizontal synchronization signals V and H and the main clock MCLK. ) Generates control signals DDC and GDC for controlling the data driving circuit 101 and the gate driving circuit 103. The data control signal (DDC) includes a source start pulse (SSP), a source shift clock (SSC), a source output signal (SOE), and a polarity signal (POL). do. The gate control signal GDC includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output signal (GOE), and the like. This timing controller 100 is integrated into the chip 60 shown in FIG.

On the other hand, when the switch 105 is embedded in the timing controller 100, the switch 105 in the timing controller 100 is operated by the user when the field alignment of the ferroelectric liquid crystal is carried out so that the field alignment voltage 105 is applied to the field alignment / normal. It supplies to the drive switch circuit 104.

12 to 14 show in detail the field alignment / normal drive switch circuit 104 according to the embodiment of the present invention.                     

12, the field alignment / normal drive switch circuit 104 according to the first embodiment of the present invention is an N-type MOS-FET (connected between the output terminal of the data driving circuit 101 and the switch 105). NT) and a bus line 111 connected between the switch 105 and the plurality of N-type MOS-FETs NT.

The source terminal and the gate terminal of the MOS-FET NT are connected to the bus line 111, and the drain terminal of the MOS-FET NT is connected to the output terminal of the data driving circuit 101. The MOS-FET NT is turned on when the voltage on the bus line 111 is higher than its threshold voltage to supply the voltage on the bus line 111 to the data lines D1 to Dm, When the voltage on 111 is lower than its threshold voltage, it is turned off to block the current path between the bus line 111 and the data lines D1 to Dm. Accordingly, the MOS-FET NT supplies the field alignment voltage 5V to the data lines D1 to Dm during the field alignment of the ferroelectric liquid crystal to which the field alignment voltage 5V is supplied from the switch 105. The analog gamma voltage from the data driving circuit 101 is supplied to the data lines D1 to Dm during the normal driving in which the ground voltage GND is supplied from the switch 105.

Referring to FIG. 13, the electric field orientation / normal drive switch circuit 104 according to the second embodiment of the present invention includes a diode D connected between the output terminal of the data driving circuit 101 and the switch 105; A bus line 121 is connected between the switch 105 and the plurality of diodes D.

The anode terminal of the diode D is connected to the bus line 121 and the cathode terminal of the diode D is connected to the output terminal of the data driving circuit 101. The diode D forms a current path between the bus line 121 and the data lines D1 to Dm when the voltage on the bus line 121 is higher than its threshold voltage, and on the bus line 111. When the voltage is lower than its threshold voltage, the current path between the bus line 121 and the data lines D1 to Dm is blocked. Accordingly, the diode D supplies the field alignment voltage 5V to the data lines D1 to Dm at the time of the field alignment of the ferroelectric liquid crystal supplied with the field alignment voltage 5V from the switch 105, while the switch The analog gamma voltage from the data driving circuit 101 is supplied to the data lines D1 to Dm during the normal driving in which the base voltage GND is supplied from the 105.

Referring to FIG. 14, the electric field orientation / normal drive switch circuit 104 according to the third embodiment of the present invention is an N-type MOS-FET connected between the output terminal of the data driving circuit 101 and the switch 105 ( NT), bus line 131 connected between switch 105 and a plurality of N-type MOS-FETs (NT), and P type connected between bus line 131 and an output terminal of data drive circuit 101. MOS-FET (PT).

The N-type MOS-FET NT supplies the field alignment voltage 5V to the data lines D1 to Dm during the field alignment of the ferroelectric liquid crystal to which the field alignment voltage 5V is supplied from the switch 105. The analog gamma voltage from the data driving circuit 101 is supplied to the data lines D1 to Dm during the normal driving in which the ground voltage GND is supplied from the switch 105. The N-type MOS-FET NT may be replaced by a diode D having an anode terminal connected to the bus line and a cathode terminal connected to the data lines D1 to Dm as shown in FIG. 13.

The gate terminal of the P-type MOS-FET PT is connected to the bus line 111 and the source terminal is connected to the output terminal of the data driving circuit 101. The drain terminal of the P-type MOS-FET PT is connected to the data lines D1 to Dm. The P-type MOS-FET PT is turned off when the voltage on the bus line 131 is higher than its threshold voltage to block the current path between the data driving circuit 101 and the data lines D1 to Dm. On the other hand, when the voltage on the bus line 111 is lower than its threshold voltage, it is turned on to form a current path between the data driving circuit 101 and the data lines D1 to Dm. This P-type MOS-FET (PT) prevents the current or voltage on the bus line 131 or the data lines D1 to Dm from affecting the data driving circuit 101 during the field alignment of the ferroelectric liquid crystal. .

As described above, the field alignment method of the ferroelectric liquid crystal according to the embodiment of the present invention and the liquid crystal display device using the same are arranged in the field alignment mode by providing an electric field alignment / switch circuit between the output terminal and the data lines of the data driving circuit. While forming a current path between the voltage source and the data lines, the current path between the field-oriented voltage source and the data lines is interrupted in the normal driving mode and forms a current path between the output terminal and the data lines of the data driving circuit. As a result, the field alignment method of the ferroelectric liquid crystal according to the embodiment of the present invention and the liquid crystal display device using the same reduce the excessive load or damage of the driving circuit during the field alignment process performed with the driving circuit used in the normal driving. Can be.                     

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (11)

delete delete In a liquid crystal display device in which a plurality of data lines and a plurality of gate lines intersect and ferroelectric liquid crystal is injected, A data driving circuit for supplying data to the data lines; A power supply for generating field alignment voltage, A switch circuit comprising a switch element connected between the data driving circuit and the data line, and a bus line connected between the switch element and the power source for supplying a voltage from the power supply to the switch element, The switch element of the switch circuit supplies the voltage on the bus line to the data lines in response to the voltage on the bus line in the case of electric field alignment, while providing a current path between the bus line and the data line in normal driving. Ferroelectric liquid crystal display device characterized in that the blocking. The method of claim 3, wherein And a second switch circuit which cuts off a current path between the power supply and the data driving circuit when the electric field is aligned. delete The method of claim 3, wherein The switch element is a ferroelectric liquid crystal display device comprising an N-type MOS-FET. The method of claim 3, wherein The switch element is a ferroelectric liquid crystal display device, characterized in that the diode. The method of claim 4, wherein The second switch circuit, A second switch element connected between the data driving circuit and the data line, And the bus line is connected between the second switch element and the power source to supply a voltage from the power source to the second switch element. The method of claim 8, The switch element interrupts a current path between the data driving circuit and the data line in response to a voltage on the bus line during the electric field orientation, while a current path between the data driving circuit and the data line during the normal driving. A ferroelectric liquid crystal display device comprising a P-type MOS-FET to form a. The method of claim 3, wherein Forming a current path between the power supply and the switch circuit during the field orientation, while blocking a current path between the power supply and the switch circuit during the normal driving and forming a current path between the ground voltage source and the switch circuit. A ferroelectric liquid crystal display device further comprising a third switch element. The method of claim 10, And the third switch element is disposed on a printed circuit board on which the data driving circuit is mounted.

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