KR100922786B1 - Method and apparatus for driving liquid crystal display - Google Patents

Abstract

The present invention relates to a method and apparatus for driving a liquid crystal display device which reduces the capacity of a data modulation memory and improves image quality.

The present invention provides a first step of setting first modulated data having a larger value than a data value of a current frame in response to an increase in a data value; Setting second modulated data to have a value smaller than a data value of the current frame in response to a decrease in a data value; a third step of receiving source data of n bits (where n is a positive integer) and storing them in a memory; a fourth step of determining whether the previous frame stored in the memory and the source data of the current frame are equal in units of n-k (where k is a positive integer smaller than n); And supplying source data of the current frame to a liquid crystal panel or modulating the source data using the first and second modulation data according to the determination result.

In this way, the present invention reduces the memory capacity of the lookup table and improves image quality by using a high speed driving method.

Description

TECHNICAL AND APPARATUS FOR DRIVING LIQUID CRYSTAL DISPLAY}             

1 is a waveform diagram showing a change in luminance in accordance with data in a conventional liquid crystal display device.

Fig. 2 is a waveform diagram showing an example of a luminance change caused by data modulation in the conventional high speed driving method.

3 is a diagram showing an example of a conventional high speed driving method in 8 bit data;

4 is a block diagram showing a conventional high speed drive device.

5 is a block diagram illustrating a driving device of a liquid crystal display according to a first embodiment of the present invention.

FIG. 6 is a block diagram illustrating in detail the timing controller shown in FIG. 5; FIG.

FIG. 7 is a diagram illustrating a modulation data setting method of the lookup table illustrated in FIG. 6.

8 is a block diagram illustrating a driving device of a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 9 is a circuit diagram showing a comparator shown in FIG. 8. FIG.                 

FIG. 10 is a diagram illustrating a modulation data setting method of the lookup table shown in FIG. 8. FIG.

<Description of Symbols for Main Parts of Drawings>

41: Lower Bit Busline 42: Upper Bit Busline

43, 58, 59, 158: frame memory 44, 62: lookup table

51, 151: timing controller 53, 153: data driver

54, 154: gate driver 55, 155: data line

56, 156: gate lines 57, 157: liquid crystal panel

60, 160: input line 61: control signal generator

159: comparator 170a to 170g: XOR gate

172: logic circuit 174: data output

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method and apparatus for driving a liquid crystal display device to reduce the capacity of a data modulation memory and to improve image quality.

In general, a liquid crystal display (LCD) displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. An active matrix liquid crystal display device in which switching elements are formed for each liquid crystal cell is suitable for displaying moving images. As a switching element used in an active matrix liquid crystal display device, a thin film transistor (hereinafter, referred to as TFT) is mainly used.

As can be seen in Equations 1 and 2, the liquid crystal display has a disadvantage in that the response speed is slow due to the inherent viscosity and elasticity of the liquid crystal.

(gamma)는 액정분자의 회전점도(rotational viscosity)를 각각 의미한다. Where τ _r is the rising time when voltage is applied to the liquid crystal, Va is the applied voltage, and V _F is the Freederick Transition Voltage at which the liquid crystal molecules begin their inclined motion, d Is the cell gap of the liquid crystal cell,

(gamma) means rotational viscosity of liquid crystal molecules, respectively.

Here, τ _f denotes a falling time during which the liquid crystal is restored to its original position by the elastic restoring force after the voltage applied to the liquid crystal is turned off, and K denotes the elastic modulus inherent to the liquid crystal.

The liquid crystal response speed of the TN mode may vary depending on the physical properties of the liquid crystal material, the cell gap, and the like, but usually has a rising time of 20-80 ms and a polling time of 20-30 ms. Since the response speed of the liquid crystal is longer than one frame period (NTSC: 16.67 ms) of the video, the screen is blurred in the video because the voltage charged in the liquid crystal cell proceeds to the next frame as shown in FIG. 1. Motion blurring phenomenon appears.

Referring to FIG. 1, a conventional liquid crystal display device does not reach a desired display luminance BL when the data VD changes from one level to another due to a slow response speed when a video is implemented. It will not be able to express color and brightness. As a result, the motion blurring phenomenon appears in the moving picture, and the display quality is deteriorated due to the decrease in the contrast ratio.

In order to solve the slow response speed of the liquid crystal display, U.S. Patent No. 5,495,265 and PCT International Publication No. WO 99/05567 use a lookup table to modulate the data according to whether or not the data is changed (hereinafter, 'high speed driving'). Has been proposed. This high speed driving method modulates data in the same principle as in FIG. 2.

을 크게 하게 된다. 따라서, 고속 구동방법을 이용하는 액정표시장치는 액정의 늦은 응답속도를 데이터값의 변조로 보상하여 동화상에서 모션 블러링(Motion Burring) 현상을 완화시 킴으로써 원하는 색과 휘도로 화상을 표시할 수 있게 된다. Referring to FIG. 2, the conventional high speed driving method modulates the input data VD and applies the modulation data MVD to the liquid crystal cell to obtain a desired luminance MBL. This high-speed driving method uses Equation 1 based on whether or not the data is changed to obtain a desired luminance corresponding to the luminance value of the input data within one frame period.

To make it larger. Therefore, the liquid crystal display device using the high speed driving method compensates the late response speed of the liquid crystal by modulating the data value, thereby alleviating the motion blurring in the moving image, thereby displaying an image with a desired color and luminance. do.

In other words, the fast driving method compares the most significant bit data MSB of each of the previous frame Fn-1 and the current frame Fn, and if there is a change between the most significant bit data MSB, the corresponding modulation data in the lookup table. Select (Mdata) to modulate as shown in FIG. This high speed driving method modulates only the upper few bits in order to reduce the capacity burden of the memory in hardware implementation. The high speed drive device implemented as described above is illustrated in FIG. 4.

Referring to FIG. 4, the conventional high speed drive device is commonly connected to the frame memory 43 connected to the upper bit bus line 42 and the output terminals of the upper bit bus line 42 and the frame memory 43. The lookup table 44 is provided.

The frame memory 43 stores the most significant bit data MSB for one frame period and supplies the stored data to the lookup table 44. Here, the most significant bit data MSB is set to the upper 4 bits among the 8 bit source data RGB Data In.

The lookup table 44 includes the upper bit data MSB of the current frame Fn input from the upper bit bus line 42 and the upper bit data MSB of the previous frame Fn-1 input from the frame memory 43. ) And the modulation data (Mdata) corresponding to the comparison result are selected. The modulated data Mdata is added to the bit data LSB from the lower bit bus line 41 and supplied to the liquid crystal display. Table 1 shows the most significant ^{4 bit (2 4, 2 5} , 2 6, 2 7) and the top ^{4 bit (2 4, 2 5} , 2 6, 2 7) of the current frame (Fn) of a previous frame (Fn-1) An example of a lookup table 44 for comparing the? And selecting the modulation data Mdata corresponding to the result of the comparison is shown.

division 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 0 0 32 48 64 80 96 112 144 160 192 208 224 240 240 240 240 16 0 16 48 64 80 96 112 128 160 192 208 224 240 240 240 240 32 0 0 32 64 80 96 112 128 160 192 208 224 240 240 240 240 48 0 0 16 48 80 96 112 128 160 176 208 224 240 240 240 240 64 0 0 16 48 64 96 112 128 144 176 192 208 224 240 240 240 80 0 0 16 32 48 80 112 128 144 176 192 208 224 240 240 240 96 0 0 16 32 48 64 96 128 144 160 192 208 224 240 240 240 112 0 0 16 32 48 64 80 112 144 160 176 208 224 240 240 240 128 0 0 16 32 48 64 80 96 128 160 176 192 224 240 240 240 144 0 0 16 32 48 64 80 96 112 144 176 192 208 224 240 240 160 0 0 16 32 48 64 80 96 112 128 160 192 208 224 240 240 176 0 0 16 32 48 64 80 96 112 128 144 176 208 224 240 240 192 0 0 16 32 48 64 80 96 112 128 144 160 192 224 240 240 208 0 0 16 32 48 48 64 80 96 112 128 160 176 208 240 240 224 0 0 16 32 48 48 64 80 96 112 128 144 176 192 224 240 240 0 0 0 16 32 48 48 64 80 96 112 128 144 176 208 240

In Table 1, the left column is the data VDn-1 of the previous frame Fn-1, and the uppermost row is the data VDn of the current frame Fn.

The reason for modulating only the 4-bit upper bit data MSB is to reduce the memory capacity of the lookup table 44.

However, when the lookup table 44 adopts a 4-bit comparison method to reduce memory capacity, there is a problem in that the quality between the gray scales is not linear and the leap occurs.

In order to reduce such deterioration of image quality, the data width of the modulation data listed in the lookup table 44 should be large enough and the input source data should be compared in full bits, that is, in units of 8 bits.                         

Table 2 shows an example of a lookup table in which modulation data (Mdata) is 8 bits and source data is compared in 8 bit full bit units.

In this case, when the lookup table is compared in 8 bit units and the modulation data (Mdata) pre-stored in the lookup table is 8 bit, the gray level is changed linearly, and thus the image quality is excellent. There is this. For example, if the lookup table is compared in 8 bit units and the modulation data Mdata is 8 bits, the memory capacity of the lookup table is increased to 65536 × 8 = 524,000 bits. Here, the first term '65536' on the left side is 8 bits of the source data product (256 × 256) in each of the previous frame (Fn-1) and the current frame (Fn), and the second term '8' on the left side is a lookup table. It is the data width (8 bits) of the modulation data listed in (44). In addition, for color realization, considering red, green, and blue (RGB), the memory capacity of the lookup table reaches 65536 x 8 x 3 = 1,572,000 bits. Therefore, if the lookup table adopts an 8-bit comparison method for high-speed driving, as the memory capacity increases, the manufacturing cost increases and the chip size increases.

Accordingly, it is an object of the present invention to set the number of bits of the source data of the previous frame and the source data of the current frame used for data modulation by one bit less than the number of bits of the original source data, thereby reducing the capacity of the memory for data modulation. The present invention provides a method and apparatus for driving a liquid crystal display device which reduces the bit comparison method and improves the image quality compared to the conventional highest 4 bit comparison method.

In order to achieve the above object, a driving method of a liquid crystal display according to an exemplary embodiment of the present invention includes a first step of setting first modulated data having a larger value than a data value of a current frame in response to an increase in a data value; ; Setting second modulated data to have a value smaller than a data value of the current frame in response to a decrease in a data value; a third step of receiving source data of n bits (where n is a positive integer) and storing them in a memory; a fourth step of determining whether the previous frame stored in the memory and the source data of the current frame are equal in units of n-k (where k is a positive integer smaller than n); And supplying source data of the current frame to a liquid crystal panel or modulating the source data using the first and second modulation data according to the determination result.

In the driving method, n is '8' and k is '1'.

In the driving method, the fifth step includes supplying data of the current frame to the liquid crystal panel when data values of the previous frame and the current frame are the same, and data values of the previous frame and the current frame. If different, comparing the source data of the previous frame and the current frame in units of nk bits (where k is a positive integer less than n) and modulating the source data using the first and second modulation data. It includes.

In the driving method, modulating the source data may include modulating the source data using the first modulated data when the source data value of the current frame is increased from the previous frame; And modulating the source data using the second modulated data when the source data value of the current frame is decreased from the previous frame.

According to an exemplary embodiment of the present invention, a driving apparatus of a liquid crystal display device includes a liquid crystal panel in which a plurality of data lines and a plurality of gate lines cross each other, and a liquid crystal cell is formed in a pixel region between the data line and the gate line to display an image. ; an input line for inputting source data of n bits, wherein n is a positive integer; A memory for receiving and storing the source data, a comparator for determining whether the previous frame stored in the memory and the source data of the current frame are equal in units of nk (where k is a positive integer smaller than n); List the first modulation data having a value larger than the data value of the current frame in response to the increase in the data value and the second modulation data to have a value smaller than the data value of the current frame in response to the decrease in the data value. And a modulator for supplying source data of the current frame to the liquid crystal panel or modulating the source data using the first and second modulated data according to the determination result from the comparator.

In the driving apparatus, the comparator supplies the data of the current frame to the liquid crystal panel when the data value of the previous frame and the current frame is the same, and, if the data value of the previous frame and the current frame is different, And supplying source data of the previous frame and the current frame to a modulator.

In the driving apparatus, the modulator compares source data of the current frame to the previous frame in units of nk bits, where k is a positive integer less than n, and compares the source data of the current frame to the previous frame as a result of the comparison. If the value is increased, the source data is modulated using the first modulated data, and if the source data value of the current frame is decreased from the previous frame, the source data is modulated using the second modulated data. do.

The driving device includes a data driver for supplying modulation data from the modulator to a data line of the liquid crystal panel; A gate driver for supplying a scan signal to a gate line of the liquid crystal panel; A timing controller for controlling the data driver and the gate driver is further provided.

In the driving device, the modulator is a lookup table built in the timing controller.

In the driving apparatus, n is '8' and k is '1'.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 10.

Referring to FIG. 5, in the driving apparatus of the liquid crystal display according to the first exemplary embodiment of the present invention, a TFT for driving the liquid crystal cell Clc intersects a data line 55 and a gate line 56. Supplying scan pulses to the liquid crystal panel 57, the data driver 53 for supplying data to the data line 55 of the liquid crystal panel 57, and the gate line 56 of the liquid crystal panel 57. A gate controller 54 and a timing controller 51 for generating timing control signals DDC and GDC while modulating the data through comparison of the upper 7 bits in 8-bit source data, and an input line 60. And first and second frame memories 58 and 59 connected between the timing controller 51 and the timing controller 51.

In the liquid crystal panel 57, liquid crystal is injected between two glass substrates, and the data lines 55 and the gate lines 56 are orthogonal to each other on the lower glass substrate. The TFT formed at the intersection of the data lines 55 and the gate lines 56 supplies the data on the data lines 55 to the liquid crystal cell Clc in response to a scan pulse from the gate line 56. . For this purpose, the gate electrode of the TFT is connected to the gate line 56 and the source electrode is connected to the data line 55. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

The data driver 53 stores the data by one line in response to a shift register for sampling the dot clock of the timing control signal DDC, a register for temporarily storing the data, and a clock signal from the shift register. For simultaneously outputting the data of the controller, an analog / digital converter for selecting a positive / negative gamma voltage corresponding to the digital data value from the latch, and a data line 55 for outputting data from the analog / digital converter It consists of a multiplexer for selecting and an output buffer connected between the multiplexer and the data line. The data driver 53 receives the modulated data Mdata of red (R), green (G), and blue (B) colors modulated by the timing controller 51 to control the gate from the timing controller 51. The modulated data Mdata is supplied to the data lines 55 of the liquid crystal panel 57 in response to the signal DDC.

The gate driver 54 shifts a shift register that sequentially generates scan pulses in response to the gate control signal GDC from the timing controller 51, and shifts the voltage of the scan pulses to a level suitable for driving the liquid crystal cell Clc. Level shifter and the like.

The timing controller 51 compares the source data Fn and Fn-1 input from the first and second frame memories 58 and 59 in the upper 7 bit units and compares the modulation data Mdata corresponding to the comparison result. Will be chosen. The modulated data Mdata selected by the timing controller 51 is input to the data driver 53. In addition, the timing controller 51 controls the gate control signal GDC and the data driver 53 for controlling the gate driver 54 using the vertical / horizontal synchronization signals V and H and the main clock MCLK. A data control signal DDC is generated.                     

The first frame memory 58 stores data from the input line 60 for one frame period and supplies the data RGB of the current frame Fn stored to the second frame memory 59 and the timing controller 51. do.

The second frame memory 59 stores data from the first frame memory 58 for one frame period, and supplies the data RGB of the previous frame Fn-1 to the timing controller 51.

On the other hand, between the input line 60 and the frame memory 58, an interface circuit adopting an interface method such as Low Voltage Differential Signaling (LVDS), Transition Minimized Differential Signaling (TMDS), RSDS, etc. Can be installed. Furthermore, the first frame input and output ends of the first and the second frame memory 59 of the memory 58, the bit conversion circuit, or discard the least significant bit (2 ⁰⁾ in the source data of 8 bit takes a top 7 bit 7 bit Bus lines may be installed.

6 shows the timing controller 51 in detail.

Referring to FIG. 6, the timing controller 51 according to the present invention includes a control signal generator 61 for generating a gate control signal GDC and a data control signal DDC, a current frame Fn, and a previous frame ( A lookup table 62 for comparing the source data of Fn-1) in units of 7 bits and outputting modulation data of 8 bits is provided.

The control signal generator 61 receives the gate start pulse GSP, the gate shift clock GSC, and the gate output enable GOE using the vertical / horizontal synchronization signals V and H and the main clock MCLK. Generate a gate control signal (GDC) including the data enable signal (DE), the source shift clock (SSC), the source start pulse (SSP), the polarity control signal (POL), and the source output enable signal (SOE). Generate a data control signal DDC.

The lookup table 62 shows the upper 7 bits (2 ⁷ , 2 ⁶ , 2 ⁵ , 2 ⁴ , 2 ³ , 2 ² , 2 ¹ ) of the current frame Fn and the upper 7 bits (of the previous frame Fn-1). 2 ⁷ , 2 ⁶ , 2 ⁵ , 2 ⁴ , 2 ³ , 2 ² , 2 ¹ ), and 8-bit modulation data corresponding to the comparison result are selected.

When the data input to the timing controller 51 represents '200' and '201' as a binary number, 11001000 ₂ and 11001001 ₂ are the upper 7 bits (2 ⁷ , 2 ⁶ , 2 ⁵ , 2 ⁴ , 2 ³ , The values of 2 ² , 2 ¹ are the same and only the least significant bit (2 ⁰ ) is different. Therefore, when the data supplied to the input line 60 is '200' and '201', 1100100 is input to the lookup table 62.

The modulation data listed in the lookup table 62 satisfies the high speed driving conditions as shown in the following relational expressions ① to ③.

VDn <VDn-1 ---> MVDn <VDn -------- ①

VDn = VDn-1 ---> MVDn = VDn, -------- ②

VDn> VDn-1 ---> MVDn> VDn. -------- ③

In (1) to (3), VDn-1 represents the data voltage of the previous frame, VDn represents the data voltage of the current frame, and MVDn represents the modulated data voltage, respectively.                     

In the case of the relation ③, the overshoot occurs electrically and optically when the modulation data Mdata is higher than the optimum value. Undershoot occurs. In the overshoot, since the brightness of the image is rapidly increased, the degradation of image quality that the observer feels subjectively is severe, whereas the undershoot hardly decreases the image quality that the observer feels subjectively. Therefore, it is preferable that the modulation data Mdata listed in the lookup table 62 is set to a value where only an undershoot can appear without overshooting. To this end, when the modulation data (Mdata) listed in the lookup table 62 is divided into three bands of the relations (1) to (3), four modulation data (Mdata) is generated in the modulation data band satisfying the relation (1) as shown in FIG. Each adjacent small band is set to a maximum value. In addition, each of the small bands adjacent to the four modulation data Mdata in the modulation data band satisfying the relation (3) is set to a minimum value. In FIG. 7, the modulation band Mdata is set to a value equal to the value of the data RGB currently input in the data band satisfying the relation (2).

Table 3 and 4 show an example of the lookup table 62. Table 3 sets modulation data (Mdata) in the lookup table of Table 2 by converting the source data into 7 bits and generating an undershoot of a modulation data band satisfying relations (1) and (3). Table 4 reconstructs the lookup table of Table 3 by taking either of the cases where the source data in Table 3 is the same.                     

Comparing Tables 2 and 3, the conventional small bands '106,108,106,107' satisfying the relation 1 in the lookup table 62 are converted to undershoot values, i.e., the maximum values 108,108,108,108. Further, in the lookup table 62, the conventional small bands '144, 145, 144 and 145' which satisfy the relation 3 are converted to undershoot values, i.e., the minimum values (144, 144, 144 and 144).

The memory capacity of the lookup table 62 according to the present invention is 16,384 × 8 = 131,072 bits, and considering the red, green, and blue colors (RGB), the memory capacity of the lookup table is 16,384 × 8 × 3 = 393,216 bits. Compared by 8 bit unit, memory capacity is greatly reduced compared to lookup table with 8 bit modulated data. Here, the first term '16, 384 'on the left side is the source data product (128 × 128) of 7 bits in the previous frame (Fn-1) and the current frame (Fn), and the second term' 8 'on the left side is the modulation data. Data width (8 bits).

The driving apparatus of the liquid crystal display according to the first exemplary embodiment of the present invention generates a data output error in the case of a still image or data of 1 gray difference.

In detail, as shown in Table 4 below, when the previous frame data value of the left side is "71" and the current frame data value is "71", the data value of "71" is replaced with an 8-bit value. "142" and "143". Accordingly, the modulation data value output when the data value of the current frame and the data value of the previous frame are changed from "142" to "142" becomes "141", and the data value of the current frame and the data value of the previous frame are When it is changed from "143" to "143", the output modulation data value is "141". In other words, if there is a still picture or 1 gray difference, a data output error occurs in which a different value is output.

In order to solve this problem, the driving device of the LCD according to the second exemplary embodiment of the present invention compares the data value of the previous frame with the data value of the current frame in 7Bit units before comparing them in 7Bit units in the lookup table. In the same case, the data value of the current frame is supplied to the liquid crystal panel.

Referring to FIG. 8, in the driving apparatus of the liquid crystal display according to the second exemplary embodiment of the present invention, the data line 155 and the gate line 156 intersect each other and drive the liquid crystal cell Clc at an intersection thereof. Scan pulses are applied to the liquid crystal panel 157 on which the TFTs are formed, the data driver 153 for supplying data to the data line 155 of the liquid crystal panel 157, and the gate line 156 of the liquid crystal panel 157. A gate controller 154 for supplying, a timing controller 151 for comparing the previous source data with the current source data in upper 7 bit units to modulate the data and generating timing control signals DDC and GDC; The frame memory 158 connected between the line 160 and the timing controller 151 and the frame memory 158 and the timing controller 151 are connected to compare the previous source data with the current source data in the upper 7 bit units. With comparator 159 for All.

In the liquid crystal panel 157, liquid crystal is injected between two glass substrates, and the data lines 155 and the gate lines 156 are orthogonal to each other on the lower glass substrate. The TFT formed at the intersection of the data lines 155 and the gate lines 156 supplies the data on the data lines 155 to the liquid crystal cell Clc in response to a scan pulse from the gate line 156. . For this purpose, the gate electrode of the TFT is connected to the gate line 156 and the source electrode is connected to the data line 155. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

The data driver 153 stores the data by one line in response to a shift register for sampling the dot clock of the timing control signal DDC, a register for temporarily storing the data, and a clock signal from the shift register. Latch for simultaneously outputting the data of the data, analog / digital converter for selecting the positive / negative gamma voltage corresponding to the digital data value from the latch, and data line 155 for outputting data from the analog / digital converter It consists of a multiplexer for selecting and an output buffer connected between the multiplexer and the data line. The data driver 153 receives the modulated data Mdata of red (R), green (G), and blue (B) colors modulated by the timing controller 151 to control the gate from the timing controller 151. The modulated data Mdata is supplied to the data lines 155 of the liquid crystal panel 157 in response to the signal DDC.

The gate driver 154 shifts the shift register which sequentially generates scan pulses in response to the gate control signal GDC from the timing controller 151, and shifts the voltage of the scan pulses to a level suitable for driving the liquid crystal cell Clc. Level shifter and the like.

The data RGB from the input line 160 is supplied to an input terminal of the frame memory 158 and a first input terminal of the comparator 159. The frame memory 158 stores the source data RGB from the input line 160 for one frame period and supplies the stored source data RGB of the current frame Fn to the second input terminal of the comparator 159.

The comparator 159 compares the current frame source data RGB from the input line 160 with the previous frame source data RGB from the frame memory 158 in the upper 7 bit units and according to the comparison result, the current frame source. The data RGB is supplied to the data driver 153 or the current frame source data RGB and the previous frame source data RGB from the frame memory 158 are supplied to the timing controller 151. At this time, a low voltage differential signaling (LVDS) method, a TMDS (Transition Transition), is used to reduce the data bus line between the input line 160 and the frame memory 158 and between the input line 160 and the first input terminal of the comparator 159. An interface circuit adopting an interface method such as a Minimized Differential Signaling (RSM) method or an RSDS method may be installed. Further, the frame memory 158 of the output terminal and the comparator (159) of the second input, the 8 bit converter or a 7 bit bus line discard the least significant bit (2 ⁰⁾ in the source data that takes a top 7 bit of the bit can be installed have.

To this end, the comparator 159 outputs signals from each of the first to seventh XOR gates 170a to 170g and the first to seventh XOR gates 170a to 170g, as shown in FIG. In response to a logic signal from the logic circuit 172 and the logic circuit 172 to receive and output a 1-bit logic value, the source data (RGB) of the current frame (Fn) is supplied to the data driver 153 or the current frame ( And a data output unit 174 for supplying the source data RGB of Fn and the source data RGB of the previous frame Fn-1 to the timing controller 151.

Source data RGB of the current frame Fn is supplied from the input line 160 to the first input terminals of each of the first to seventh XOR gates 170a to 170g, and to the second input terminals. The source data RGB of the previous frame Fn-1 is supplied from the memory 158. That is, each bit of the 7Bit source data RGB of the current frame Fn and the previous frame Fn-1 is supplied to each of the first to seventh XOR gates 170a to 170g. That is, when the data '100' and '101' input to the comparator 159 are expressed in binary numbers, the upper 7 bits (2 ⁷ , 2 ⁶ , 2 ⁵ , 2 ⁴ , 2 ³ ,) are 01100100 ₂ and 01100101 ₂ . The values of 2 ² , 2 ¹ are the same and only the least significant bit (2 ⁰ ) is different. Therefore, if the data supplied through the input line 160 is '100' and '101', 0110010 is input to the comparator 159.

Accordingly, each of the first to seventh XOR gates 170a to 170g has a logic value of “0” (or LOW) when the data supplied to each of the first input terminal and the second input terminal is the same logical value. The logic circuit 172 is supplied to the logic circuit 172. When the logic values are different from each other, a logic value of "1" (or HIGH) is supplied to the logic circuit 172.

The logic circuit 172 receives an output signal from each of the first to seventh XOR gates 170a to 170g. Accordingly, the logic circuit 172 sends a logic value of "0" (or LOW) to the data output unit 174 when the output signals from each of the first to seventh XOR gates 170a to 170g are the same. If not equal, a logic value of "1" (or HIGH) is supplied to the data output unit 174.

When the logic value supplied from the logic circuit 172 is "0" (or LOW), the data output unit 174 supplies the source data RGB of the 8-bit current frame Fn to the data driver 153. If 1 "(or HIGH), the source data RGB of the 7-bit current frame Fn and the source data RGB of the previous frame Fn-1 are supplied to the timing controller 151.

As such, the comparator 159 stores the source data RGB of the current frame Fn supplied from the input line 160 and the source data RGB of the previous frame Fn-1 supplied from the frame memory 158. In the same case, the source data RGB of the current frame Fn is supplied to the data driver 153 in comparison with the upper 7 bit units. On the other hand, the comparator 159 compares the source data RGB of the current frame Fn supplied from the input line 160 and the source data RGB of the previous frame Fn-1 supplied from the frame memory 158. When the data is not the same in units of upper 7 bits, the source data RGB of the current frame Fn and the source data RGB of the previous frame Fn-1 are supplied to the timing controller 151.

The timing controller 151 compares the previous and current source data (Fn, Fn-1) input from the comparator 159 in the order of upper 7 bits and selects the modulation data Mdata corresponding to the comparison result. . The modulated data Mdata selected by the timing controller 151 is input to the data driver 153. In addition, the timing controller 151 controls the gate control signal GDC and the data driver 153 for controlling the gate driver 154 using the vertical / horizontal synchronization signals V and H and the main clock MCLK. A data control signal DDC is generated.

To this end, the timing controller 151 includes a control signal generator 61 for generating a gate control signal GDC and a data control signal DDC, a current frame Fn and a previous frame as shown in FIG. 6. A lookup table 62 for comparing the source data of Fn-1) in units of 7 bits and outputting modulation data of 8 bits is provided.                     

The control signal generator 61 receives the gate start pulse GSP, the gate shift clock GSC and the gate output enable GOE using the vertical / horizontal synchronization signals V and H and the main clock MCLK. Generate a gate control signal (GDC) including the data enable signal (DE), the source shift clock (SSC), the source start pulse (SSP), the polarity control signal (POL), and the source output enable signal (SOE). Generate a data control signal DDC.

A look-up table 62 is the top 7 of the current frame ^{(Fn) bit (2 7,} 2 6, 2 5, 2 4, 2 3, 2 2, 2 1) and the top seven bit (2 ⁷ of the previous frame (Fn) , 2 ⁶ , 2 ⁵ , 2 ⁴ , 2 ³ , 2 ² , 2 ¹ ), and 8-bit modulation data corresponding to the comparison result are selected.

When the data input from the comparator 159 to the timing controller 151 is represented in binary format as '100' and '101', they are 01100100 ₂ and 01100101 _2, which are upper 7 bits (2 ⁷ , 2 ⁶ , 2 ⁵ , 2 ^4). , 2 ³ , 2 ² , 2 ¹ ) are the same and only the least significant bit (2 ⁰ ) is different. Therefore, if the data input from the comparator 59 is '100' and '101', the lookup table 62 includes 0110010 ₂ ,. That is, 50 is input.

The modulation data listed in the lookup table 62 satisfies the high-speed driving conditions such as the above-described equations (1) to (3).

In the case of relation (3), overshoot occurs electrically and optically when the modulation data (Mdata) is higher than the optimum value. Undershoot will occur. In the overshoot, since the brightness of the image is rapidly increased, the degradation of image quality that the observer feels subjectively is severe, whereas the undershoot hardly decreases the image quality that the observer feels subjectively. Therefore, it is preferable that the modulation data Mdata listed in the lookup table 62 is set as a value that the observer does not feel subjectively and an undershoot may occur even when an overshoot occurs. To this end, when the modulation data (Mdata) listed in the lookup table 62 is divided into three bands of the relations (1) to (3), four modulation data (Mdata) is generated in the modulation data band satisfying the relation (1) as shown in FIG. Each adjacent small band is set to a value larger than the current frame. In addition, each of the small bands adjacent to four modulation data Mdata in the modulated data band satisfying the relation 3 is set to a value smaller than the current frame. In FIG. 8, the modulation data Mdata is set to the same data band as the value of the currently input data RGB in the data band satisfying the relation (2).

For this purpose, the modulation data Mdata listed in the lookup table 62 is listed as shown in Table 5 below.                     

In Table 5, when the 7Bit data value input in the current frame is "70", the 8Bit data value supplied to the input line 60 is "140" or "141". In addition, when the 7Bit data value input in the previous frame is "127", the 8Bit data value supplied to the input line 60 is "255" or "256".

Accordingly, the modulated data Mdata is set to the same data band as the value of the data RGB input in the current frame Fn. That is, the data band satisfying relation (2) differs from the source data RGB of the current frame Fn and the source data RGB of the previous frame Fn-1 supplied from the frame memory 58 in the comparator 59. The value of the data RGB inputted in the current frame Fn is supplied to the data driver 53 when it is determined to be the same compared in 7 bit units.

Modulated data bands satisfying the above relational expression 1 in Table 3 set modulation data Mdata as a value at which an undershoot occurs. That is, the modulated data bands satisfying the relation ① are set to a value smaller than the value of the data RGB input in the current frame Fn. In addition, modulated data bands satisfying the above relational expression 3 in Table 3 set the modulated data Mdata as a value that an observer cannot feel subjectively even when an overshoot occurs. That is, the modulated data bands satisfying the relation 3 are set to a value larger than the value of the data RGB input in the current frame RGB.

The driving apparatus of the liquid crystal display according to the second exemplary embodiment of the present invention compares the data value of the previous frame with the data value of the current frame in 7Bit units before comparing the data value of the current frame in 7Bit units in the lookup table. By supplying the liquid crystal panel, data output error can be improved.

In addition, the memory capacity of the lookup table 62 in the driving apparatus of the liquid crystal display according to the second embodiment of the present invention is 16,384 × 8 = 131,072 bits, and considering the red, green, and blue (RGB) memory of the lookup table The capacity is 16,384 x 8 x 3 = 393,216 bits, which greatly reduces the memory capacity compared to the conventional lookup table in which the source data is compared in 8-bit units and 8-bit modulation data is set. Here, the first term '16, 384 'on the left side is the source data product (128 × 128) of 7 bits in the previous frame (Fn-1) and the current frame (Fn), and the second term' 8 'on the left side is the modulation data. Data width (8 bits).

As described above, the method and apparatus for driving a liquid crystal display according to an exemplary embodiment of the present invention provide a bit number of the source data of the previous frame and the source data of the current frame used for data modulation by one bit than the number of bits of the original source data. By setting it small, the capacity of the data modulation memory can be reduced compared to the conventional full bit comparison method, and the image quality can be improved compared to the conventional highest four bit comparison method.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (11)

A first step of setting first modulated data of n bits (where n is a positive integer) having a larger value than the source data of the current frame in response to an increase in the data value; Setting n bits of second modulated data to have a smaller value than source data of the current frame in response to a decrease in a data value; a third step of receiving n-bit source data and storing it in a memory; determining whether the source data of the previous frame and the source data of the current frame are equal to each other stored in the memory in n-1 bit units; When the source data of the previous frame and the source data of the current frame are the same as the result of the determination in the fourth step, the source data of the n-bit current frame is supplied to the data driver, and the source data of the previous frame and the current frame are supplied. A fifth step of supplying source data of a previous frame of n-1 bits and source data of a current frame of n-1 bits to the data driver through a timing controller when the source data of the? The n-1 bit is composed of the remaining higher bits except the least significant bit of the n bit; The timing controller compares the source data of the previous frame of the n-1 bit with the source data of the current frame of the n-1 bit and selects one of the first and second modulated data according to the comparison result. A driving method of a liquid crystal display device, characterized in that the supply to the data driver. The method of claim 1, N is '8' driving method of the liquid crystal display device. delete The method of claim 1, The timing controller, And selecting the first modulated data when the source data value of the current frame is increased from the previous frame, and selecting the second modulated data when the source data value of the current frame is decreased from the previous frame. Method of driving display device. A liquid crystal panel in which a plurality of data lines and a plurality of gate lines cross each other, and a liquid crystal cell is formed in a pixel region between the data line and the gate line to display an image; an input line for inputting source data of n bits, wherein n is a positive integer; A memory for receiving and storing the source data; It is determined whether the source data of the previous frame and the source data of the current frame stored in the memory are equal in units of n-1 bits. If the source data of the previous frame and the source data of the current frame are the same as the result of the determination, n bits of If the source data of the current frame is supplied to the data driver, and the source data of the previous frame and the source data of the current frame are different, the source data of the previous frame of n-1 bits and the source data of the current frame of n-1 bits are supplied. A comparator for supplying the data driver through a timing controller; The n-1 bit is composed of the remaining higher bits except the least significant bit of the n bit; The timing controller has n-bit first modulation data having a value greater than the data value of the current frame in response to the increase in the data value and n having a value smaller than the data value of the current frame in response to the reduction in the data value. Register the second modulated data of the bit in a lookup table, compare the source data of the previous frame of n-1 bits with the source data of the current frame of n-1 bits, supplied from the comparator and perform the And one of the first and second modulated data is selected and supplied to the data driver. delete The method of claim 5, wherein The timing controller, And selecting the first modulated data when the source data value of the current frame is increased from the previous frame, and selecting the second modulated data when the source data value of the current frame is decreased from the previous frame. Drive of display device. The method of claim 5, wherein A data driver for supplying modulation data from the timing controller to a data line of the liquid crystal panel; A gate driver for supplying a scan signal to a gate line of the liquid crystal panel; And the timing controller controls the data driver and the gate driver. delete The method of claim 5, wherein N is '8' driving device of the liquid crystal display device. The method of claim 5, wherein The comparator, A plurality of exclusive logical gates for performing an exclusive logical product operation on the source data of the previous frame of n-1 bits and the source data of the current frame of n-1 bits from the memory; A logic circuit for outputting a low logic value if the outputs from the exclusive logical gates have the same logic value, and a high logic value if the outputs from the exclusive logical gates are not the same; Source data of an n-bit current frame is supplied to the data driver according to a low logic value from the logic circuit, and n-1 bit of source data of a previous frame of n-1 bits according to a high logic value from the logic circuit. And a data output unit for supplying source data of a current frame of bits to the timing controller.

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