KR100919186B1 - Driving circuit of liquid crystal display and driving method thereof - Google Patents

Abstract

The present invention relates to a driving circuit and a driving method of a liquid crystal display device, and more particularly, to a liquid crystal display device capable of minimizing the occurrence of electromagnetic interference and improving data transmission speed by connecting an optical fiber between a timing controller and a source driver. It relates to a driving circuit and a driving method of the. To this end, the present invention receives an electrical signal output from the timing controller converts the optical signal into an optical signal for outputting; Optical signal distribution means for receiving an optical signal outputted from the electro-optical conversion unit and distributing the optical signal to the source drivers; And an opto-electric converter connected to each of the source drivers to reconvert the optical signal into an electrical signal.

Description

Driving circuit and driving method of liquid crystal display device {DRIVING CIRCUIT OF LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit and a driving method of a liquid crystal display device, and more particularly, to generating electromagnetic interference (EMI) by connecting an optical fiber between a timing controller and a source driver. The present invention relates to a driving circuit and a driving method of a liquid crystal display device capable of minimizing the number and improving a data transmission speed.

Among the display devices for displaying image information on the screen, the thin-film flat panel display device has become an object of intensive development in recent years because of its advantages of being light and easily used in any place. In particular, since liquid crystal displays have high resolution and fast reaction speeds sufficient to realize moving images, the most active research is being conducted.

The principle of the liquid crystal display device is to use the optical anisotropy and polarization properties of the liquid crystal. That is, by artificially adjusting the alignment direction of the liquid crystal molecules having the directionality by using polarization, it is possible to transmit and block light with optical anisotropy according to the alignment direction, and use it as a screen display device.

Recently, an active matrix liquid crystal display in which thin film transistors and pixel electrodes connected thereto are arranged in a matrix manner is most popular because it provides excellent image quality.

1 is an exemplary view showing a conventional liquid crystal display device.

Referring to FIG. 1, image data DATA [R, G, B] and a control signal CS are applied to the timing controller 110 from an external graphic controller 190.

The timing controller 110 supplies a control signal CS to m gate drivers 180, and also supplies the image data DATA [R, G, B to n source drivers 170. ]) And the control signal CS. In this case, the timing controller 110 controls the driving timing of the gate driver 180 and the source driver 170 by supplying a predetermined clock signal, a gate start signal, and a timing signal as the control signal CS.

The gate driver 180 receives a control signal CS of the timing controller 110 and sequentially supplies a gate pulse to a gate wiring through a gate pad part (not shown) of the liquid crystal panel 101.

The source driver 170 converts the image data DATA [R, G, B], which are digital signals output from the timing controller 110, into an analog signal, thereby converting the liquid crystal panel 101 according to the control signal CS. It is supplied to a data line through a data pad (not shown).

Accordingly, the liquid crystal panel 101 displays an image according to the gate pulse supplied through the gate driver 180 and the image data supplied through the source driver 170 as described above.

As described above, in order to display an image through a liquid crystal display, a connection line for transmitting image data DATA [R, G, B] must be provided between the timing controller 110 and the source driver 170. .

The number of colors that can be displayed in the liquid crystal display is determined by the number of bits of the red (R), green (G), and blue (B) image data DATA [R, G, B]. For example, when the number of bits is 6, red (R), green (G), and blue (B) each have a six-bit gray level. At this time, the timing controller 110 and the source driver 170 are separated. 19 connection wires are required for transferring the image data DATA [R, G, B]. 18 of the 19 connection wires are provided for the transmission of the image data DATA [R, G, B] of red (R), green (G), and blue (B) each having a six-bit gradation. One connection line is provided to transmit the control signal CS between the timing controller 110 and the source driver 170.

As described above, in order to transfer image data DATA [R, G, B] and a control signal between the timing controller 110 and the source driver 170, a connection line is used in a parallel manner.

However, as the liquid crystal display device is driven to become high quality and large screen in consideration of the user's preference, the number of connection wires for transmitting digital image data DATA [R, G, B] and various control signals increases. In addition, the clock frequency of the transmission signals is increased for high speed operation.

In general, each connection wiring forms an electric field induced by the flow of current according to the transmission signal, and this electric field acts as a noise to the transmission signal of the adjacent connection wiring, which hinders normal driving of the product. The EMI phenomenon is further exacerbated, especially when the number of connection wires and the clock frequency of transmission signals increase as described above.

The driving circuit and driving method of the conventional liquid crystal display have the following problems.

First, as described above, 18 pieces of connection wirings for transferring image data between a timing controller and a source driver are applied when transmitting 6-bit color image data having a XGA resolution to a single port. When 8-bit image data signals in true color mode are transmitted to a single port, 24 are applied and data must be transmitted / received every clock at a high frequency of 65 MHz. Therefore, a large amount of noise is generated due to EMI, which is necessary for data transmission. Power consumption will also increase. In addition, as the resolution and image quality of the liquid crystal display device improve, the amount of data to be transmitted per unit time increases, thus generating noise and power consumption due to EMI as described above.

Second, in order to reduce such a problem, a separate component is connected to each connection wiring in a printed circuit board (PCB), and the number of connection wirings is doubled to reduce the data transmission rate to half (32.5MHz). Although the dual port method is used, the number of connection wirings has doubled, causing difficulties in the design of the printed circuit board. Also, in the resolution of XGA or higher, satisfactory EMI reduction effect cannot be expected. Countermeasures are required.

Accordingly, an object of the present invention is to solve the above problems by minimizing the number of connection wires for data transmission between the timing controller and the source driver.

In order to achieve the above object, an embodiment of the present invention includes a plurality of source drivers and a plurality of gate drivers for applying signals to data lines and gate lines of a liquid crystal display device; A timing controller which receives an electrical signal including a data signal and a control signal from a graphic controller and converts the electrical signal into a signal that can be processed by the source driver and the gate driver and outputs the electrical signal; An electric-optical signal converter for receiving an electric signal output from the timing controller and converting the electric signal into an optical signal; Optical signal distribution means for receiving an optical signal output from the electric-optical signal converter and distributing the optical signal to the source drivers; And an opto-electric converter connected to each of the source drivers to reconvert the optical signal into an electrical signal.

The optical signal distribution means includes an optical splitter; A first optical fiber unit connecting the optical splitter and the electric-optical signal converter; And a second optical fiber unit connecting the optical splitter and the photo-electric converter.

The timing controller further includes a parallel-serial converter for converting a parallel signal into a serial signal.

The source driver further includes a serial-parallel converter for converting a serial signal into a parallel signal.

The first optical fiber unit is preferably composed of four strands of optical fibers for transmitting data signals and control signals of R, G, and B, respectively.

Preferably, the second optical fiber unit is connected to each of four source optical fibers which transmit data signals and control signals of R, G, and B to each of the source drivers.

In addition, in order to achieve the above object, the present invention receives an electrical signal including a data signal and a control signal from the outside in the form of a parallel signal to convert the source driver and the gate driver into a signal that can be processed to output the electrical signal. Controller; A parallel-serial signal conversion circuit for converting the parallel electric signal output from the timing controller into a serial electric signal; And an electric-optical signal converting circuit for receiving an electrical signal output from the parallel-serial signal converting circuit and converting the electrical signal into an optical signal.

In addition, the present invention is an optical-electric conversion unit for receiving an optical signal in the form of a serial signal from the timing controller to convert the optical signal into an electrical signal to achieve the above object; A serial-parallel converter for converting the serial signal into a parallel signal; And a source driver for receiving a parallel signal output from the serial-parallel converter and applying the parallel signal output to each data line of the liquid crystal display.

In order to achieve the above object, the present invention includes a signal output step of receiving a data signal and a control signal from the outside and converting the signal into a signal that can be processed by the source driver and the gate driver to output the data signal and the control signal as an electrical signal; An electro-optical conversion step of receiving a data signal which is the output electrical signal and converting the data signal into an optical signal; A signal distribution step of distributing the optical signal to the source driver; An optical-electric conversion step of converting the optical signal into an electrical signal and outputting the converted optical signal; And a pixel voltage applying step of applying the electric signal to each data line.

The signal output step preferably includes a parallel-serial conversion step of converting an input data signal into a serial signal.

The pixel voltage applying step preferably includes a parallel-serial conversion step of converting an input data signal into a parallel signal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is an exemplary view showing a liquid crystal display device according to an embodiment of the present invention.

As described in the prior art, a case of a liquid crystal display that represents 6-bit color image data and has an XGA-class resolution will be described as an example. If R, G, and B are controlled by 6 bits, respectively, the transmittance of each subpixel can be adjusted in 64 steps, and one pixel can express the number of colors of 2 ¹⁸ . LCD panels with XGA resolution have 1024 * 768 pixels.

In the liquid crystal display according to the exemplary embodiment of the present invention, as shown, a screen is constructed of image data DATA [R, G, B] and control signals CS supplied from a graphic controller 290 such as a computer. The timing control unit 200 adjusts and outputs the timing so that the timing control unit 200 fits the control signal, and converts the image data DATA [R, G, B], which are digital signals output from the timing control unit 200, into analog signals to convert the control signal ( Gate pulses to the gate lines of the liquid crystal panel according to the n source driver 240 supplied to the liquid crystal panel 201 for a given time according to CS and the control signal CS provided from the timing controller 200. M gate drivers (280) for applying the configuration.

The source driver 240 and the gate driver 280 are installed outside the liquid crystal panel 201 and electrically connected to the timing controller 200 installed on a printed circuit board (PCB).

The timing controller 200 includes a timing controller 210, a parallel-serial converter 220, and an electro-optical converter 230, and the source driver 240 includes an opto-electric converter 250. , A serial-parallel converter 260 and a source driver 270.

The timing controller 200 and the n source drivers 240 are electrically connected to each other through four connection wires. Three connection wirings are for image data DATA [R, G, B] of R, G, and B, and one connection wiring is for control signal CS.

In addition, the m gate drivers 280 are electrically connected to the timing controller 210 of the timing controller 200 to receive various control signals.

Hereinafter, the configuration and operation of the liquid crystal display according to the embodiment of the present invention will be described in more detail.

3 is a block diagram showing the configuration of the timing controller.

The timing controller 200 includes a timing controller 210, a parallel-serial converter 220, and an electro-optical converter 230 as shown.

The connection line 300 connecting the timing controller 210 and the parallel-to-serial conversion unit 220 includes six R-connection wires, six G-connection wires, six B-connection wires, and one for control signals. Including 19. Since high frequency signals are transmitted through 19 connection lines, it is expected that a large amount of EMI will be generated in this area, but the influence can be ignored because of the relatively short signal transmission distance.

The parallel-serial converter 220 converts an externally input parallel data signal into a serial data signal for each of R, G, and B. Therefore, the parallel-to-serial converter has four output wires 310 for R, G, B and control signals.

The parallel-serial converter 220 is electrically connected to the electro-optical converter 230 through an amplifier 340. The electro-light conversion unit 230 includes a light emitting diode or a laser diode. The light emitting diode or the laser diode generates an optical signal having a different intensity according to the voltage of the applied electric signal, and the optical signal is input to the optical fiber 320 for each of R, G, and B. One wire not connected to the amplifier 340 serves as a ground wire for applying a voltage to a light emitting diode or a laser diode of the electro-optical converter 230.

In the electro-optical converter 230, four optical fibers 320 for transmitting image data DATA [R, G, B] and control signals CS of R, G, and B are optical splitters 330. 4 optical fibers are connected to each source control unit by the optical splitter 330.

The operation of the timing controller 200 configured as described above is as follows.

The timing controller 200 transmits 64 gray (6 bits) image data to each source driver 240 using three connection lines, one bit for each connection line for each clock (clk), for a total of 3 bits / clock. Image data is transferred at the transmission speed.

Each of the three connection wires is composed of R-connection wires, G-connection wires, and B-connection wires, so that digital image data is transmitted one bit each for R, G, and B during each clock.

4 shows connection wirings through which optical signals are distributed by the optical splitter.

As shown, the number of connection wires for transferring the image data between the timing controller 200 and each source driver 240 is 1 for each of the three connection wires (R, G, B) when 6-bit color image data is transmitted. Wirings) and one control wiring for transmitting the control signal CS.

When transmitting image data having an XGA-class resolution, high frequency image data of about 170 MHz is transmitted in parallel on three connection lines. Data of each pixel is sequentially stored in the source driver 240 according to a clock applied to the source driver 240.

5 shows the configuration of each source driver as a video signal driver in the liquid crystal display.

As illustrated, the source driver 240 includes an opto-electric converter 250, a parallel-serial converter 260, and a source driver 270.

The photo-electric converter 250 is connected to four optical fibers 520 connected to the optical splitter. The photo-electric converter 250 includes a photo diode, which is a photodetector, to convert an input optical signal into an electrical signal having a voltage corresponding to the size.

The converted electrical signal is amplified by a ratio through the amplifier 540 and then input to the series-parallel converter 260. One wire not connected to the amplifier 540 serves as a ground wire for applying a voltage to the photodiode of the photo-electric converter 250.

The serial-parallel converter 260 receives 18 bits of data required for displaying one pixel during six clock passes. The serial-parallel converter 260 includes a latch for storing data during six clock passes.

The serial-parallel converter 260 receives 18 bits of data, converts the data in parallel, and transmits the data to the source driver 270 through 18 wires of 1 bit each.

When the 384 output driver is employed in the XGA class liquid crystal display, eight source drivers 270 are arranged. If one source driver 270 drives 128 pixels, one pixel is composed of R, G, and B so that 384 data lines can be driven.

The 18-bit image data thus transferred is converted into an analog signal in each source driver 270 and used to drive one pixel in the liquid crystal panel for a predetermined time.

In the case of an XGA-class liquid crystal display having 60 frames per second, each gate wiring is sequentially driven at about 21.7 ㎲ intervals, which is called one horizontal period.

In order to transfer one row of image data from a timing controller to a source driver, 1024 clocks are required, and conventionally, a clock of 65 MHz has been used.

In the XGA-class liquid crystal display, the number of clocks in one horizontal period is more than 1024, so the image data transmission speed is not a big problem, but as the liquid crystal panel becomes large, it requires a faster transmission speed. . When the liquid crystal panel is large, one horizontal period is shortened and the resolution is high, which requires a high number of clocks.

Therefore, when the timing controller and the source driver is connected to the optical fiber as in the present invention, the data transmission rate of 170 MHz is guaranteed due to the wideband characteristic of the optical fiber and no signal interference occurs between the connection wires. Therefore, even if data is transmitted serially instead of the conventional parallel signal transmission method, it is possible to transmit all of one column of data in one horizontal period in the large liquid crystal panel.

Many details are set forth in the foregoing description, but they should be construed as preferred embodiments rather than limiting the scope of the invention.

For example, the parallel-to-serial converter and the electro-optical converter can be formed separately without one-chip with the conventional timing controller and the source driver.

Therefore, the scope of the invention should not be defined by the described embodiments, but should be defined by the claims and the equivalents of the claims.

According to the present invention has the following effects.

First, by using the optical fiber as the connection wiring between the conventional timing controller and the source driver, the number of connection wirings can be significantly reduced, and thus power consumption can be reduced. In the case of a 6-bit XGA-class resolution, 18 connection wires have been conventionally required for R, G, and B image data transmission, but according to the present invention, only three connection wires are used.

Second, since the light does not interfere with each other, the present invention using the optical fiber can minimize the generation of EMI. In the case of a 6-bit XGA resolution, EMI is largely generated because image data, which is an electrical signal, must be transmitted / received at a high frequency of about 65 MHz in parallel on 18 connection lines.

Third, since light has a wide bandwidth, data can be transmitted / received at a frequency of 170 MHz, so that the driving circuit of the present invention can be applied even if the resolution is improved or the number of bits representing R, G, and B is increased.

1 is an exemplary view showing a conventional liquid crystal display device.

2 is an exemplary view showing a liquid crystal display device according to the present invention.

3 is a block diagram showing a configuration of a timing controller of the present invention.

4 is a plan view of a liquid crystal display device showing a connection wiring according to the present invention.

5 is a block diagram showing a configuration of a source driver of the present invention.

*** Description of the symbols for the main parts of the drawings ***

101,201: liquid crystal panel 110,210: timing controller

170,270: source driver 200: timing control unit

220: parallel-serial conversion unit 230: electric-light conversion unit

240: source driver 250: optical-electric converter

180,280: Gate Driver 190,290: Graphic Controller

300, 310, 500, 510: connection wiring 320, 520: optical fiber

330: optical splitter 340, 540: amplifier

Claims (11)

A plurality of source drivers and a plurality of gate drivers for applying signals to data lines and gate lines of the liquid crystal display device; A timing controller which receives an electrical signal including a data signal and a control signal from a graphic controller and converts the electrical signal into a signal that can be processed by the source driver and the gate driver and outputs the electrical signal; An electro-optical conversion unit which receives an electrical signal output from the timing controller and converts the electrical signal into an optical signal; Optical signal distribution means for receiving an optical signal outputted from the electro-optical conversion unit and distributing the optical signal to the source drivers; And A photo-electric converter connected to each of the source drivers and reconverting the optical signal into an electrical signal, The optical signal distribution means, Optical splitter; A first optical fiber unit connecting the optical splitter and the electro-optical converter; And A second optical fiber unit connecting the optical splitter and the photo-electric converter; The driving circuit of the liquid crystal display device comprising a. delete The driving circuit of claim 1, wherein the timing controller further comprises a parallel-serial conversion unit for converting a parallel signal into a serial signal. The driving circuit of claim 1, wherein the source driver further comprises a series-parallel converter configured to convert a serial signal into a parallel signal. The driving circuit of claim 1, wherein the first optical fiber unit comprises three optical fibers for transmitting image data of each of R, G, and B, and one optical fiber for transmitting a control signal. The driving circuit of claim 1, wherein the second optical fiber unit is connected to four strands of optical fibers which transmit image data and control signals of R, G, and B to the respective source drivers. delete delete A signal output step of receiving image data and a control signal and converting the signal into a signal that can be processed by the source driver and the gate driver and outputting the data signal and the control signal as an electrical signal; An electro-optical conversion step of receiving a data signal which is the output electrical signal and converting the data signal into an optical signal and outputting the same through an optical fiber; A signal distribution step of distributing an optical signal from the first optical fiber and distributing and outputting the optical signal to the source driver through a second optical fiber; An optical-electric conversion step of reconverting and outputting the optical signal from the second optical fiber into an electrical signal; And A pixel voltage applying step of applying the electrical signal to each data line; Circuit driving method of the liquid crystal display device comprising a. 10. The circuit driving method of claim 9, wherein the signal output step includes a parallel-serial conversion step of converting an input data signal into a serial signal. 10. The circuit driving method of claim 9, wherein the pixel voltage applying step includes a series-parallel conversion step of converting input image data into a parallel signal.