KR100918297B1 - Raster circuit capable of controlling timing of video mixing system - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a raster circuit capable of timing control of a video mixing system. More specifically, the present invention relates to a pixel and a symbol removed by a symbol kill signal when mixing an external image supplied from a camera and a symbol image supplied from a raster circuit. By enabling synchronization in the raster circuit, accurate synchronization can be achieved and distortion of the video signal can be prevented.

Video, Mixing, External Video, Symbol Video, Video Enhancement, Distortion, Sync

Description

Raster circuit that can control timing of video mixing system {RASTER CIRCUIT CAPABLE OF CONTROLLING TIMING OF VIDEO MIXING SYSTEM}

1 is a waveform diagram for explaining an image signal

2 is a block diagram schematically illustrating a configuration of a conventional video mixing system.

3 is an explanatory diagram illustrating a process of mixing and displaying an external image and a symbol image in a conventional video mixing system;

4 is a timing diagram showing the timing of each signal in a conventional video mixing system.

5 is an explanatory diagram for explaining symbol reinforcement during basic image mixing

6 is a block diagram showing the configuration of a raster circuit in FIG.

FIG. 7 is a timing diagram for illustrating timing of output signals of respective components of the raster circuit of FIG. 6. FIG.

8 is a timing diagram illustrating timing of a signal input to a conventional video mixing system.

9 is a block diagram schematically illustrating a configuration of a raster circuit capable of timing control of a video mixing system according to the present invention.

10 is a timing diagram for illustrating timing of an output signal of a raster circuit capable of timing control of a video mixing system according to the present invention.                 

<Description of the symbols for the main parts of the drawings>

30, 100: raster circuit 31, 110: pixel clock generator

32, 130: Ram D / A converter 33, 140: Kill signal supply

120: divider 150: buffer

160: shift registers 161 to 164: first to fourth D-flip flops

170: multiplexer 180: microprocessor

The present invention relates to a video mixing system. Specifically, when mixing an external image supplied from a camera and a symbol image supplied from a raster circuit, a raster circuit synchronizes a symbol and a pixel removed by a symbol kill signal. The present invention relates to a raster circuit capable of controlling the timing of a video mixing system in which accurate synchronization is performed to prevent distortion of an image signal.

First, the video signal will be described. The video signal is a signal indicating the brightness of the video, and the brightness is determined according to the level. The lightest color, the highest level, is white, and the darkest color, the lowest, is black.

1 is a waveform diagram illustrating a video signal.

As shown in Fig. 1, the green level is 1Vp-p (75Ω), and 0V to 0.286V are sync signals. Red and blue are the same as green, but there is only the brightness part of the image without the sync signal part. 1 means one horizontal scanning line, and horizontal and vertical synchronization signals are loaded on the green signal.

As shown in FIG. 2, the video mixing system 10 generally includes a camera 20, a raster circuit 30, a mux circuit 40, and a monitor 50.

2 is a block diagram schematically illustrating a configuration of a conventional video mixing system.

The camera 20 supplies an external image.

The raster circuit 30 generates and supplies a symbol kill signal and a symbol image for symbol enhancement.

The MUX circuit 40 receives an external image supplied from the camera 20, a symbol kill signal and a symbol image supplied from the raster circuit 30, amplifies the image signal, and then mixes and outputs the mixed image signal. In this case, when there is no input of the symbol image, the mux circuit 40 immediately outputs an external image. Here, the mux circuit 40 includes a plurality of amplification circuits, a high pass filter, a butter, a mixing circuit, and the like.

The monitor 50 displays an image output from the mux circuit 40.

This conventional video mixing system will be described with reference to FIGS. 3 and 4 as follows.

FIG. 3 is an explanatory diagram illustrating a process of mixing and displaying an external image and a symbol image in a conventional video mixing system, and FIG. 4 is a timing diagram illustrating timing of each signal of a conventional video mixing system.

The mux circuit 40 receives an external image signal, a symbol image supplied from the raster circuit 30, and a symbol kill signal for symbol enhancement from the camera 20. Here, the symbol kill signal is an active high signal controlled by the raster circuit 30 and is used to mix an external image and a symbol image, and the external image is removed while the signal is activated, and the horizontal symbol enhancement is performed through this function. Function and video mixing function.

Then, the mux circuit 40 amplifies the input signal, and then outputs it directly to the monitor 50 when only an external image is input through the camera 20 and displays it. At this time, when the external image and the symbol image are input, as shown in FIG. 3, the image, the symbol image, and the symbol kill signal, which combine the two images, are mixed as shown in FIG. 4.

Meanwhile, symbol enhancement during image mixing will be described with reference to FIG. 5.

5 is an explanatory diagram for explaining symbol reinforcement during basic image mixing.

FIG. 5 illustrates a case in which symbol enhancement is applied and not applied in image mixing, and when a symbol image and a symbol kill signal are not synchronized.

When mixing an external image such as a and a symbol image such as b, if symbol enhancement is applied, it is displayed as c, and if symbol enhancement is not applied, it is displayed as d. At this time, when the symbol image is not synchronized with the symbol kill signal when the symbol enhancement is applied, e and f are displayed. That is, when the symbol image and the symbol kill signal are not synchronized, the source is distorted.

The reason why the synchronization of the symbol image and the symbol kill signal is inconsistent is that a problem occurs while the external image and the symbol image are mixed in the mux circuit. The reason for this will be described in detail with reference to FIGS. 6 to 8. same.

FIG. 6 is a block diagram showing the configuration of the raster circuit of FIG. 2, and FIG. 7 is a timing diagram for illustrating the timing of the output signal of each component of the raster circuit of FIG. 6, and FIG. 8 is input to a conventional video mixing system. It is a timing diagram for showing the timing of the signal to become.

6 and 7, the timing of the symbol image and the symbol kill signal provided by the raster circuit 30 is synchronized with the pixel clock provided from the pixel clock generator 31 to the RAM D / A converter 32. In other words, the D-flip-flop 34 is synchronized with the pixel clock provided from the pixel clock generator 31 and accordingly outputs the symbol kill signal supplied from the kill signal supply 33. 7 illustrates a form in which a symbol occupies 2 pixels and a symbol kill signal is provided for 2 pixels to the left and right.

As mentioned above, there is no problem in the output signal of the raster circuit, but a problem occurs when the external image and the symbol image are mixed in the mux circuit. The timing of each signal input to the mux circuit is well synchronized, but the mux In the circuit, two signals, i.e., an external image and a symbol image, are different from each other, and a delay occurs through each element inside the MUX circuit, resulting in a timing misalignment as shown in FIG. .

Therefore, an object of the present invention is to solve the above problems, the raster synchronization of the pixel and the symbol removed by the symbol kill signal when mixing the external image supplied from the camera and the symbol image supplied from the raster circuit raster By allowing the circuit to fit, accurate synchronization is achieved to prevent distortion of the video signal.

Features of the present invention for achieving the above object,

Input a camera for supplying an external image, a raster circuit for generating and supplying a symbol kill signal and a symbol image for symbol enhancement, an external image supplied from the camera, and a symbol kill signal and a symbol image supplied from the raster circuit. In a video mixing system comprising a mux circuit for receiving and amplifying a video signal and then mixing and outputting the video signal, and a monitor for displaying an image output from the mux circuit

The raster circuit,

A pixel clock generator for generating a pixel clock,

A divider for dividing the pixel clock generated from the pixel clock generator by N;

A RAM D / A converter receiving a pixel clock divided from the divider and outputting a symbol image;

A kill signal supply for supplying a kill signal,

A shift register synchronized with a pixel clock generated from the pixel clock generator, and outputting a plurality of kill signals by directly outputting a kill signal inputted from the kill signal supplier or sequentially delaying each clock signal by a clock;

A multiplexer for selectively selecting any one of a kill signal according to external control among a plurality of kill signals output from the shift register;

And a microprocessor for outputting a control signal such that any one kill signal is selected by the multiplexer according to the input selection signal.

Wherein the divider is

It is a four-minute period that divides the pixel clock generated from the pixel clock generator into four.

Here also between the pixel clock generator and the shift register,

A buffer is further provided for buffering the pixel clock.

Here, the shift register is

A first D-flip flop having an output terminal of the pixel clock generator connected in parallel to a clock terminal and an output terminal of the kill signal supply connected to an input terminal;

A second D flip-flop having an output terminal of the pixel clock generator connected in parallel to a clock stage and an input terminal of the pixel clock generator being connected to an output terminal of the first D flip-flop;

A third D flip-flop having an output terminal of the pixel clock generator connected in parallel to a clock terminal and an input terminal of the pixel clock generator being connected to an output terminal of the second D flip-flop;

An output terminal of the pixel clock generator is connected in parallel to a clock terminal, and a fourth D-flip flop is connected to an output terminal of the third D-flip flop.

Hereinafter, a configuration of a raster circuit capable of timing control of a video mixing system according to the present invention will be described in detail with reference to FIG. 9.

9 is a block diagram schematically illustrating a configuration of a raster circuit capable of timing control of a video mixing system according to the present invention.

9, a raster circuit 100 capable of timing control of a video mixing system according to the present invention includes a pixel clock generator 110, a divider 120, a RAM D / A converter 130, It is composed of a kill signal supply 140, a buffer 150, a shift register 160, a multiplexer 170, and a microprocessor 180.

 The pixel clock generator 110 generates a pixel clock.

The divider 120 divides the pixel clock generated from the pixel clock generator 110 into four quarters.

The RAM D / A converter 130 receives the divided pixel clock from the divider 120 and outputs a symbol image.

The kill signal supplier 140 supplies a kill signal.

The buffer 150 buffers the pixel clock output from the pixel clock generator 110.

The shift register 160 is synchronized to the pixel clock generated from the pixel clock generator 110, and directly outputs a kill signal input from the kill signal supplier 140 or sequentially delays each clock signal to output a plurality of kill signals. The output terminal of the pixel clock generator 110 and the output terminal of the pixel clock generator 110 and the first D-flip-flop 161 having the output terminal of the kill signal supply 140 connected to the input terminal in parallel. A second D flip-flop 162 connected in parallel with the clock terminal and having an input terminal connected to an output terminal of the first D flip-flop 161 and an output terminal of the pixel clock generator 110 in parallel with the clock terminal. A third D flip-flop 163 connected to an output terminal of the second D flip-flop 162 and an output terminal of the pixel clock generator 110 are connected in parallel to a clock terminal, and a third D A fourth D-flip having an input connected to the output of the flip-flop 163; It consists of a drop-164.

The multiplexer 170 selectively selects one kill signal according to external control among a plurality of kill signals output from the shift register 160.

The microprocessor 180 outputs a control signal such that any one kill signal is selected by the multiplexer 170 according to the input selection signal.

Hereinafter, an operation of a raster circuit capable of timing control of a video mixing system according to the present invention will be described in detail with reference to FIGS. 9 and 10.

10 is a timing diagram for illustrating timing of an output signal of a raster circuit capable of timing control of a video mixing system according to the present invention.

The divided clock 120 is selected four times faster than the required clock first, and the divided clock is provided to the RAM D / A converter 130, and the clock for the symbol kill signal retains the unbranched pixel clock. use.

Meanwhile, each D-flip-flop of the shift register 160 delays and outputs a kill signal by a clock. The delayed kill signal is selectively supplied to a mux circuit (not shown) using a multiplexer.

This will be described in more detail with reference to FIG. 10, wherein a portion indicated by a dotted line in the symbol kill signal of the figure is a timing when symbol enhancement is normally performed, and a portion indicated by a solid line means a timing shifted from the mixing circuit input of the mux circuit. .                     

To correct this, it is necessary to adjust the pixel clock, which outputs a control signal from the microprocessor 180 to the multiplexer 170 to change the setting of the shift register 160 to find an appropriate value and adjust the pixel clock. In this case, all these operations, that is, adjusting the pixel clock, are caused by not knowing the exact delay values of the devices used in different passes, so the adjuster visually checks the screen displayed on the monitor even during the actual adjustment. It is desirable to adjust the microprocessor to select an appropriate value.

In more detail, first, when the microprocessor outputs a selection signal to the multiplexer, the multiplexer receives a kill signal input through a specific input terminal among 0, 1, 2, 3, and 4. If the kill signal is input through the 0 input, this signal is no delay. If the kill signal is input through the 1 input, the signal is delayed by one clock. If the kill signal is input through the 2 input, the signal is The signal is delayed by two clocks, the three inputs are set clocks, and the four inputs are delayed signals by four clocks.

Thus, as shown in the figure, the delayed clock signal is supplied to the mux circuit by the timing shifted from the mixing circuit input of the mux circuit so that the synchronization is performed.

Therefore, by adjusting the pixel clock from the outside to synchronize, it is possible to prevent the image signal from being distorted.

As described above, according to the raster circuit capable of timing control of the video mixing system according to the present invention, a pixel and a symbol removed by a symbol kill signal when mixing an external image supplied from a camera and a symbol image supplied from a raster circuit are provided. By synchronizing with the raster circuit, accurate synchronization is achieved and distortion of the video signal can be prevented.

Claims (4)

A camera for supplying an external image, a raster circuit for generating and supplying a symbol kill signal and a symbol image for symbol enhancement, an external image supplied from the camera, and a symbol kill signal and a symbol image supplied from the raster circuit are received. A video mixing system comprising a mux circuit for amplifying a video signal and then mixing and outputting the video signal, and a monitor for displaying an image output from the mux circuit. The raster circuit, A pixel clock generator for generating a pixel clock, A divider for dividing the pixel clock generated from the pixel clock generator by N; A RAM D / A converter receiving a pixel clock divided from the divider and outputting a symbol image; A kill signal supply for supplying a kill signal, A shift register synchronized with a pixel clock generated from the pixel clock generator, and outputting a plurality of kill signals by directly outputting a kill signal inputted from the kill signal supplier or sequentially delaying each clock signal by a clock; A multiplexer for selectively selecting any one of a kill signal according to external control among a plurality of kill signals output from the shift register; And a microprocessor for outputting a control signal such that any one kill signal is selected in the multiplexer. The method of claim 1, The divider is, And a four-division period for dividing the pixel clock generated by the pixel clock generator into four quarters. The method of claim 1, Between the pixel clock generator and the shift register, And a buffer for buffering the pixel clock. The raster circuit capable of timing control of a video mixing system. The method of claim 1, The shift register, A first D-flip-flop having an output terminal of the pixel clock generator individually connected to each clock of the clock stage and an output terminal of the kill signal supply connected to an input terminal; A second D flip-flop having an input connected to an output end of the first D flip-flop; A third D flip-flop having an input connected to an output end of the second D flip-flop, And a fourth D flip-flop having an input connected to an output end of the third D flip-flop. 3.

Images