KR100916835B1 - METHOD OF PROCESSING PACKETS PER-FLOW USING NETWORK PROCESSOR IN DiffServ-over-MPLS - Google Patents

Abstract

The present invention discloses a packet processing method for each flow using a network processor in a differential service MPS network. According to the method of the present invention, when the ingress node processes the packet, if the MPS packet is decomposed according to the MAC type field by decomposing the received packet, the MPS packet according to the label in the shim header is used. MPLS) to an incoming label mapping (MPLS ILM) microblock and other packets to a range classifier; If the range classifier finds a flow that meets the specified policy, the packet is assigned to a specific flow ID, LS ID, and class ID. ; Metering step; Mark step of putting a class ID and color ID; Applying an MPLS (MPLS) process that matches a specific FEC in the MPLS FTN microblock after the mark; And the scheduler receives a packet from an MPLS incoming label map microblock or a general IPv4 processing or MPLS FMP to Next Hop (MPLS FTN) microblock, schedules a packet in a transmission queue, and transmits the packet to the switch network. It consists of steps.

MPLS, Class, Range Sorter, Scheduler, Linked List, Memory Management

Description

Differential service packet processing method using network processor in MPS network {METHOD OF PROCESSING PACKETS PER-FLOW USING NETWORK PROCESSOR IN DiffServ-over-MPLS}

1 is a diagram illustrating a differential service DiffServ-over-MPLS traffic engineering structure for processing a packet for each flow according to the present invention;

2 is a packet flow diagram in DiffServ-over-MPLS according to the present invention;

3 is a diagram illustrating an aggregated bitvector algorithm applied to the present invention;

4 is a queue state transition diagram according to the present invention;

5 is a conceptual diagram of a search engine design for searching an IP address according to the present invention;

6 illustrates a memory management concept designed for a range classifier in accordance with the present invention;

7 is a relationship diagram between a configuration utility, a core component, and a microblock according to the present invention;

8 is a conceptual diagram illustrating a queue state storing of a scheduler according to the present invention;

9 is an internal configuration diagram of an IXP2400 network processor used in an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

101,203: Sorter 108,209,215: Scheduler

201: Packet receiver 202: L2 decomposition / classifier

204, 212: M 205: Marker

206: MPLS FTN 207: MPLS ILM

211: Receive Queue 214: WRED

The present invention relates to a packet processing method in a DiffServ-over-MPLS network, and more particularly, to a packet processing method for each flow using a network processor in a differential service MPLS network.

In general, the DiffServ-over-MPLS architecture is designed to be simple and easy to implement and to operate at low overhead to support a range of network services. Differentiation Service (DiffServ) classifies flows into only a small number of classes to allocate network resources and provide quality of service (QoS). DiffServ provides differentiated forwarding to adapt different quality of service (QoS) to traffic types. Therefore, the differential service scheme does not require the signaling and maintenance of the policy according to the flow policy to the core network equipment. However, when traffic encounters a network device that does not have sufficient resources in a device that supports quality of service, the quality of service may not be guaranteed. That is, without sufficient resources required by the traffic, the network device cannot guarantee QoS.

Meanwhile, MPLS traffic engineering provides macroscopic traffic control. In addition, MPLS traffic engineering can fairly divide bandwidth and apply various segment recovery techniques. Differentiation Service (DiffServ) and Multiprotocol Label Switching (MPLS) techniques are presented and developed separately, but they are collectively referred to as "DiffServ-over-MPLS". Differentiation Service DiffServ-over-MPLS can provide quality of service (QoS) and a variety of granularities. However, in order to guarantee the quality of service (QoS) of the flow at high speed, a complex packet processing such as a classifier capable of distinguishing a large number of flows and a low-jitter packet scheduler is required.

Intel, on the other hand, offers a network processor known as the IXP2400 and a development tool known as the Intel IXDP2400. The Intel IXP2400 network processor provides an XScale embedded processor and eight microengines (ME), as shown in FIG. . Each microengine (ME) classifies packet processing functions at very high speeds, and is capable of metering, marking, queuing, and packet scheduling. The IXP2400 network processor can also accommodate 2.4Gbps traffic such as OC-48. XScale cores are used to establish relatively slow data paths and to execute control panel modules, such as when it is necessary to split packets arriving at the local system. The Intel IXDP2400 development platform is designed for access and edge applications that require OC-48 / 4Gbe speeds at full duplex OC-12 / 1GbE such as the OC-48 DSLAM. It consists of two IXP2400 chipsets. Instead of having a real CSIX switching optical interface, it has a CSIX loopback card. This allows debugging without any additional hardware, and Intel provides the IXDP2400 development platform, common libraries, and software development tools.

The INTEL IXA SDK 4.1 framework has the basic structure as a network application. In addition, transferable code structure and robust development software and APIs save development time and are ideal for applying external application modules. In a network processor, all functional modules are usually divided into core components and microblocks. The microblocks control general packet processing, while the core component is responsible for complex packet processing and controlling individual execution modules in the microblocks.

Currently, the Intel IXA_SDK only provides an Exact match classifier, and provides a limited number of 32 queues and a non-scalable scheduler. In other words, one of the most complex functional blocks in DiffServ-over-MPLS Processing is the range classification that should detect the flow to which the packet belongs. The IXA SDK Framework ) Does not include a software-based range classifier.

Most scheduling algorithms are very complex, as they are implemented on the IXP2400 microengine. The existing DRR (Deficit Round Robin) structure is well scalable but sends packets from queue to back-to-back when queue credit is larger than packet size. This process generates high jitter. In addition, the existing DRR scheduler implemented for the IXP2400 network processor included in the IXA SDK framework does not support a large number of queues because of the structure of using bitvectors to store queue state. Do not. These bitvectors are 32 bits long to read into the microengine's registers. Because of this, it is not possible to apply the DRR structure in a system with more than 32 queues, which, in turn, does not meet the goals of MPLS traffic engineering.

The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a packet processing method for each flow using a network processor in a DiffServ-over-MPLS network. That is, the present invention implements a DiffServ-over-MPLS packet processing system that can provide a quality-of-service for many high-speed flows.

In order to achieve the above object, in the method of the present invention, an ingress node, which is an edge router, transfers a packet transmitted from a subscriber network to a switch network consisting of switch routers, and an egress node transmits a packet transmitted from the switch network. In the DiffServ-over-MPLS network that delivers the data to the subscriber network,

The process of processing the packet by the ingress node,

Receiving a packet; If the received packet is decomposed and is an MPLS packet according to a MAC type field, the received packet is sent to an MPLS incoming label mapping (MPLS ILM) microblock according to a label in a shim header. Sending other packets to the range classifier; If the range classifier finds a flow that meets the specified policy, the packet is assigned with a specific flow ID, LSP ID, and class ID. Assigning the packet with a base class ID and sending the packet to general IPv4 processing; A metering step of finding a color value of the packet for each flow; A mark step of putting a class ID and a color ID into the DSCP field of the IP header of the packet after the metering; Applying an MPLS process that matches a specific FEC in the MPLS FEC to Nexthop (FTN) microblocks after the mark; And a scheduler receives a packet from the MPLS incoming label mapping (MPLS ILM) microblock or the general IPv4 processing or the MPLS F Two To Next Hop (MPLS FTN) microblock and transmits the packet to a transmission queue. Scheduling and transmitting to the switch network.

The processing of the packet by the egress node may include: reconstructing the packet according to LSP by metering the packet when the common switch interface (CSIX) receiving queue receives the packet from the switching fabric; Processing the weighted random early detection (WRED) microblock with a different profile according to the color value; And the scheduler issues a dequeue request in each cycle according to the bandwidth and priority of the LSP ID and class ID, and when the queue manager receives a dequeue message from the queue, The queue manager consists of sending packets to the media interface.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the implementation of the DiffServ-over-MPLS in the present invention is largely composed of a range classifier and a scheduler. Compared to the scheduler implementation implemented for the IXP2400 processor in the IXA SDK framework, the scheduler implementation in the present invention uses a different design for the queue state information storage space. In other words, by using a linked list for storing queue state information, the limited memory capacity of the system allows the use of bitvectors to support the same number of queues as the size of a microengine register.

1 is a diagram illustrating a DiffServ-over-MPLS traffic engineering structure for processing a packet for each flow according to the present invention, and FIG. 2 is a DiffServ-over-MPLS service according to the present invention. Is a packet flow diagram.

The DiffServ-over-MPLS traffic engineering architecture according to the present invention divides all IP packets entering the classifier 101 into respective flows, as shown in FIG. Each flow has a traffic parameter in which a committed Information Rate (CIR) and a Peak Information Rate (PIR) are defined that represent the corresponding burst sizes. After executing per-flow policing 102, each flow is mapped 104 to several Label Switched Paths (LSPs).

The MPLS label stack operation 105 processes incoming MPLS packets, and as a result, one output LSP set is generated. Each LSP has a bandwidth corresponding to it, and the bandwidth is greater than or equal to that of all incoming flows or LSPs. If the amount of traffic is exceeded, the bandwidth that is not currently being used is used to send the traffic, or the higher rank traffic is occupied first.

In the case of a flow where no policy is specified, the packet passes through the general IP processing 103, and the MPLS packet with the last label is processed like a normal IP by the classifier 101. In the case of the core router (LSR), packet processing is simpler because no traffic classification and flow metering is required. For flows that require very fine quality of service (QoS), a dedicated LSP can be used even if other flows of the same class type share the same LSP.

Classifier 101 uses an Aggregated BitVector algorithm, which executes each divided search in different fields 301 and returns the result 303, as shown in FIG. Are combined. Bitvectors 302 reduce the number of memory reads and allow for fast range classification.

The scheduler 108 has a complexity and uses a modified DRR (Deficit Round Robin) algorithm to provide a larger number of queues compared to the existing one provided by the IXA SDK framework. In the scheduler algorithm developed in the present invention, the queue has four states, as shown in FIG. Referring to FIG. 4, in the present invention, the queue has an active state 401, a scheduleable / empty 402, a suspended / backlogged 403, and a suspended state. It has four states, such as Suspended / Empty 404. Transition to Scheduled / Empty 402 by Scheduling in Active 401 State and Suspended / Empty by Decay in Scheduled / Empty 402 Empty) (404). Transition from Suspended / Empty 404 to Suspended / Backlogged 403 by enqueue, and in a new round in Suspended / Backlogged 403 By the transition to the active (401) state. Transition to Suspended / Backlogged 403 by dequeue / scheduling in Active state 401 and active by enqueue in Scheduleable / Empty 402. Active state 401

Next, the operation of the present invention will be described in detail by dividing the overall flow, the range classifier, and the scheduler.

1. The whole flow

FIG. 2 is a diagram illustrating an internal packet flow when processing packets at an ingress node and an egress node of a DiffServ-over-MPLS network according to the present invention. Ingress nodes include packet receiver 201 and L2 decomposition / classifier 202, range classifier 203, meter 204, marker 205, MPLS FTN 206, MPLS ILM 207, and IPv4 208. , MPLS switch composed of LSR routers, consisting of queue manager / fabric scheduler 209 and common switch interface transmission queue 210 to process packets transmitted from subscriber network at the entrance of MPLS network. The egress node to the common switch interface (CSIX) receive queue 211, meter 212, ARP 213, WRED 214, queue manager / scheduler 215, and transmit queue 216. It is configured to process the packets transmitted from the switch network at the exit of the MPLS switching network to transmit to the subscriber network. In an embodiment of the present invention, the ingress node is implemented as an IXP2400 network processor in the inlet label edge router (LER), and the egress node is implemented as an IXP2400 network processor in the exit label edge router (LER).

Referring to FIG. 2, when the ingress node receives a packet from the media reception interface 201, the ingress node is classified according to the MAC type field in the L2 decomposition / classifier 202, and the L2 header is removed.

If the received packet is an MPLS packet, the Sim (MPLS) Incoming Label Mapping (MPLS ILM) microblock 207 performs MPLS packet processing. shim) Sent according to a label in the header. The other packet is sent to a range classifier 203 which finds the forwarding equivalence class (FEC) of the packet. If it is determined by the last label, the packet is classified as a normal IP packet.

If the range classifier 203 finds a flow that meets the specified policy, the packet is assigned with a specific flow ID, LSP ID, and class ID. Flow ID is used in the metering microblock 204 to find the color value of packets based on per-flow metering.

The marker 205 puts a class ID and a color ID in the DSCP field of the IP header. The MPLS FEC to Nexthop (FTN) microblock 206 then applies MPLS operation matching the specific forwarding equalization class (FEC).

If the range classifier 203 cannot find a matching rule, the packet is assigned a base class ID and sent through normal IPv4 processing 208. The fabric transmitter microblock 210 transmits a packet in a single or multiple cell format to a CSIX interface. Each packet is divided into several C-frames and sent to the switching fabric. The first C-frame of the packet carries additional information such as LSP ID, class ID and next hop information.

Meanwhile, at the egress node, the common switch interface (CSIX) receive queue 211 receives a packet from the switching fabric, and the packet can be reconfigured according to LSP based on metering 212. have. The weighted random early detection (WRED) microblock 213, which processes packets in parallel with the meter 212, has different profiles according to color values. Once WRED is applied, the packet is sent to the queue manager microblock 215 in charge of putting it into a specific queue according to the LSP ID and class ID in the output port number. . The scheduler 215 generates a request to dequeue each cycle according to the bandwidth and priority of different LSP IDs and class IDs. When the queue manager 215 receives a dequeue message from the queue, the queue manager 215 queues specified in the transmit microblock 216 to send packets to the media interface. Retrieve packets from

2. Detailed Actions of Range Classifier

The range classifier 203 uses a multibit trie, as shown in FIG. 5, to find the corresponding class using individual fields requiring matching by range.

5, all intermediate trie nodes 503 contain 16 entries and can be found with 4 bit values. The IP address search engine has two tries that can be updated simply. The first trie 501 is used for prefixes with 16-bit values or more, and the second trie 502 is used for prefixes shorter than 16 bits. After the two IP trie search is completed, the bit OR operation is performed by the bitvector result before performing the bit AND operation of the results of all the search engines. Since all structures involved in the search are replaced by shared memory, a lot of memory fragmentation will occur during the memory allocation / return process. To avoid this problem, the present invention implements a simple memory management system as shown in FIG.

Referring to FIG. 6, the memory management module is for memory allocation of as many trie nodes 603 as possible and other data structures 604 requiring dynamic updates. The amount of memory allocated is set before the system is compiled and is chosen according to the amount of unused memory. After the memory is allocated, the indices of the minimum possible ones to the largest possible entries 602 are inserted into the unidirectional linked list. When a new entry is needed, one index is taken from the freelist and the entry marked with this index is used. When some entries are no longer used, its index is returned to the freelist. An empty freelist indicates that all allocated memory is being used.

This range classifier is composed of a core component (CC) 703, a microblock 701, and a configuration utility 704, as shown in FIG. 7. .

Referring to FIG. 7, the configuration utility 704 is implemented in the Xscale processor of the network processor, the core component 703 is implemented in the kernel space, and the microengine 701 and the Xscale processor are the memory subsystem 702. Use And the control plane applications 705 control the Xscale processor via CLI / socket via the network.

To configure the Classification database configuration utility, the system calls the kernel portion of the configuration device driver utility. The configuration device driver analyzes the given parameters and passes the message to the classifier core component (CC) 703 via a message helper function. When the Core Component Infrastructure finds that there are new messages in the queue, a message handler is called. The message handler performs the given configuration processing and calls a callback function that returns the result of the configuration utility.

3. Detailed operation of scheduler

8 is a conceptual diagram illustrating a queue state storing of a scheduler according to the present invention.

8, each level has an independent queue state information storage. The top layer of the storage layer is the port information table 801. The port information table 801 includes an entry 802 for each output port. Each port information table entry includes a scheduled packet counter 803, a current queue credit 804, a credit increment that defines the queue output rate 805, and an active queue list 806, 807. A pointer value for the < RTI ID = 0.0 >), < / RTI >

The packet processing method for each flow using a network processor in the differential service MPS network according to the present invention described above is not limited to the above-described embodiments, and the present invention may be made without departing from the gist of the present invention as claimed in the following claims. Anyone with ordinary knowledge in this field will have the technical spirit of the present invention to the extent that various modifications can be made.

As described above, the present invention implements a range classifier and a jitter-free scheduler using a network processor, and compared with a hardware-based implementation, the network processor-based implementation provides a faster and better architecture. Is easy to implement, and compared to general-purpose processor-based implementations, network processor-based implementations can process packets at high speed.

In addition, in the present invention, all IP packets are divided into respective flows by using a per-flow-based structure having flexible scalability and flexibility. ) Are assigned to each class's TE-LSP according to the characteristics of each flow, and each TE-LSP guarantees QoS requirements (eg bandwidth, jitter, delay, etc.) for each class. Features such as active queue management can be applied to ensure robust quality of service (QoS).

Claims (7)

DiffServ-over (DiffServ-over), which delivers the packet transmitted from the subscriber network to the switch network composed of switch routers by the ingress node, which is an edge router, and the packet transmitted by the egress node to the subscriber network. In the MPLS network, The process of processing the packet by the ingress node, Receiving a packet; If the received packet is decomposed and is an MPLS packet according to a MAC type field, the received packet is sent to an MPLS incoming label mapping (MPLS ILM) microblock according to a label in a shim header. Sending other packets to the range classifier; If the range classifier finds a flow that meets the specified policy, the packet is assigned with a specific flow ID, LSP ID, and class ID. Assigning the packet with a base class ID and sending the packet to general IPv4 processing; A metering step of finding a color value of the packet for each flow; A mark step of putting a class ID and a color ID into the DSCP field of the IP header of the packet after the metering; Applying an MPLS process that matches a specific FEC in the MPLS FEC to Nexthop (FTN) microblocks after the mark; And A scheduler receives a packet from the MPLS Incoming Label Mapping (MPLS ILM) microblock or the general IPv4 processing or the MPLS F Two To Next Hop (MPLS FTN) microblock and schedules it to a transmission queue. And transmitting to the switch network, The process of processing the packet by the egress node, When the Common Switch Interface (CSIX) receive queue receives a packet from the switching fabric, metering the packet to reconfigure according to LSP; Processing the weighted random early detection (WRED) microblock with a different profile according to the color value; And If the scheduler issues a dequeue request in each cycle according to the bandwidth and priority of the LSP ID and class ID, and the queue manager receives a dequeue message from the queue, the queue manager (queue manager) is a packet processing method for each flow using a network processor in the differential service MPLS network characterized in that it comprises the step of sending a packet to the media interface. delete The apparatus of claim 1, wherein the range classifier A core component implemented in software in a processor block of a network processor, a micro block for processing a packet, a configuration utility implemented in software in a processor block of a network processor, and a memory system. A packet processing method for each flow using a network processor in a differential service MPLS network. The apparatus of claim 3, wherein the range classifier A method of processing a packet for each flow using a network processor in a differential service MPLS network using a multibit trie to find a corresponding class using individual fields requiring matching by range. The memory system of claim 3, wherein the memory system comprises: A packet processing method for each flow using a network processor in a differential service MPS network, which is managed as a linked list. The method of claim 1, wherein the scheduler is Active state, scheduled / empty, suspended / backlogged, suspended / empty, etc. using a modified DRR algorithm A packet processing method for each flow using a network processor in a differential service MPLS network characterized by managing queues in four states. The method of claim 6, wherein the scheduler is It has independent queue state information storage for each level, the top layer of the storage hierarchy being a port information table, the port information table containing an entry for each output port, and each port information table entry being a scheduled packet. Differential service MP, which stores a counter, a credit increment that defines the current queue credit and queue output rate, a pointer value for the active queue list, and a pointer value for the suspended queue list. A packet processing method for each flow using a network processor in an LS network.

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