KR100915399B1 - Data partitioning and critical section reduction for bayesian network structure learning - Google Patents

Abstract

In a parallel system, multiple threads operate in parallel to perform network structure learning. The global score cache is divided into a number of separate score caches, which in one embodiment involves associating a score cache with a node of a structure to be learned. Training can be performed within a split neighbor scoring loop with a split score cache, where the first loop operates on a separate score cache partition and enables score cache splitting for the second loop. )do.

Description

STRUCTURE LEARNING METHOD, COMPUTER-READABLE STORAGE MEDIA, DEVICES AND SYSTEMS {DATA PARTITIONING AND CRITICAL SECTION REDUCTION FOR BAYESIAN NETWORK STRUCTURE LEARNING}

Embodiments of the present invention relate to network structure learning, and more particularly, to data partitioning for Bayesian network structure learning.

A large amount of information, especially related information, can be organized into a network structure. Bayesian networks are a common example of such a network structure. The use of Bayesian networks is increasing in bioinformatics, pattern recognition, and statistical calculations. Learning of Bayesian network structures is very computationally intensive, and the solution to finding a true "optimal" structure can be NP-complete. Although the learning of Bayesian network structures is very computationally intensive, networks with much larger data sets have been explored, which can increase computation intensity, potentially including exponential increases in computation intensity. have. Heuristic approaches sometimes focus on improving the performance efficiency of structural learning, for example by reducing execution time. Performance efficiency is becoming increasingly important in providing acceptable practical solutions for modern networks.

The parallel learning approach has been contemplated to include the resources of multiple computational machines and / or processing cores in executing structure learning algorithms. The parallel nature of this approach attempted to distribute the work among multiple resources to reduce the time it takes for any one system to find a solution. Conventional parallel learning distributes computation tasks in a basic, simple manner, which typically only takes into account the number of tasks allocated to each parallel computation resource in distributing computation tasks among parallel computation resources.

For example, in neighbor score computation, the main or master thread may distribute neighbor calculations among other available threads. In calculating Naver, the thread checks the score cache to determine whether a family score for the structure is known. The score cache is traditionally a data structure in which network family scores are obtained and stored, shared among threads, and accessed as hash tables. Once the score is obtained (as a result of a cache hit), the computational resource simply loads the score and uses that score to calculate the Naver score (directed acyclic graph, or score of the structure of interest). Can be. If the score is not obtained (as a result of a cache miss), a computing resource may be required to calculate the family score before calculating the neighbor score. Note that because the data structure is available to multiple threads, score cache access may be required to be present in a critical section to reduce overrunning of data. Thus, there may be a period in which a computational resource inefficiently uses that resource and / or remains idle while waiting for other computational resources to publish the score cache. Thus, it may be said that current or conventional multiprocessing / hyper-threading approaches to structure learning have failed to provide the required performance of structure learning for networks of increasing size and complexity.

The following detailed description has included several examples in the drawings and the accompanying drawings as examples only and not by way of limitation. This figure can be briefly described as follows.

1 is a block diagram illustrating one embodiment for a computing device having a partitioned score cache.

2 is a block diagram illustrating one embodiment for a multi-threaded computing device having a partitioned score cache.

3 is a flow diagram illustrating one embodiment for splitting a structure learning loop into an inner loop and an outer loop.

4 is a flow diagram illustrating one embodiment for structure learning with a split score cache.

In a very general sense, structure learning is applied to Bayesian networks as a way of discovering probable relationships between variables in a node's network, each representing information related to the condition / state and / or cause and / or effect of the condition / state. . Structure learning can represent a network by constructing a network structure representation based on the probability relationships of individual nodes. Hill-climbing is an algorithm that is sometimes used to learn static and / or dynamic Bayesian networks, and typically includes a score cache, which is a multidimensional sparse matrix implemented as a hash table. Can be. Each component of the matrix stores a score of a node family or a family of nodes (or simply referred to herein as a "family"). The family includes the current node or target node of interest (child node) and the parent node of the current node (or simply referred to herein as "parents"). Parent and target nodes may be associated according to a probability relationship. The score cache may be used to store the score of the family after the score is calculated.

In structure learning, the learning algorithm generally determines structure by first loading training data (known relationships) and calculating scores based on the training data and specific scoring metrics. The algorithm calculates a score for either the starting point or the initial current structure, which may be an initial user-defined Bayesian network structure in which structure learning will begin. A neighbor of the starting point (a structure separated by an edge difference from the current structure) may be generated, and the score of each neighbor may be calculated. Conventional approaches to scoring the calculations for each neighbor include searching the score cache to determine whether the score of the family corresponding to the neighbor has been verified or already calculated. Family scores can be considered unchanged, so once a score is calculated for one calculation, the score can be stored and reused in another calculation. If a family score is available, the score can be loaded directly and the Naver score is calculated. If a family score is not available, the score of the entire structure (including the family) is generally calculated and the score cache is updated. The process is typically repeated for every neighbor, and the algorithm selects the neighbor with the maximum score as the new current structure in which the next iteration of learning can begin. At best, the process is repeated until there is no neighbor that can have a higher score than the current structure. Practical applications sometimes use a heuristic approach because optimal solutions are not feasible or achievable as determined in one embodiment.

A common problem with structure learning is computational intensity and the long execution time associated with it. Parallelism can speed up the structure learning process by distributing NAVER scoring tasks / calculations to multiple threads (eg, parallel cores, arithmetic logic units (ALUs), processing cores, processors, central processing units (CPUs, etc.)). . In a simple parallelization approach, each thread can receive one or more neighbors to compute, which neighbors are equally distributed to the threads. The processes involved in accessing the score cache and / or the contents of the score cache may affect the performance of the thread, the generation of racing conditions, delays, and the like. The score cache is traditionally a single data structure accessible to each thread, which can result in the same state as described above. Current parallelization approaches involve creating a critical section to limit cache access to one thread at a time. Other approaches can store multiple versions of the cache, one for each thread, but this can lead to an unacceptable level of overhead penalty.

System efficiency can be improved by providing improved load-balancing between locality optimization and computational tasks. In addition, the scoring algorithm may be reconfigured to be executed to enable more efficient use and / or access of the score cache. In one embodiment, the score cache is divided into a number of lower portions. For example, the score cache may be an array of individually addressable memory structures, where each element of the array is a score cache for a node. For example, in a complex directed acyclic graph (DAG) where one contains thousands of nodes, failures caused by irregular access patterns of hash-index functions may be reduced by providing a score cache array. Can be. The failure of hash-indexing can be replaced by a failure associated with the higher overhead of managing the score cache. In large complex DAGs, the impairment for random / random access can be much higher than the impairment due to overhead.

For example, in gene network applications, a DAG can consist of thousands of nodes, meaning that the score cache must store millions of devices. The hash-index function can cause significantly higher failures than managing a score cache array with array elements for each of thousands of nodes. For example, random cache access to a gene-network with 2400 variables (which corresponds to a DAG having 2400 nodes) is higher than accessing a score cache generated by an addressable array of 2400 elements. May cause disability. In one embodiment each element represents a small score cache that stores only the scores of corresponding nodes in the genetic network.

In addition, the split score cache approach offers the opportunity to reorganize the neighbor of the current DAG within scoring. When evaluating neighbors that add or delete edges to the same node, the scoring algorithm (also the thread that executes the algorithm) accesses only one single score cache array element corresponding to a particular node (referred to herein as a split score cache). Thus, all the information necessary to complete the Naver calculation can be obtained. Thus, managing entries that distribute neighbors to scores can improve the locality of accessing the score cache by grouping neighbors associated with nodes. For a neighbor whose edge is reverse, two operations are involved, deleting the original edge and adding the edge in the opposite direction. In this case each reverse neighbor will access one split score cache for the child node and one split score cache for the parent node. Reverse neighbors can be grouped with neighbors that perform add / delete edges for the same child node, which can control the access pattern of the scoring / calculation function, thereby improving access locality. Improved locality results in faster execution. Note that split score cache with optimized access provides both temporal and geographic localization performance enhancement.

Partitioning data with a split score cache can also reduce the likelihood of data races or race conditions. If different end nodes are distributed to different threads, the possibility of interdependence of data between threads is reduced. A critical zone that can access the two score caches corresponding to the starting and ending nodes can also be used to calculate the reverse edge, but otherwise the use of the critical zone will be greatly reduced.

Thus, partitioning of the score cache may not only provide removal of several critical zones in a multi-threaded implementation of the scoring algorithm, but also improve data access locality, fine management capabilities for the scoring algorithm. In one embodiment, the main scoring loop is divided into two loops. In the first loop, a thread may be allowed to access only a portion of the score cache, which may be a different portion / sub-section than is available to other threads. Also, a thread in the first loop may attempt to "warm" the score cache for another thread. Activation of the score cache may include loading family scores for the one or more families associated with the node into the score cache. If the score cache was pre-loaded for use in the second loop by the process of the first loop, the second loop would be a critical zone due to the fact that each cache would only be read and not written. You may not need it. Loading the score cache in the first loop prevents cache misses from occurring in the second loop even though there is no critical section, and reduces or eliminates the possibility of data contention. As a result, multi-thread scalability is greatly increased in this approach. For example, experiments have shown that implementing this technique can provide 1.95x acceleration on dual processor (DP) simulaneous multi-processor (SMP) machines / systems. Also, due to the data partitioning described, an almost linear speed increase is obtained on SMP, on-chip multi-processor (CMP) and / or non-uniform memory access NUMA parallel processing machines with more processors or central processing units (CPUs). There is a possibility. Note that about 3-11% performance degradation can be observed in the scoring network with a small number of nodes due to the additional overhead incurred in memory and execution time to manage the split score cache.

Various references to "embodiments" herein are to be understood to describe particular features, structures or features included in at least one embodiment of the invention. Thus, expressions such as "in one embodiment" or "in another embodiment" and the like refer to various embodiments of the invention and not necessarily all refer to that embodiment.

1 is a block diagram illustrating one embodiment for a computing device having a partitioned score cache. Computing device 100 represents a computer, server, workstation or other computing device / device / machine. The computing device 100 may be multi-threaded to enable concurrent / parallel processing for different processes. Processor 110 represents one or more processing units and / or computing cores. The processor 110 may include a central processing unit, a microcontroller, a digital signal processor (DSP), an ALU, and the like. Processor 120 likewise represents one or more processing units and / or computing cores, and may include a central processing unit, microcontroller, DSP, ALU, and the like. Processors 110 and 120 may operate in parallel. In one embodiment, processors 110 and 120 represent parallel processing cores of computing device 100. In one embodiment, computing device 100 does not include a processor 120. The computing device 100 may represent a simulaneous multi-processor (SMP) system, an on-chip multi-processor (CMP) system, and / or other parallel processing non-uniform memory access (NUMA) system.

Memory 112 may provide storage for temporary variables and / or instructions executed by processor 110. Memory 112 may represent an on-chip memory, such as a cache hierarchy on processor 110, volatile storage on the system bus of computing device 100, system random access memory (RAM), and the like. Memory 112 may be accessed by direct access by processor 110, through a system bus, and / or a combination thereof. The memory 122 may be similarly described with respect to the processor 120. In one embodiment, the memory / cache is commonly accessible to both processors 110 and 120.

In one embodiment, the computing device 100 includes an input / output (I / O) interface 130, which may allow the computing device 100 to receive input from and / or provide output to an external source. Represents one or more mechanisms / devices that connect securely. External sources may include other computing systems, users, and the like, and may include display devices, cursor controls, alphanumeric input devices, audio input and / or output devices, visual displays (eg, light emitting diodes (LEDs), etc.). I / O interface 130 may also include a driver for the I / O device .. Information / data / instructions received via I / O interface 130 may include memory 112 and //. Or in memory 122 and / or mass storage 140. Mass storage 140 may be removable storage 142 (e.g., disk drive, memory stick / card /). One or more different storage mechanisms, including slots, universal serial bus (USB) connections, etc.) and non-volatile storage devices 144 (eg, disk drives, memory sticks / cards, hard disk drives, etc.). that Device 140 may store programs / applications and / or instructions loaded into memory 112 and / or 122 for execution on processor 110 and / or 120, and / or data associated with or associated with the program or instructions. Can be stored.

Data, instructions and / or program information may be provided by the machine / electronic device / hardware through the article of manufacture and executed by the computing device 100 / in the computing device 100. The article of manufacture may include a machine accessible / readable medium having content that provides instructions, data, and the like. Content can cause computing device 100 to perform the various operations and operations described. Machine-accessible media includes any mechanism for providing (ie, storing and / or transmitting) information / content in a form accessible by a machine (eg, computing device, electronic device, electronic system / subsystem, etc.). do. For example, a machine-accessible medium may be an electrical, optical, acoustical or other form of propagated signal (e.g., carrier waves, infrared signals, digital signals, etc.) as well as recordable / non-recordable media (e.g., For example, read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, and the like. The machine accessible medium may further comprise a computing system having code loaded into the computing system and executable by the computing system when the computing system is operating. Thus, delivering such code to a computing system can be understood to provide content such as that described above in an article of manufacture. In addition, storing the code in a database or other memory location and providing the code to be downloaded over a communication medium via a radio signal may be understood to provide content such as that described above in the article of manufacture.

In one embodiment, computing device 100 may include a network interface 150 that may include a wired or wireless interface and / or may include both a wired and wireless interface. Network interface 150 may represent a network card / circuit that enables computing device 100 to interface with a parallel computing device via a network.

In one embodiment, computing device 100 includes a score cache 160 that may represent one or more components that provide storage of values for structural learning of a data network. Score cache 160 may include multiple partitions / subsections / elements 161, which may be individually addressable memory locations / sections. Each location may be addressed / accessed by making each element of the array an element 161 to configure the score cache 160 as an array of elements. Score cache 160 may represent hardware and / or software components that manage storage hardware. In one embodiment, the score cache 160 represents a data structure accessible to the processor 110 and the processor 120. Storage of data and access to data within score cache 160 may be controlled to reduce data contention, improve locality, and remove one or more critical areas within the structure learning process. Score cache 160 is generally shown within computing device 100 and stored in mass storage device 140 to be executed on one or both of processors 110 or 120 and / or in memory 112 or 122. It can be understood as data residing in one or both.

2 is a block diagram illustrating one embodiment for a multi-threaded computing device having a partitioned score cache. Computing device 200 represents a device, system, apparatus and / or computer that implements / controls execution of a program. The computing device 200 may execute some or all of the network structure learning functions or programs. Computing device 200 includes a number of threads from 1 to N, where N represents an integer. For example, threads 1 through N may represent multiple parallel computing resources on an SMP, CMP, or NUMA machine. In one embodiment, computing device 200 also includes a score cache 210 partitioned into a number of sub-parts from sub 1 to sub M, where M represents an integer that may or may not be equal to N. . For example, computing device 200 may include two threads and partition score cache 210 into 1000 elements. In another example, the computing device may include sixteen threads and divide the score cache into twenty elements. The description of the techniques herein is not limited to this or any other specific implementation. This approach is scalable to multiple parallel computing resources (threads) and can be scaled from small network learning structures to large complex learning structures.

Each partition, sub 1 through sub M, may contain multiple entries, which may or may not be the same number of entries for each partition. The representation of FIG. 2 is for illustration only and is not intended to represent the number of entries that may be associated with any particular partition. In one embodiment each partition is associated with a different node in the network structure to learn. An entry may represent a value of a different family associated with each node or may represent a different node state (eg, a relationship with another node). If a value is calculated and stored in, for example, sub 1, this value can be assumed to be a constant. Thus, this value is once scored, stored in the entry of sub 1, and can be individually addressed for later access for use in the calculation of later neighbor scores.

sub 1 to sub M may be accessed by any one of threads 1 to N, respectively. In one embodiment, access from multiple threads is controlled for different partitions. Access can be controlled by the organization of computational tasks to be executed by threads. For example, thread N may be any continuous task that computes each entry of subM. In subsequent computations, if thread 1 accesses sub M, all values will be calculated and there will be no cache miss in access by thread 1. In this way, since the value of the entry will not change, thread 1 and thread N can access sub M without requiring a critical section.

In one embodiment, communication network 220 may represent a wide area network (WAN), for example, the Internet, or may represent a local area network (LAN), or other local interconnection between computers. Communication network 220 may represent a combination of LAN and WAN, and may include wired and / or wireless connections / links. The communication network 220 representing the interconnection of computing devices should not be confused with a data network or network structure (eg, Bayesian network) that refers to the logical representation of the information and the internal relationships of the information.

In one embodiment, the database (DB) 240 is coupled with the computing device 200, which may be a direct link or, for example, a communication interface through the communication network 220. In this example, communication network 220 may represent one or more intermediate connections between computing device 200 and database 240. Database 240 may represent any number of database hardware devices, servers, etc., capable of storing information / data. In one embodiment, the database 240 includes information related to the network structure to be learned. For example, database 240 may include evidence (eg, known data, training data) that allows one or more families or other network structures to be derived. Thus, the database 240 may include data that allows the structure to be learned, data that enables the determination of the neighbor, and the family associated with the neighbor. Database 240 may also be considered to store the network structure itself. The handle to the network structure may be generated by one of the threads of the database 240 and / or computing device 200. The information in database 240 may be used to calculate family scores to be loaded into score cache 210.

3 is a flow diagram illustrating one embodiment for dividing a structure learning loop into an inner and an outer loop. In starting structure learning, the structure can be selected as a starting point and the neighbor can be determined. The determination of the neighbor and the selection of one or more startup structures may be executed by the main thread. The main thread can distribute the neighbor computation work to multiple parallel computing threads, including the main thread itself. In either the main thread or the parallel thread, an initial score is calculated 302. This calculation and any other calculations, operations, and executions derived from the components of FIG. 3 can be said to be executed in multiple threads, concurrently or nearly simultaneously, and operate in parallel. The starting point may be selected based on a given criterion / parameter in the structure learning program, randomly selected, or based on other reasons. The thread selects a node in the DAG as an end node (304), and selects a given node as a start node (306). The end node is the child node to which the arcs will face. The starting node is a parent node, and the relationship of parent and child between two nodes is represented by arc or edge. The starting and ending nodes may also be arbitrarily selected, such as in the first of a list of nodes, or based on some other criteria. In one embodiment this selection is not important.

The thread determines 310 whether there is an edge from the start node to the end node. For example, the thread accesses the score cache to determine whether the value of the edge has been calculated. In the case of a split score cache, access to the score cache is performed on the score cache, or on a segment or segment of the score cache associated with the node. If no edge exists, the thread determines 320 whether adding an edge will create a valid neighbor. If a valid neighbor will be generated, a new edge is added to calculate the new score of the ending node (322). The thread may determine the neighbor score based on the new edge, determine if the neighbor score is better than the current highest neighbor, and if the calculated neighbor score is better, update the highest scoring neighbor (324).

If no edge exists, the thread may determine whether the reverse edge will generate a valid neighbor (330). If a valid neighbor will be generated, a new score of the start node and end node can be calculated (332). The thread determines the neighbor score based on the new edge, determines if the neighbor score is better than the current highest neighbor, and updates the highest scoring neighbor if the calculated neighbor score is better. After the highest scoring neighbor is updated, if the edge from the starting node to the ending node does not produce a valid neighbor, or if the reverse edge does not produce a valid neighbor, then the thread determines whether the scored starting node is the last starting node for the selected ending node. It is determined whether or not (340). This decision allows the split or split score cache to be used in providing better locality for faster execution of the scoring algorithm. For example, the split score cache may have a single addressable memory location for the ending node, with each entry in the memory location representing a score associated with the ending node for the starting node. Note that the roles of the end node and the start node can be changed while producing similar results.

If the start node is not the last start node, then the next start node is selected (342), and the process repeats until all start nodes have been processed. Once all start nodes have been processed, the thread determines 350 whether all end nodes have been processed. This structure provides a first loop and a second loop, where the first loop processes the value of the score cache for the node. In this way the first loop loads the cache to be used by the second loop and activates the score cache. If the last ending node has not been processed, the next ending node is selected (352), and processing begins for that ending node. If the last ending node has been processed, the thread determines 360 whether the learning is complete. When learning is completed at the node, the current DAG is updated and scored 362, and the process repeats until the Naver's score is no higher than the score of the current structure. If the best scoring neighbor is found, the last learned DAG is output (364).

4 is a flow diagram illustrating an embodiment of structure learning with a split score cache. The main or master thread calculates 402 an initial score for the structure to be learned. Initial scores provide a starting point for learning. The master thread prepares for thread task dispatching for parallel threads based on the split score cache architecture (404). In one embodiment, the main score cache data structure is divided into a number of small or separate score caches, which may allow one split score cache to be allocated for each node of the network to be learned. Score calculation may be distributed (dispatched) to parallel threads for processing. The segregation characteristic of the score cache allows a certain amount of work to be executed sequentially (as opposed to parallel), so that some optimization in work distribution is reduced in the system.

The master thread distributes computational work to each available thread, that is, thread 1 to thread N. The calculation may include some or all of the operations of calculating the score of the neighbor. Each thread calculates the score of the effective neighbor (412, 422). Since the score cache is detached, a thread can allocate a score calculation that does not conflict in the first loop of neighbor calculations. Traditionally, parallelization has consisted of creating all neighbors and equally distributing them to threads to compute them. The thread then processes each assigned neighbor. However, first, the thread can search the score cache to see if the score has been calculated for the Naver calculation, so the fact that only the global score cache has traditionally been used avoids data races (competitive conditions) and ensures thread stability. This meant that score cache access would need to be monitored by the critical zone. This is because if the query is lost, the thread calculates the score and updates the score cache. In this case, different threads may attempt to write to the same entry in the global score cache.

However, the critical section reduces the benefit of parallelism by having portions of a multi-threaded program run sequentially, which greatly reduces scalability. For example, up to 60% of the run time may be executed sequentially due to critical regions in the execution of the genetic network. Amdah's law states that when 60% of the execution time is sequential, the dual processor system is limited to an acceleration of l ((l-0.60) /2+0.60) = 1.25 times or less, and the quad processor system is l /((l-0.60)/4+0.60)=1.43 times less acceleration. This corresponds only to potential linear acceleration of 0.625 or 0.358, respectively. It will be appreciated that increasing the number of processors exacerbates the discrepancy between linear acceleration and actual acceleration.

With a split score cache, the main neighbor scoring loop of each learning iteration can be split into two fewer loops. The first loop processes the neighbor of the add / delete edge and activates the split score cache in the case of the corresponding reverse edge. In one embodiment, this can be done without a critical section because all data / actions are completely partitioned to prevent thread collisions in the score cache data. Since the calculated score is written to the split score cache, the system of threads can be synchronized, and all subsequent queries to the score cache result in a score cache hit, eliminating the need to rewrite the score cache. Thus, since all necessary calculations have been performed in the first loop, the second (later) loop can handle the reverse edge neighbor by reading the split score cache without a critical section.

Thus, intra-thread access 414, 424 of the detached score cache is executed by a thread in a score cache partition (eg, elements of a score cache array) that is only processed by a particular thread. The thread may score a value for the node associated with the score cache partition and load the score cache for subsequent inter-thread access (416, 426), which may be the second loop as described above. have. The thread selects the neighbor with the highest score (418, 428), and although one embodiment may be designed such that the lowest score or the score closest to a particular value is the highest score, this value is typically in a hill-climbing implementation. It will be the best score.

The processing executed by the various parallel threads is typically synchronized 430 by the master thread selecting the current processed neighbor with the highest score. The second loop may then be processed to determine whether there is a better scored neighbor. The operation is again dispatched for several parallel threads, and the thread calculates the score of the valid neighbor with a thread-to-thread split score cache access (442, 452). Note that since the split score cache was loaded with previously enabled or calculated scores, the thread does not need to perform any score calculations. Thus, even though a thread does not operate on data that is completely isolated or data that is isolated from access by another thread, this operation can be executed without a critical section. The thread selects the neighbor with the highest score here (444, 454), the selection of the individual threads is synchronized, and the highest neighbor in the system is updated with the highest score (462). The current best neighbor can be controlled by a master thread that determines whether one of the neighbors scored by the thread is better than the current best neighbor.

The master thread may then apply the neighbor to the DAG and update the score (464). When the learning is completed (470), the final learned DAG is output (472). If the learning is not completed, the learning is repeated 474 to determine the neighbor with the better score. Learning can be completed based on a number of criteria for a particular implementation. For example, the criterion may be that the neighbor is the highest neighbor in the number of critical iterations, the number of critical iterations has been reached, the time limit of the calculation is reached, and the like.

In addition to those described herein, various modifications may be made to embodiments of the invention without departing from the scope of the invention. Therefore, the description and examples herein should be regarded as illustrative and not in a limiting sense. The scope of the invention should only be determined by the claims which follow.

Claims (20)

As a structure learning method, A first thread for scoring a task of a structure learning scoring process, the first thread accessing only a first portion of a global scoring cache for the scoring task and for use in the scoring task; Calculating a value-assigning to, A second thread to perform an additional score calculation operation-the second thread accesses a second partition of the global score cache for the additional score calculation operation, does not access the first partition of the global score cache, and Assigning in parallel a second value to be used in an additional scoring operation, The first and second threads respectively store the first value and the second value in the first partition of the global score cache and the second partition of the global score cache. Structure learning method. The method of claim 1, Assigning the score calculation task and the additional score calculation task to the first thread and the second thread includes assigning the task to the first and second processors of a concurrent multi-processor system. Structure learning method. The method of claim 1, Assigning the score calculation task and the additional score calculation task to the first thread and the second thread comprises assigning tasks to the first and second processing cores of an on-chip multi-processor system. Containing steps Structure learning method. The method of claim 1, The first thread accessing the first partition includes a first thread accessing the first partition of the global score cache shared without a critical section. Structure learning method. The method of claim 1, The first and second dividers include addressable elements of a divider array. Structure learning method. The method of claim 5, wherein The addressable element of the partition array comprises an element associated with a node of a Bayesian network, Each said node associated with a device of said partition array. Structure learning method. The method of claim 1, The structure of the additional score calculation includes a node, and the scoring operation includes neighbor scoring of a neighbor having a node different from the node of the structure of the additional score calculation. Structure learning method. A computer readable storage medium having contents providing instructions for causing a machine to perform an action, The operation is, Associating a direct addressable cache partition with each node of the Bayesian network; Distributing neighbor calculations associated with one of the nodes of the Bayesian network to a first parallel thread, the first parallel thread accessing the direct addressable cache partition associated with the one node to perform the neighbor calculation. Obtaining information about-and, Distributing neighbor calculations associated with additional ones of said nodes of said Bayesian network to second parallel threads, said second parallel threads accessing said direct addressable cache partition associated with said additional nodes to provide information about said neighbor calculations; Obtained-containing Computer-readable storage media. The method of claim 8, Content providing instructions that cause the machine to perform the operation of associating the direct addressable cache partition to each node provide a direct unique address that indexes to a memory location within the data structure in which the machine has an address. Containing content that provides instructions to enable Computer-readable storage media. The method of claim 8, Content providing instructions that cause the machine to distribute the neighbor computations provide instructions that cause the machine to distribute computations for separate neighbors of non-interdependent nodes to the first and second parallel threads. Containing content Computer-readable storage media. The method of claim 8, The first and second parallel threads comprise first and second computational resources of a system having a plurality of parallel computational resources sharing access to memory data structures. Computer-readable storage media. The method of claim 8, The direct addressable cache partition associated with the one node includes an entry for a family score of each family associated with the one node. Computer-readable storage media. The method of claim 8, The first storing the score of the calculated family for the one node and the additional node in the neighbor calculation, in the cache partition associated with the one node and the cache partition associated with the additional node; Further comprising a second parallel thread Computer-readable storage media. The method of claim 13, The content providing instructions for causing the machine to distribute the neighbor calculation is Content providing instructions for causing the machine to dispatch neighbor calculations for a first neighbor scoring sub-loop of a neighbor scoring loop of a hill-climbing algorithm; Further comprising content providing instructions for causing the machine to dispatch neighbor calculations for a second neighbor scoring sub-loop of the neighbor scoring loop of the hill-climbing algorithm; The first and second parallel threads access the family score stored in the cache partition during the first neighbor scoring sub-loop. Computer-readable storage media. A memory having data defining execution of an operation of repeating network structure learning; A processor coupled to the memory and executing the operation defined in the memory, The operation is, In a repetition of the structure learning, a neighboring scoring function is distributed to parallel threads for a first loop of neighbor scoring such that a first thread accesses a first element of a scoring cache array, and a second thread is assigned to the first element of the scoring cache array. 2 operation to access the device, Distributing an additional neighbor scoring function to the parallel threads for a second loop of neighbor scoring in the iteration of the structure learning so that the first thread is the first element of the score cache array and the second element of the score cache array. Or to access other elements of the score cache array. Device. The method of claim 15, Each element of the score cache array corresponds to a single node of the network structure to learn. Device. The method of claim 16, The memory includes the first and second elements of the score cache array in which the first and second threads have a family score for the family of single nodes corresponding to the first and second elements within the first loop. Further comprising data defining an operation of loading each of them so that they can be used later in the second loop. Device. Scoring the neighbor in a first loop, including accessing a first element of the score cache array with a first processing core, and accessing a second element of the score cache array with a second processing core; Scoring additional neighbors in a second loop, including accessing the first element of the score cache array or the second element of the score cache array with the first processing core A memory having data defining the execution of the operation of scoring a neighbor of a Bayesian network comprising: The first and second processing cores coupled to the memory and executing the operations defined in the memory; A database coupled to the memory and storing data for allowing the Bayesian network structure to be learned and providing the data to the memory System comprising a. The method of claim 18, The first and second processing cores include a first processor and a second processor of a plurality of processors in a multi-processor machine. system. The method of claim 18, The first and second processing cores include a first processing core and a second processing core of a plurality of processor cores of a multi-processor integrated circuit chip. system.