KR100915203B1 - Interference cancellation module, radio repeater having the same, and method thereof - Google Patents

Abstract

Disclosed are an interference cancellation module, a wireless repeater including the interference cancellation module, and a method thereof. The wireless repeater selectively receives the downlink signal generated by the downlink signal processor and the uplink signal generated by the uplink signal processor in response to the synchronization signal, and removes the first interference signal or the second interference signal from the selectively received signal. Including an interference canceling module for time-dividing the interference cancellation of the downlink signal and the uplink signal, repeater manufacturing cost, power consumption, There is an effect that can reduce the area, and heat generation.

Description

Interference cancellation module, a wireless repeater including the interference cancellation module, and a method thereof {Interference cancellation module, radio repeater having the same, and method}

The present invention relates to an interference signal cancellation technology in a wireless repeater, and more particularly, an interference cancellation module capable of removing interference signals as one module in up and down wireless communication, a wireless repeater including the interference cancellation module, and It's about how.

In general, the repeater is a device that is located in a place where the radio wave between the base station and the terminal is weak or not reachable to provide a good signal to the area to enable the corresponding service.

For example, the repeater is located between the base station and the terminal to convert the weak signal generated from the base station into a good signal to transmit to the terminal (hereinafter referred to as 'forward transmission' or 'downward transmission'), The weak signal generated from the terminal may be converted into a good signal and transmitted to the base station (hereinafter referred to as 'reverse transmission' or 'upward transmission').

The repeater may be a microwave repeater, an RF repeater, an optical repeater, or an interference canceling repeater. Among them, the interference cancellation repeater (ICS) is particularly used in a densely populated area or an urban area with poor wireless environment. An apparatus that plays an important role in ensuring stable service refers to a repeater that removes feedback signals generated due to lack of isolation of transmit and receive antennas in the forward and reverse transmissions.

The interference elimination repeater removes the feedback signal using a digital signal processing technique, and the interference elimination repeater according to the related art may be included in the forward transmission and the reverse transmission using different interference cancellation modules for forward transmission and reverse transmission. Remove each interference signal.

Therefore, since the interference elimination repeater includes at least two interference elimination modules, it can be expensive, and power consumption, area, and heat generation can be increased.

Accordingly, the technical problem to be achieved by the present invention is to provide an interference cancellation module capable of time-divisionally removing interference signals by implementing a single module for forward transmission and reverse transmission, a wireless repeater including the interference cancellation module, and a method thereof. will be.

Wireless repeater for achieving the technical problem is a first antenna for transmitting and receiving a radio signal with a base station; A second antenna for transmitting and receiving a wireless signal with the terminal; A downlink signal processor configured to receive a first analog signal including a first interference signal through the first antenna, process the received first analog signal, and convert the received first analog signal into a signal for transmission through the second antenna; An uplink signal processor configured to receive a second analog signal including a second interference signal through the second antenna, process the received second analog signal, and convert the received second analog signal into a signal for transmission through the first antenna; And selectively receiving a downlink signal generated by the downlink signal processor and an uplink signal generated by the uplink signal processor in response to the synchronization signal, and removing the first interference signal or the second interference signal from the selectively received signal. As a result, it may include an interference cancellation module for time-divisionally removing interference between the downlink signal and the uplink signal.

The interference cancellation module may be implemented as one digital signal processing (DSP) module.

The wireless repeater may further include a synchronization signal generator configured to generate the synchronization signal based on timing information included in the first analog signal or the second analog signal transmitted in a TDD scheme.

The interference cancellation module may include a first switch selectively receiving and outputting the downlink signal or the uplink signal; An analog-digital converter converting the output signal of the first switch into a first digital signal; An interference canceling unit estimating and removing the first interference signal or the second interference signal included in the first digital signal in response to the synchronization signal; A digital-analog converter converting the second digital signal output from the interference canceling unit into an analog signal; And a second switch selectively outputting the output signal of the digital-analog converter to the downlink signal processor or uplink signal processor.

The interference canceller may include a preprocessor configured to convert the first digital signal output from the analog-digital converter into a format suitable for interference signal cancellation in response to the synchronization signal; In response to the synchronization signal, a replication of the first digital signal and the second digital signal converted by the preprocessor is detected, and the first digital signal is converted from the converted first digital signal based on the simulation information corresponding to the detection result. An interference canceller for outputting the second digital signal by removing a first interference signal or the second interference signal; And a post processor configured to filter the second digital signal to a predetermined band.

The simulation information may include at least one of time, phase, and amplitude in which the converted first digital signal and the second digital signal have the simplicity.

The interference canceller calculates a first interference coefficient for removing the first interference signal or a second interference coefficient for removing the second interference signal based on the converted digital signal and the second digital signal. An interference signal estimation unit generating the first interference signal corresponding to the first interference coefficient or the second interference signal corresponding to the second interference coefficient in response to a synchronization signal; And a subtractor which subtracts the first interference signal or the second interference signal from the converted first digital signal and outputs a subtraction result as the second digital signal.

The interference signal estimator may include: a searcher for detecting the simplicity of the converted digital signal and the second digital signal in response to the synchronization signal and outputting the simulation information corresponding to a detection result; An interference coefficient processor for outputting the first interference signal or the second interference signal based on the simulation information; A first memory unit for storing the first interference coefficient; And a second memory unit storing the second interference coefficient.

The interference cancellation module further includes a selector for outputting the first interference coefficient stored in the first memory unit or the second interference coefficient stored in the second memory unit to the interference coefficient processor in response to the synchronization signal. The interference coefficient processor is configured to update the first interference coefficient or the second interference coefficient in real time based on the simulation information, and to adjust the first interference signal or the second interference signal corresponding to the updated coefficient. Output to the subtractor.

The wireless signal relay method for achieving the technical problem is, in response to the synchronization signal, the downlink signal including the first interference signal generated by the downlink signal processor and the uplink signal including the second interference signal generated by the uplink signal processor. A receiving step of selectively receiving; And an interference signal removing step of time-divisionally removing interference between the downlink signal and the uplink signal by removing the first interference signal or the second interference signal from the signal received in the reception step.

The interference signal removing step may be performed by one digital signal processing (DSP) module.

The wireless signal relay method may further include generating the synchronization signal based on timing information included in the uplink signal or the downlink signal transmitted in a TDD scheme.

The interference signal removing step may include: converting the signal received in the receiving step into a first digital signal; Estimating and removing the first interference signal or the second interference signal included in the first digital signal in response to the synchronization signal; Converting the second digital signal from which the first interference signal or the second interference signal is removed to an analog signal; And selectively outputting the second digital signal to the downlink signal processor or uplink signal processor.

As described above, the interference elimination module and its method according to the present invention can be implemented as a single interference elimination module to remove interference signals generated during forward and reverse transmission, thereby manufacturing costs, power consumption, area, And it is effective to reduce the heat.

As described above, the wireless repeater according to the present invention requires only one interference canceling module to remove the interference signal generated during the forward transmission and the reverse transmission, thereby reducing the manufacturing cost, power consumption, area, and heat generation of the wireless repeater. It can be effective.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram of a wireless repeater according to an embodiment of the present invention.

FIG. 2 is a diagram for describing a method of generating a synchronization signal by the synchronization signal generator of FIG. 1.

3 is a block diagram of the interference cancellation module of FIG. 1.

4 is a block diagram of the interference canceller of FIG. 4.

5 is a flowchart illustrating a method of removing an interference signal according to an exemplary embodiment of the present invention.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a block diagram of a wireless repeater according to an exemplary embodiment of the present invention, FIG. 2 is a diagram illustrating a method of generating a synchronization signal by the synchronization signal generator of FIG. 1, and FIG. 4 is a block diagram of the interference canceller of FIG. 3.

1 to 4, the wireless repeater 10 includes a first antenna 11, a down-unit, a down-unit, an up-unit, an interference cancellation module 21, and a synchronization signal generator. (Or, a synchronization detector module (SDM) 31, and a second antenna 41).

The wireless repeater 10 is located between a base station (not shown) and a terminal (not shown) to receive a weak signal generated from the base station through the first antenna 11 and receive the first analog signal Vr1. Is converted into a good signal (for example, a signal that has been removed from interference or noise and amplified), and then the converted second analog signal Vr11 is transmitted to the terminal through the second antenna 41 (hereinafter, 'forward transmission' or ' 'Downlink transmission'.

In addition, the wireless repeater 10 receives the third analog signal Vr22 generated from the terminal through the second antenna 41 and converts the received signal into a good signal (for example, a signal in which interference or noise is removed and amplified). In this case, the fourth analog signal Vr2 may be converted to the base station through the first antenna 11 (hereinafter, referred to as 'reverse transmission' or 'upward transmission').

The wireless repeater 10 may be an interference cancellation system (ICS) and may use a time division duplex (TDD) scheme.

As is known to those skilled in the art, the TDD scheme uses the same frequency for forward and reverse transmission as opposed to the FDD (Frequency Division Duplex) scheme for forward and reverse transmission. In the case of a backward transmission time domain, a signal (or a "downward signal") is transmitted in a reverse direction signal (or "upward signal").

The first antenna 11 may transmit and receive radio signals Vr1 and Vr2 with a base station (not shown).

The down-signal unit receives a first analog signal Vr1 including a first interference signal through the first antenna 11 and processes the received first analog signal Vr1 to process the received first analog signal Vr1. The second analog signal Vr11 may be converted into a second analog signal for transmission through the second antenna 41. The first interference signal may be a feedback signal that is directly or reflected by the signal transmitted through the second antenna 41 and is input to the first antenna 11.

The down-signal processing unit includes a first band pass filter 13, a first circulator 15, a first low noise amplifier 17, a first down converter 19, and a first up converter 23. , A first amplifier 25, a second circulator 27, and a second bandpass filter 29.

The first bandpass filter 13 may band-filter the first analog signal Vr1 including the first interference signal output from the base station through the first antenna 11 during forward transmission.

The first circulator 15 may forward-transmit the output signal of the first bandpass filter 13.

For example, the first circulator 15 induces an output signal of the first bandpass filter 13 in a forward direction (ie, outputs the output signal of the first bandpass filter 13 to a first low noise amplifier) during forward transmission. (17).

The sync signal TDD-sgn (FIG. 2) is a signal generated by the sync signal generator 31 and is generated based on the first analog signal Vr1 or the third analog signal Vr22 transmitted in the TDD scheme and is forward. In the case of the transmission time T1, the wireless repeater 10 enables forward transmission of the first analog signal Vr1, and in the case of the reverse transmission time T2, the wireless repeater 10 is the third analog signal. A signal for enabling reverse transmission of (Vr22) and a detailed description thereof will be described later.

The first low noise amplifier 17 may receive an output signal of the first bandpass filter 13 input through the first circulator 15 to amplify low noise, and the first low noise amplifier 17 The operation of may be enabled or disabled by the synchronization signal TDD-sgn.

The first down converter 19 down converts the signal output from the first low noise amplifier 17. For example, the first down converter 19 may convert a signal output from the first low noise amplifier 17 and a reference frequency signal (not shown) and down convert the intermediate frequency signal.

The first up converter 23 up-converts the first interference cancellation signal V15 output from the interference cancellation module 21. For example, the first up converter 23 may mix the first interference cancellation signal V15 and a reference frequency signal (not shown) to up-convert the RF signal.

The first amplifier 25 may amplify the output signal of the first up converter 23, and the operation of the first amplifier 25 may be enabled or disabled by the synchronization signal TDD-sgn. Can be.

The second circulator 27 may forward-transmit the output signal of the first amplifier 25.

For example, the second circulator 27 induces the output signal of the first amplifier 25 in the forward direction during forward transmission (that is, the second bandpass filter 29 derives the output signal of the first amplifier 25 in the forward direction. Can be sent to).

The second bandpass filter 29 may band-filter the output signal of the first amplifier 25 in the forward transmission.

The up-unit receives the second analog signal Vr22 including the second interference signal through the second antenna 41 and processes the received second analog signal Vr22 to perform the processing. The second interference signal may be converted into a signal Vr2 for transmission through the first antenna 11. The second interference signal may be directly or reflected by the signal transmitted through the first antenna 11. It may be a feedback signal input to 41.

The up-signal processor includes a second band pass filter 29, a second circulator 27, a second low noise amplifier 33, a second down converter 35, and a second up converter 37. , A second amplifier 39, a first circulator 15, and a first bandpass filter 13.

The second bandpass filter 29 may band-filter the third analog signal Vr22 input through the second antenna 41, and the second circulator 27 may perform the second bandpass filter ( 29) the output signal can be reversely transmitted.

For example, the second circulator 27 induces the output signal of the second bandpass filter 29 in the reverse direction (that is, the output signal of the second bandpass filter 29 to the second low noise amplifier 33). Transmission).

The second low noise amplifier 33 may receive the output signal of the second band pass filter 29 input through the second circulator 27 and amplify the low noise, and the second low noise amplifier 33 The operation of may be enabled or disabled by the synchronization signal TDD-sgn.

The second down converter 35 down converts the signal output from the second low noise amplifier 33. For example, the second down converter 35 may convert a signal output from the second low noise amplifier 33 and a reference frequency signal (not shown) to down convert the intermediate frequency signal.

The second up converter 37 up-converts the second interference cancellation signal V17 output from the interference cancellation module 21. For example, the second up converter 37 may mix the second interference cancellation signal V17 and a reference frequency signal (not shown) to up-convert the RF signal.

The second amplifier 39 may amplify the output signal of the second up converter 37, and the operation of the second amplifier 39 may be enabled or disabled by the synchronization signal TDD-sgn. Can be.

The first circulator 15 may reversely transmit an output signal of the second low noise amplifier 39.

For example, the first circulator 15 induces the output signal of the second low noise amplifier 39 in the reverse direction (ie, transmits the output signal of the second low noise amplifier 39 to the first bandpass filter 13). )can do.

The first bandpass filter 13 may band-filter the output signal of the second low noise amplifier 39 to transmit the band-filtered fourth analog signal Vr2 to the base station through the first antenna 11. .

The interference cancellation module 21 generates a downlink signal V1 generated by the down-signal unit and a uplink signal generated by the uplink signal processor Up-down in response to the synchronization signal TDD-sgn. Selectively receive (V2), and time-divisionally remove interference of the downlink signal (V1) or the uplink signal (V2) by removing the first interference signal or the second interference signal from the selectively received signal can do.

For example, the interference cancellation module 21 estimates or detects the first interference signal from the output signal of the first down converter 19 (that is, the downlink signal V1) in response to the synchronization signal TDD-sgn. By outputting the first interference cancellation signal (V15) or by estimating or detecting the second interference signal from the output signal of the second down converter 35 (that is, the upstream signal (V2)) by removing the second interference cancellation signal ( V17) can be output.

For example, the interference cancellation module 21 outputs the output signal V1 of the first down converter 19 in response to the synchronization signal TDD-sgn in a first logic level (eg, 'high level') state in the forward transmission. The first interference cancellation signal V15 may be output by estimating and removing the first interference signal at.

In addition, the interference cancellation module 21 outputs the output signal V2 of the second down converter 35 in response to the synchronization signal TDD-sgn in a second logic level (eg, 'low level') state in the reverse transmission. The second interference cancellation signal V17 may be output by estimating and removing the second interference signal at.

The interference cancellation module 21 may be implemented as one digital signal processing (DSP) module.

As shown in FIG. 3, the interference cancellation module 21 may include a first switch (or a first selector 51), an analog-digital converter 53, an interference canceler 54, and a digital-analog converter ( 61), a second switch (or second selector 63), and a sync signal distributor 65.

The first switch 51 selectively selects the output signal V1 of the first down converter 19 and the output signal V2 of the second down converter 35 in response to the synchronization signal TDD-sgn. The analog-digital converter 53 may transmit the data.

The analog-to-digital converter 53 controls the output signal V1 of the first down converter 19 or the output signal V2 of the second down converter 35 transmitted from the first switch 51. Can convert to 1 digital signal.

The interference canceling unit 54 may remove the first interference signal or the second interference signal included in the output signal of the analog-digital converter 53 in response to the synchronization signal TDD-sgn. .

The interference canceling unit 54 may include a preprocessor 55, an interference canceller 57, and a postprocessor 59. The preprocessor 55 may convert the first digital signal V5 output from the analog-digital converter 53 into a format suitable for interference signal cancellation in response to the synchronization signal TDD-sgn. have.

For example, the preprocessor 55 may digitally filter the first digital signal V5 to a predetermined bandwidth so that the interference canceller 57 may easily remove the interference signal.

The interference canceller 57 may include an interference signal estimator 71 and a subtractor 72 as shown in FIG. 4. The interference signal estimation unit 71 removes a first interference coefficient or the second interference signal for removing the first interference signal based on the converted first digital signal V7 and the second digital signal V9. Calculate a second interference coefficient to generate and output a first interference signal corresponding to the first interference coefficient or a second interference signal corresponding to the second interference coefficient in response to the synchronization signal TDD-sgn. Can be.

Specifically, the interference signal estimation unit 71 may include a searcher 73, an interference coefficient processor 74, a forward interference coefficient memory 76, a reverse interference coefficient memory 77, and a selector 79. .

The searcher 73 detects the replicability of the converted digital signal V7 and the second digital signal V9 in response to the synchronization signal TDD-sgn and outputs the simulation information corresponding to the detection result. can do. The simulation information is information representing the simplicity between the converted first digital signal V7 and the second digital signal V9. The simulation information includes the converted first digital signal V7 and the second digital signal. It may include a simulation point (or common point) with respect to the phase (Phase) and the amplitude (Amplitude) according to the time of (V9).

That is, the searcher 73 searches for replication of the converted first digital signal V7, that is, the interference canceller input signal and the second digital signal V9, that is, the interference canceller output signal. In this case, simulation information including at least one of time, phase, and amplitude information in which simulation is present is extracted in real time and provided to the interference coefficient processor 74.

The interference coefficient processor 74 generates the first interference coefficient or the second interference coefficient based on the simulation information received from the searcher 73, and generates the first interference signal or the first interference signal corresponding to the first interference coefficient. A second interference signal corresponding to the second interference coefficient may be estimated and output to the subtractor 72. The estimated first interference signal or the second interference signal may be a signal having the same amplitude based on time, phase, and amplitude information received from the searcher 73, but having opposite phases (ie, out of phase). have.

The first and second interference coefficients generated by the interference coefficient processor 74 may be stored in the forward interference coefficient memory 76 and the reverse interference coefficient memory 77, respectively.

The selector 79 may determine the first interference coefficient stored in the forward interference coefficient memory 76 or the second interference coefficient stored in the backward interference coefficient memory 77 in response to the synchronization signal TDD-sgn. Output to the interference coefficient processor 74.

For example, when forward transmission is started, the selector 79 generated by the interference coefficient processor 74 is a synchronization signal TDD-sgn of the first logic level (eg, high ('1') level) state. In response, the first interference coefficient stored in the forward interference coefficient memory 76 may be output to the interference coefficient processor 74.

In this case, the interference coefficient processor 74 generates a first interference signal corresponding to the first interference coefficient, and outputs the first interference signal to the subtractor 72. The subtractor 72 converts the first signal from the converted digital signal V7. The second digital signal V9 may be output by subtracting the interference signal.

The interference coefficient processor 74 may also update the first interference coefficient in real time based on the simulation information output from the searcher 73 and store the updated coefficient in the forward interference coefficient memory 76. have. In particular, the interference coefficient processor 74 preferably stores the last updated first interference coefficient in the forward interference coefficient memory 76 after the forward transmission is completed.

On the other hand, when reverse transmission is started, the selector 79 responds to the reverse interference coefficient memory 77 in response to the synchronization signal TDD-sgn at the second logic level (eg, low ('0') level) state. ) May output the second interference coefficient stored in the < RTI ID = 0.0 >

In this case, the interference coefficient processor 74 outputs a second interference signal corresponding to the second interference coefficient to the subtractor 72, and the subtractor 72 converts the second interference signal from the converted digital signal V7. May be subtracted to output the second digital signal V9.

The interference coefficient processor 74 may also update the second interference coefficient in real time based on the simulation information output from the searcher 73 and store the updated coefficient in the backward interference coefficient memory 77. have. In particular, the interference coefficient processor 74 preferably stores the last updated second interference coefficient in the backward interference coefficient memory 77 after the reverse transmission is completed.

As described above, the memory 76 for storing the interference coefficient (first interference coefficient) required for the interference cancellation of the downlink signal in the interference cancellation module 21 and the interference coefficient for the interference cancellation of the uplink signal (the second interference coefficient). The memory 77 for storing a) is provided separately, but most other components necessary for the interference cancellation of the uplink signal and the downlink signal are provided in common, and according to the present invention, even if the uplink and downlink cancellers are not set apart, You can effectively remove the signal.

Referring to FIG. 3 again, the post processor 59 outputs the filtered digital signal V11 by filtering the second digital signal V9 into a predetermined band.

The digital-analog converter 61 converts the digital signal V11 output from the post processor 59 into an analog signal and outputs the converted analog signal V13.

The second switch 63 converts the analog signal output from the digital-analog converter 61 in response to the synchronization signal TDD-sgn into a first interference cancellation signal V15 or a second interference cancellation signal V17. Can be output as

The sync signal distributor 65 may select the sync signal TDD-sgn generated by the sync signal generator 31 from at least one of the first switch 51, the interference canceller 54, and the second switch 63. You can distribute to one.

The sync signal generator 31 receives the output signal of the first low noise amplifier 17 and forward-transmits time T1 or third of the first analog signal Vr1 transmitted in a TDD scheme based on the received signal. A synchronization signal TDD-sgn (FIG. 2) having information on the reverse transmission time T2 of the analog signal Vr3 can be detected.

The synchronization signal TDD-sgn may correspond to a WiBro frame structure of a wibro communication method. For example, the forward transmission time T1 may correspond to the downlink of the WiBro frame structure and the reverse transmission time T2 may correspond to the uplink of the WiBro frame structure, respectively.

The synchronization signal generator 31 may detect the detected synchronization signal TDD-sgn (FIG. 2) by using a first band pass filter 13, a first circulator 15, a first low noise amplifier 17, and an interference cancellation module ( 21), the second circulator 27, the second bandpass filter 29, and the second low noise amplifier 33 are transmitted to at least one of the first analog signal Vr1 of the wireless repeater 10. Forward transmission or reverse transmission of the third analog signal Vr22 may be enabled.

That is, in the forward transmission (when the synchronization signal TDD-sgn (FIG. 2) is in a first logic level (for example, a high ('1') level) state), the down-signal processing unit (down-unit) receives the synchronization signal ( In response to TDD-sgn, a first analog signal Vr1 including a first interference signal is received through a first antenna 11, and the received first analog signal Vr1 is processed to process the second antenna ( 41 may be converted into a signal Vr11 for transmission.

In this case, the interference cancellation module 21 receives the downlink signal V1 generated by the down-signal unit in response to the synchronization signal TDD-sgn and receives the first interference signal from the received signal. Can be removed.

Also, in reverse transmission (when the synchronization signal TDD-sgn (FIG. 2) is in a second logic level (for example, low level)), an up-signal processing unit (Up-unit) is connected to the synchronization signal ( In response to TDD-sgn, a third analog signal Vr22 including a second interference signal is received through a second antenna 41, and the received third analog signal Vr22 is processed to process the first antenna ( 11) it can be converted into a signal Vr2 for transmission.

In this case, the interference cancellation module 21 receives the uplink signal V2 generated by the up-unit in response to the synchronization signal TDD-sgn and receives the second interference signal from the received signal. Can be removed.

Therefore, the wireless repeater 10 according to the embodiment of the present invention needs only one interference cancellation module 21 for removing interference signals generated during forward or reverse transmission time-divisionally, and thus, a manufacturing cost of the wireless repeater It is effective to reduce power consumption, area, and heat generation.

The second antenna 41 may transmit / receive wireless signals Vr11 and Vr22 with a terminal (not shown).

Components of the wireless repeater 10 may be changed or changed depending on the embodiment, or the connection relationship between the components may vary. For example, although not shown in FIG. 1, the wireless repeater 10 is input to the reference frequency signals input to the first and second down converters 19 and 35 and to the first and second up converters 23 and 37. The apparatus may further include a local oscillator for generating a reference frequency signal. The reference frequency signals input to the first and second down converters 19 and 35 and the first and second up converters 23 and 37 may be the same frequency or different frequencies depending on the embodiment. Further, for example, the output signal of the second low noise amplifier 33 may be connected as an input signal of the synchronization signal generator 31.

5 is a flowchart illustrating a method of removing an interference signal according to an exemplary embodiment of the present invention. Referring to FIGS. 1 and 5, the interference canceling unit 54 upwards from the downlink signal V1 including the first interference signal generated in the down-unit in response to the synchronization signal TDD-sgn. In operation S11, an upstream signal V2 including the second interference signal V2 generated by the signal processing unit Up-unit is selectively received.

The interference canceling unit 54 performs time division division cancellation on the downlink signal V1 and the uplink signal V2 by removing the first interference signal or the second interference signal from the signal received in operation S11. (S13).

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (17)

A first antenna for transmitting and receiving a radio signal with a base station; A second antenna for transmitting and receiving a wireless signal with the terminal; A downlink signal processor configured to receive a first analog signal including a first interference signal through the first antenna, process the received first analog signal, and convert the received first analog signal into a signal for transmission through the second antenna; An uplink signal processor configured to receive a second analog signal including a second interference signal through the second antenna, process the received second analog signal, and convert the received second analog signal into a signal for transmission through the first antenna; And One digital signal processing (DSP) module may be configured to selectively receive a downlink signal generated by the downlink signal processor and an uplink signal generated by the uplink signal processor in response to a synchronization signal, and selectively And an interference cancellation module for time-divisionally eliminating interference of the downlink signal and the uplink signal by removing the first interference signal or the second interference signal. delete According to claim 1, The wireless repeater, And a synchronization signal generator configured to generate the synchronization signal based on timing information included in the first analog signal or the second analog signal transmitted in a TDD scheme. The method of claim 1, wherein the interference cancellation module, A first switch for selectively receiving and outputting the down signal or the up signal; An analog-digital converter converting the output signal of the first switch into a first digital signal; An interference canceling unit estimating and removing the first interference signal or the second interference signal included in the first digital signal in response to the synchronization signal; A digital-analog converter converting the second digital signal output from the interference canceling unit into an analog signal; And And a second switch for selectively outputting the output signal of the digital-analog converter to the downlink signal processor or the uplink signal processor. The method of claim 4, wherein the interference cancellation unit, A preprocessor converting the first digital signal output from the analog-digital converter into a format suitable for interference signal cancellation in response to the synchronization signal; In response to the synchronization signal, a replication of the first digital signal and the second digital signal converted by the preprocessor is detected and based on the simulation information corresponding to the detection result, An interference canceller configured to output a second digital signal by removing a first interference signal or the second interference signal; And And a post processor for filtering the second digital signal into a predetermined band. The method of claim 5, wherein the simulation information, And the converted first digital signal and the second digital signal include at least one of time, phase, and amplitude having the simplicity. The method of claim 5, wherein the interference canceller, A first interference coefficient for removing the first interference signal or a second interference coefficient for removing the second interference signal is calculated based on the converted first digital signal and the second digital signal, and the synchronization signal is calculated. An interference signal estimator which generates in response the first interference signal corresponding to the first interference coefficient or the second interference signal corresponding to the second interference coefficient; And And a subtractor which subtracts the first interference signal or the second interference signal from the converted first digital signal and outputs a subtraction result as the second digital signal. The method of claim 7, wherein the interference signal estimation unit, A searcher for detecting the simplicity of the converted first digital signal and the second digital signal in response to the synchronization signal and outputting the simulation information corresponding to the detection result; An interference coefficient processor for outputting the first interference signal or the second interference signal based on the simulation information; A first memory unit for storing the first interference coefficient; And And a second memory unit for storing the second interference coefficient. The method of claim 8, wherein the interference cancellation module, And a selector for outputting the first interference coefficient stored in the first memory unit or the second interference coefficient stored in the second memory unit to the interference coefficient processor in response to the synchronization signal. The interference coefficient processor, Update the first interference coefficient or the second interference coefficient in real time based on the simulation information and generate and output the first interference signal or the second interference signal corresponding to the updated coefficient to the subtractor. Wireless repeater. In the interference cancellation module implemented by one DSP module, A receiving step of selectively receiving a downlink signal including a first interference signal generated by the downlink signal processor and an uplink signal including a second interference signal generated by the uplink signal processor in response to the synchronization signal; And And an interference signal removing step of time-dividing the interference of the downlink signal and the uplink signal by removing the first interference signal or the second interference signal from the signal received in the receiving step. delete The method of claim 10, wherein the wireless signal relay method, And generating the synchronization signal based on the timing information included in the uplink signal or the downlink signal transmitted in a TDD scheme. The method of claim 10, wherein the interference signal removing step, Converting the signal received in the receiving step into a first digital signal; Estimating and removing the first interference signal or the second interference signal included in the first digital signal in response to the synchronization signal; Converting the second digital signal from which the first interference signal or the second interference signal is removed to an analog signal; And And selectively outputting the second digital signal to the downlink signal processor or the uplink signal processor. The method of claim 13, wherein estimating and removing the first interference signal or the second interference signal comprises: A preprocessing step of converting and outputting the first digital signal into a format suitable for interference signal cancellation in response to the synchronization signal; Detecting replication of the first digital signal and the second digital signal converted in response to the synchronization signal; Generating an estimated first interference signal or an estimated second interference signal based on simulation information corresponding to the detection result; Subtracting the estimated first interference signal or the estimated second interference signal from the converted first digital signal and outputting the second digital signal; And A post-processing step of filtering the second digital signal into a predetermined band, The simulation information, And at least one of time, phase, and amplitude of the converted first digital signal and the second digital signal having the simplicity. A first switch for selectively receiving and outputting an uplink signal including a first interference signal and a downlink signal including a second interference signal in response to the synchronization signal; An analog-digital converter configured to convert the output signal of the first switch into a first digital signal; An interference canceller for time-dividing interference cancellation of the downlink signal and the uplink signal by estimating and removing the first interference signal or the second interference signal included in the first digital signal in response to the synchronization signal; And A second switch outputting the second digital signal output from the interference canceling unit to a Xiangyang signal processor or a downlink signal processor; The interference canceller may include: a preprocessor configured to convert the digital signal output from the analog-digital converter into a format suitable for interference signal cancellation in response to the synchronization signal; In response to the synchronization signal, a replication of the first digital signal and the second digital signal converted by the preprocessor is detected, and the first interference signal estimated based on the simulation information corresponding to the detection result, or An interference canceller for generating an estimated second interference signal and subtracting the estimated first interference signal or the estimated second interference signal from the converted first digital signal and outputting the second digital signal; And a post processor for filtering the second digital signal into a predetermined band. The interference canceller calculates a first interference coefficient for removing the first interference signal or a second interference coefficient for removing the second interference signal based on the converted first digital signal and the second digital signal. An interference signal estimator for generating the first interference signal corresponding to the first interference coefficient or the second interference signal corresponding to the second interference coefficient in response to the synchronization signal; And a subtractor which subtracts the first interference signal or the second interference signal from the converted first digital signal and outputs a subtraction result as the second digital signal. The interference signal estimator may include: a searcher for detecting the simplicity of the converted first digital signal and the second digital signal in response to the synchronization signal and outputting the simulation information corresponding to a detection result; An interference coefficient processor for outputting the first interference signal or the second interference signal based on the simulation information; A first memory unit for storing the first interference coefficient; And a second memory unit which stores the second interference coefficient. The method of claim 15, wherein the synchronization signal, And a synchronization signal generated based on timing information included in the uplink signal or the downlink signal transmitted in a TDD scheme. The method of claim 15, And a selector for outputting the first interference coefficient stored in the first memory unit or the second interference coefficient stored in the second memory unit to the interference coefficient processor in response to the synchronization signal. The interference coefficient processor is configured to update the first interference coefficient or the second interference coefficient in real time based on the simulation information, and to adjust the first interference signal or the second interference signal corresponding to the updated coefficient. Generating and outputting to the subtractor.