KR100911252B1 - Apparatus and method for testing a memory device - Google Patents

Abstract

An apparatus and a method for testing a memory device are provided to reduce a test time without an additional post process by determining the pass / fail of a block and a sector based on the result of the determination test. A pattern generation part(33) produces a test pattern, and a capture logic unit(32) reads data from a memory in which the test pattern is recorded. A comparison logic part(34) compares data and the test pattern read on the capture logic, and a fail logic determines whether a block is fail or not by accumulating the number of a fail bit in a test unit based on the comparison result. A defect block processing unit(36) accumulates the number of a defect block which is determined as a defect block, and stores the position of the detect block.

Description

Apparatus And Method For Testing A Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test apparatus and method, and more particularly, to a test apparatus and method of a NAND flash memory for determining whether a sector and a block are defective at the same time as a read test.

In general, a flash memory is a semiconductor memory capable of erasing and writing. The read, write, and erase modes are performed in a whole cell area or a specific size unit by a mode control command. Recorded data, ie programmed data, is retained with or without power supply.

Flash memory can be broadly divided into NAND flash memory and NOR flash memory.

NAND flash memory is used for products that require high-capacity data storage, such as MP3 players or digital cameras, and Noah flash memory is used for products that require low-capacity data storage, such as mobile phones or set-top boxes.

1 is an example of configuration diagram of a general NAND flash memory.

The NAND flash memory includes a cache register 11 and a data register 12 for temporarily storing data provided from the outside, and one or more memory cells and a memory cell for receiving and storing data from the data register 12. An array 13 and a control block (not shown) for controlling data storage and output of the cache register 11 and the data register 12, and the like.

The memory cell array 13 of FIG. 1 is an example of a storage capacity of 4,224 Mbits, which has a hierarchical internal architecture.

The memory cell array consists of 4,096 blocks, each of which consists of 64 pages (also called 'lines'). One page is mainly 2112 bytes (2,048 bytes + 64 bytes) long.

Each page is divided into four quarters of logical sectors of 512 bytes, as shown in FIG. An additional byte of 16 bytes divided by 64 bytes is combined with each 512 byte sector. This additional 16 bytes are used as an error correction code (ECC).

1 is only one example of the storage capacity of the NAND flash memory is 4,224 Mbit. The number of blocks constituting one memory cell array, the number of pages constituting each block, the length of one page, and the size of sectors that divide one page vary depending on the NAND flash memory storage capacity and circuit design. Can be.

NAND flash memory is not used as a whole storage unit because of its high capacity, but is used as a block or page unit. Thus, most tests of NAND flash memory are directed to be performed around blocks.

NAND flash memories require testing to efficiently evaluate their internal architecture and standard mode of use. Typically, a test is performed for each page, and a pass / fail of the corresponding page or block is determined according to the test result.

A test technique of a conventional NAND flash memory will be described.

A conventional NAND flash memory writes and reads a predetermined test pattern. The read result is compared with the test pattern bit by bit, and if the two bit values are the same, the corresponding bit is determined as a pass. If the two bit values are not the same, a failure is determined. In this specification, this process is called a read test.

As a result of this read test, a pass / fail is determined for each sector of the page. Since the error correction code (ECC) can be used for each sector, even if a sector fails, the sector is recognized as a pass if the number of fail bits is within the allowable number of bits. This allowable number of bits is determined by the semiconductor manufacturer and its customers, but should not exceed the number that can be corrected by the error correction code (ECC). If the number of fail bits in one sector exceeds the allowable number of bits, the block containing that sector is determined to be bad. In addition, if the number of bad blocks exceeds the allowable number of blocks, the NAND flash memory under test is treated as bad.

Conventionally, an error catch RAM is used to determine sector-by-sector pass / fail. That is, a read test is performed on all the memory cell arrays, and if a fail occurs in any bit, the fail information is written to the error catchram. As a post-process of the read test for all the memory cell arrays, the fail information recorded in the error catch ram is read again to determine whether sectors and blocks are to be failed, and whether or not the corresponding NAND flash memory is failed.

In order to accurately write the read test result to the error catch ram for each address of the memory cell array, the size of the memory cell array and the error catch ram must be the same. However, since the size of the error catch ram is directly proportional to the size of the error catch ram, the post processing time is too much.

So most NAND flash memory test equipment manufacturers use compression technology to reduce the size of the error catchram. That is, in each cell of the error catchram, read test results of cells that are positionally equivalent from different pages, different sectors, or both of one block of the memory cell array are written together. For example, the read test result for each cell constituting the first page of any one block is written to the error catchram, and the read test result for each cell constituting the second page of the same block is also written to the same error catchram. Is recorded.

Thus, each cell in the error catchramm simultaneously displays the read test results of several cells distributed in different pages or different sectors of one block of NAND flash memory. In the post-processing process, the result of the read test recorded in the error catch ram is used to determine whether the corresponding block is defective.

According to this compression, since the read test results of multiple pages or sectors are simultaneously written to one error catch ram, the time required for post-processing the read test results corresponding to one block is reduced, thereby improving test speed. There is an advantage.

On the other hand, in general, when a read test shows that the number of fail bits of individual sectors is within the allowable number of bits, the corresponding sector is determined as a pass. However, if the fail bits of multiple sectors are written to one error catchram by compression, the number of fail bits written to the error catchram may exceed the allowable number of bits, in which case the block is determined to fail. There is a danger. In other words, fail bits, which are scattered in a plurality of sectors, are compressed and recorded in one error catch ram, so that the corresponding block is determined as a fail.

Therefore, if the read test result is compressed, even if the number of fail-correctable errors occurs in the individual sectors, the block including the sector may be determined as bad, and the reason why the NAND flash memory under test is unnecessarily determined as bad is caused. There is a problem that can be.

SUMMARY OF THE INVENTION An object of the present invention is to provide a test apparatus and method for determining whether a block is failing without post-processing for reading and interpreting an error catchram that records a read test result. It is to.

Another object of the present invention is to provide a test apparatus and method without a block that is unnecessarily determined to fail even though it is determined to be a pass.

A memory test apparatus according to the present invention for achieving the above object comprises: a capture logic section for reading data from a memory in which a test pattern is recorded; A comparison logic unit for comparing the data read from the capture logic unit and the test pattern in units of bits of corresponding positions; And a fail logic unit configured to accumulate the number of fail bits for each test unit from the comparison result of the comparison logic unit to determine whether a block including the test units is defective.

In addition, the memory test method according to the present invention includes a capture step of reading data from a memory in which a test pattern is recorded; A comparison step of comparing the data read in the capturing step and the test pattern in bit units of mutually corresponding positions; And a fail determination step of determining whether a block including the test units is defective by accumulating the number of fail bits for each test unit from the comparison result of the comparing step.

According to the present invention, since the pass / fail of each sector is determined according to the read test at the same time as the read test, and whether or not the corresponding block is defective according to whether the sectors pass / fail, the post-process after the read test is performed separately. There is no need for the process, which shortens the test time.

In addition, since it is determined whether the corresponding sector is failed using only the read test result of each sector, there is no effect of a sector or block that is unnecessarily determined to fail, thereby improving the reliability of the test result.

In addition, if one sector is determined to be a failure, since the block to which the sector belongs is determined to be a bad block, a read test of the remaining sectors of the block can be omitted. The test time is further shortened because the NAND flash memory being used is determined early as bad and the read test for the remaining blocks can be omitted.

Hereinafter, a NAND flash memory test apparatus and method according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a NAND flash memory test apparatus according to an embodiment of the present invention.

The NAND flash memory test apparatus of the present invention includes a device under test (DUT) 31, which is a NAND flash memory (not shown) to be tested, and a capture logic unit for reading data recorded in the DUT31 ( 32), a pattern generation unit 33 for generating a test pattern recorded in the NAND flash memory, and a test pattern output from the pattern generation unit 33 and data read from the capture logic unit 32 corresponding to bits at positions. The comparison logic unit 34 that outputs the fail address (Fail_addr) and the number of fail bits (Fail_Num) according to whether the two bits to be compared and the same are compared, and the fail address (Fail_addr) input from the comparison logic unit 34. ) And a fail logic unit 35 to determine whether a sector-by-sector failure is performed by using the Fail_Num information, and to process information on the defective block output from the fail logic unit 35. A block processor 36 is provided.

The capture logic unit 32 captures data recorded in the NAND flash memory by 8 bits (1 byte) or 16 bits (2 bytes). The width of the data captured in the capture logic portion 32 is variable. When the capture logic unit 32 captures valid data, the byte counter (not shown) accumulates the number of valid bytes, and enables the last byte signal Last_Byte when the last byte of the page under test is captured.

The comparison logic unit compares the data captured by the capture logic unit 32 with the test pattern generated by the pattern generation unit 33. The comparison logic section 34 determines that the two bits to be compared (the data captured by the capture logic section 32 and the test pattern) are not the same and fail, and the address of the data where the failure occurs (hereinafter, It outputs a fail address (Fail_addr) and the number of bits failed in the fail address (hereinafter, referred to as a fail bit number (Fail_Num)). The comparison logic unit 34 may optionally be provided with a comparison mask. In this case, the comparison logic unit 34 excludes the bit position corresponding to the comparison mask from the captured data.

4A and 4B are diagrams illustrating a fail logic unit 35 according to an exemplary embodiment of the present invention.

The fail logic unit 35 uses a plurality of sector fail determination units 41 and 42 (shown in FIG. 4A) to determine whether a test block fails by sector using a fail address Fail_addr and a fail bit number Fail_Num. And a bad block determination 43 (shown in FIG. 4B) that determines a bad block by using the sector-by-sector failure information of the test blocks of the plurality of sector fail determination units 41 and 42. FIG. When a plurality of pages are accumulated and tested, the sector fail determination unit determines whether to fail a cumulative sector in which corresponding sectors of each page are accumulated.

Each sector fail decision section 41 determines a sector range regulation section 41a, 41b, 41c that determines whether the fail address Fail_addr belongs to an address range of a determination target sector to be determined by the sector fail decision section 41. , 41d, 41e, 41f, 41g, and 41h, and a fail counter 41i that cumulatively calculates the number of fail bits (Fail_Num) if the fail address (Fail_addr) falls within an address range of a determination target sector, and a fail counter 41i. ) And a fail comparator 411j for enabling the fail signal Fail_0 of the determination target sector by comparing the cumulative value of " Err_Limit_N ". Here, the error limit number Err_Limit_N means the allowable number of bits that can be error corrected by the error correction code ECC.

One page is composed of four quarter sectors and four additional bytes as shown in Fig. 2A, and one sector is combined with one additional byte (error correcting code). Here, one combined sector and one additional byte constitute one determination target sector. That is, the range of data to be judged in one determination target sector is divided into two places.

In FIG. 4A, the upper address of the sector constituting the determination target sector is referred to as the sector upper address (Hi_Lim_N_0), and the lower address of the same sector is referred to as the sector lower address (Lo_Lim_N_0), and the upper address of the additional bytes constituting the same determination subject sector is referred to. Additional Higher Address (Hi_Lim_N_1) The lower address of the same additional byte is called an additional lower address (Lo_Lim_N_1).

The sector range regulation compares the sector upper address Hi_Lim_N_0 and the fail address Add_Failer, and if the sector upper address Hi_Lim_N_0 is greater than or equal to the fail address Adder, the first comparator 41a and the sector lower address Lo_Lim_N_0) and the fail address (Fail_addr) are compared if the fail address (Fail_addr) is greater than or equal to the sector sub-address (Lo_Lim_N_0) enable the second comparator 41b and the output value of the first comparator 41a and the second comparator By performing a logical AND operation on the output value of (41b), if the fail address Fail_addr is between the sector lower address Lo_Lim_N_0 and the sector upper address Hi_Lim_N_0, the first logical operator 41c and the additional upper address Hi_Lim_N_1 are enabled. Compare the fail address (Fail_addr) with the third comparator (41d) enabled, and the additional sub address (Lo_Lim_N_1) and the fail address (Fail_addr) if the additional high address Hi_Lim_N_1 is greater than or equal to the fail address (Fail_addr). By If the address Fail_addr is greater than or equal to the additional sub-address Lo_Lim_N_1, the fail address is logically calculated by multiplying the output value of the fourth comparator 41e, the output of the third comparator 41d, and the output value of the fourth comparator 41e. If (Fail_addr) is between the additional lower address (Lo_Lim_N_1) and the additional upper address (Hi_Lim_N_1), the enabled second logical operator 41f, the first logical operator 41c, and the second logical operator 41f are enabled. The output value is ORed and supplied to the enable terminal EN of the fail counter 41i so that one of the first logical operator 41c and the second logical operator 41f outputs the enable signal. The logical sum calculator 41g is provided.

In addition, the sector range regulator further adds a third logical operator 41h that performs an AND operation on the output of the logical operator 41g and the external enable signal Enable to provide the enable terminal EN of the fail counter 41i. It may be provided. A plurality of memory test devices may be allocated to one DUT, and selecting one of the plurality of memory test devices is an external enable signal.

The operation of the sector fail decision unit 41 configured as described above will be described.

The comparison logic unit 34 provides the fail address Fail_addr and the number of fail bits Fail_Num. The fail address Fail_addr includes the first comparator 41a, the second comparator 41b, and the third comparator 41d. It is input to the fourth comparator 41e, and the number of fail bits Fail_Num is input to the fail counter 41i.

The first comparator 41a compares the fail address Fail_addr and the sector upper address Hi_Lim_N_0, and the second comparator 41b compares the fail address Fail_addr and the sector lower address Lo_Lim_N_0, and the first logical product. The calculator 41c performs an AND operation on the output value of the first comparator 41a and the output value of the second comparator 41b. Accordingly, it is possible to know whether the fail address Fail_addr is included in the range of the sector upper address Hi_Lim_N_0 and the sector lower address Lo_Lim_N_0.

In addition, the third comparator 41d compares the fail address Fail_addr and the additional high address Hi_Lim_N_1, and the fourth comparator 41e compares the fail address Fail_addr with the additional sub address Lo_Lim_N_1, and the second comparator 41d. The AND product 41f performs an AND operation on the output value of the third comparator 41d and the output value of the fourth comparator 41e. Accordingly, it is possible to know whether the fail address Fail_addr is included in the range of the additional high address Hi_Lim_N_1 and the additional low address Lo_Lim_N_1.

The logical sum operator 41g performs a logical sum operation on the output value of the first logical operator 41c and the output value of the second logical operator 41f. The fail address Fail_addr includes the sector upper address Hi_Lim_N_0 and the sector lower address Lo_Lim_N_0. If it is included in the range of) or within the range of the additional high address Hi_Lim_N_1 and the additional low address Lo_Lim_N_1, the output signal is enabled. The output signal of the logical sum operator 41g may be directly provided to the enable terminal EN of the fail counter 41i, or may be provided after the logical AND operation with the enable signal 41h in the third logical operator 41h. May be

Therefore, the fail counter 41i may be included when the fail address Fail_addr is included in the range of the sector upper address Hi_Lim_N_0 and the sector lower address Lo_Lim_N_0 or in the range of the additional upper address Hi_Lim_N_1 and the additional lower address Lo_Lim_N_1. Is enabled. When the fail counter 41i is enabled, the fail bit number Fail_Num is accumulated.

The cumulative number of fail bits accumulated in the fail counter 41i is compared with the error limit number Err_Limit_N in the fail comparator 41j. The fail comparator 41j enables and outputs a fail signal Fail_0 when the cumulative fail bit number is greater than or equal to the error number.

The plurality of sector fail determining units 41 and 42 determine whether to fail the determination target sector as described above for each sector, and fail signals of the plurality of sector fail determining units 41 and 42 are shown in FIG. 4B. The bad block determination unit 43 is provided.

In the case of the memory having 2112 bytes as in the embodiment of the present invention, it is possible to simultaneously determine whether or not to fail four sectors consisting of four sectors. On the other hand, a memory composed of 4224 bytes may be divided into eight sectors. In this case, the present invention may be configured by eight sector fail determining units to determine whether or not to fail each sector simultaneously. The number of sector fail judgments can be changed.

When the last byte signal Last_Byte is enabled, the bad block determining unit 43 performs an OR operation on the fail signals Fail_0, Fail_2, ..., Fail_N inputted from the sector fail determining units 41 and 42, respectively. When a single fail signal is enabled, the block fail signal Block_Fail is enabled and the corresponding block is treated as a bad block. This block fail signal Block_Fail is input to the bad block processing unit 36.

5 is a block diagram of a bad block processing unit 36 according to an embodiment of the present invention.

The bad block processing unit includes a bad block counter 51 that accumulates the number of bad blocks, and a bad block memory 52 that stores the location of the bad blocks.

The bad block memory 52 includes as many cells as the blocks constituting the memory cell array, and all cells are initialized to a normal state. The bad block memory 52 is inputted with a block fail signal Block_Fail, a last byte signal Last_Byte, and a block counter Block_Counter. The block fail signal Block_Fail is accumulated in the logic calculator 53 and input to the data input terminal Data In of the bad block memory 52. The block counter Block_Counter represents the address of the block currently being tested.

When the block fail signal Block_Fail is enabled, the bad block memory 52 accumulates in the logical combiner 53. When the last byte signal Last_Byte is enabled, the bad block memory 52 uses the block counter Block_Counter as an index to select a cell of the corresponding address. Set to bad block. The Data Out outputs an enable (high) to enable the logic operator 53 while testing the block. When the last byte signal (Last_Byte) is enabled, the data output (Data Out) is disabled (low) and accumulates the number of bad blocks of the bad block counter 51 through the logical product operator 54 and the logical operator 53 Clear.

The bad block count Bad_Block_Count accumulated in the bad block counter 51 is used for the final bad judgment on the NAND flash memory. That is, by comparing the bad block number Bad_Block_Count and the allowable error block number Block_Err_limit_N, if the bad block number exceeds the allowable error block number, the corresponding NAND flash memory is determined as bad. When the NAND flash memory is determined to be defective during the test on the NAND flash memory, a test stop signal is output to stop the test.

In the current NAND flash memory test technique, even if one sector among sectors constituting a block is determined to be a failure, the block is treated as a bad block. That is, sectors are set in test units. Thus, although the embodiment of the present invention has been described with reference to sectors as test units, the present invention is not limited thereto, and several sectors may be superimposed as one test unit.

On the other hand, RAM is generally considered a pass only when there are no fail bits. However, RAM having ECC in RAM is similar to NAND flash memory in that it is recognized as a pass in the case of one bit failure of one byte. Therefore, the present invention can be applied to the test of a memory including a RAM having an ECC.

The technical spirit of the present invention has been described above with reference to the accompanying drawings, but this is by way of example only for describing the best embodiment of the present invention and not for limiting the present invention. In addition, it is obvious that any person skilled in the art can make various modifications and imitations without departing from the scope of the technical idea of the present invention.

1 is a configuration diagram of a general NAND flash memory;

2A is a conceptual diagram of pages and sectors of a general NAND flash memory;

3 is a block diagram showing a NAND flash memory test apparatus according to an embodiment of the present invention;

4A and 4B are diagrams illustrating a fail logic unit according to an embodiment of the present invention;

5 is a block diagram of a bad block processing unit according to an embodiment of the present invention.

     <Brief description of symbols for the main parts of the drawings>

31: DUT 32: Capture Logic

33: pattern generating section 34: comparative logic section

35: fail logic unit 36: bad block processing unit

Claims (15)

delete A capture logic section for reading data from the memory in which the test pattern is recorded; A comparison logic unit for comparing the data read from the capture logic unit and the test pattern in units of bits of corresponding positions; A fail logic unit for accumulating the number of fail bits for each test unit from the comparison result of the comparison logic unit to determine whether a block including the test units is defective; And a bad block processing unit for accumulating the number of bad blocks determined to be bad in the fail logic unit and storing position information of the bad blocks. The method of claim 2, wherein the logic unit outputs a fail address generated from the fail and the number of fail bits generated from the fail address, The fail logic unit accumulates a number of fail bits for each test unit constituting the block to determine whether to fail the test unit, and a plurality of fail decision units to determine whether to fail the test to configure the block. And a bad block determination unit determining the block as a bad block if at least one of the units is a fail. The method of claim 3, wherein the fail determination unit, A range regulation for determining whether the fail address is an address belonging to the test unit, a fail counter for accumulating the fail bit number if the fail address is an address belonging to the test unit, a cumulative operation value of the fail counter, And a comparator for comparing the error limit number and enabling the fail signal of the test unit when the cumulative operation value exceeds the error limit number. The memory test apparatus of claim 4, wherein the test unit is variable. 6. The memory according to claim 5, wherein the range regulator determines whether the fail address is an address within a range between an upper address and a lower address of a sector or a range between an upper address and a lower address of an additional byte allocated to the sector. Test equipment. The memory test apparatus of claim 2, wherein a comparison mask is input to the comparison logic unit. delete A capture step of reading data from a memory in which a test pattern is recorded; A comparison step of comparing the data read in the capturing step and the test pattern in bit units of mutually corresponding positions; A fail determining step of accumulating the number of fail bits for each test unit from the comparison result of the comparing step to determine whether a block including the test units is defective; And a bad block processing step of accumulating the number of bad blocks determined to be bad in the fail determining step and storing position information of the bad blocks. 10. The memory test method of claim 9, further comprising a final defect determination step of determining whether the memory is defective by using information on the defective block of the memory. The method of claim 9, wherein the comparing step outputs a fail address where a fail is generated and the number of fail bits generated by the fail address. The fail determination step includes a fail determination step for each test unit that determines whether to fail for each test unit by accumulating the number of fail bits for each test unit constituting the block, and a test for configuring a result block of the fail determination step for each test unit. And determining a block as a bad block if at least one of the units is a fail. The memory test method of claim 11, wherein the test unit is variable. The method of claim 11, wherein the fail determination step sequentially performs the fail determination step and the bad block determination step for each test unit for the test units constituting the block, and if the block is determined to be defective, configure the block. The memory test method, characterized in that to terminate the test for the remaining test units. The memory test method of claim 9, wherein a comparison mask is input to the comparison step. The memory test method of claim 9, wherein when the accumulated number of bad blocks exceeds an allowable error block, the memory is treated as bad and the test is terminated.

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