KR100911188B1 - Semiconductor Integrated Circuit - Google Patents

Abstract

The semiconductor integrated circuit of the present invention comprises at least one bank; A row-based control circuit unit disposed at an outer side of the bank; And a precharging portion formed with a power line and disposed outside the bank facing the row control circuit portion to precharge the sense amplifier in the bank.

Precharging circuit, tRP, bank

Description

Semiconductor Integrated Circuits

1 is a circuit diagram of a general semiconductor integrated circuit,

2 is a timing diagram of a pair of bit lines of the semiconductor integrated circuit shown in FIG. 1;

3 is a schematic block diagram of a semiconductor integrated circuit according to the present invention;

4 is a detailed block diagram of the semiconductor integrated circuit shown in FIG. 3;

5 is a detailed circuit diagram of an nth precharging unit illustrated in FIG. 4;

6 is a timing diagram of a pair of bit lines of the semiconductor integrated circuit shown in FIG. 4;

7 and 8 are schematic block diagrams of a semiconductor integrated circuit according to another embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10: sense amplifier array 11, 111: sense amplifier

20,200: precharging unit 30: sub-hole

40: sub wordline driver array

50: sub word line driver

60: cell array 210: equalizing unit

220,230: Provide first and second precharge voltage

300: row control circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to semiconductor integrated circuits including precharging circuits.

1 is a block diagram of a general semiconductor integrated circuit.

The semiconductor integrated circuit shown in FIG. 1 is composed of a sense amplifier driver 50, a sense amplifier 11, and a precharging unit 20.

The sense amplifier driver 50 receives the first and second control signals SAN and SAP2 and the overdriving signal SAP1 and supplies an external supply voltage VDD, a core voltage Vcore, and the sense amplifier 11 to the sense amplifier 11. Supply the ground voltage (VSS).

The first control signal SAN is a control signal for supplying the ground voltage VSS supplied to the NMOS transistors NM1 and NM2 of the sense amplifier 11, and the second control signal SAP2 is A control signal for supplying a core voltage Vcore, which is a power supply voltage supplied to the PMOS transistors PM1 and PM2 of the sense amplifier 11. In addition, the overdriving signal SAP1 is a control signal for supplying a voltage higher than the core voltage Vcore, that is, an external supply voltage VDD, to the sense amplifier 11.

The sense amplifier 11 senses and amplifies data carried on the bit line pairs BL and BLB. The power electrode rto is a terminal to which the power voltage of the sense amplifier 11 is supplied, and the ground electrode sb is a terminal to which the ground voltage VSS of the sense amplifier 11 is supplied. The sense amplifier 11 receives the power supply voltage and the ground voltage VSS from the sense amplifier driver 50 to the power supply electrode rto and the ground electrode sb, so that the bit line pair BL, Amplify the data on the BLB).

The precharge unit 20 precharges the power electrode rto and the ground electrode sb in the precharge mode. Therefore, in the precharging mode, the power line rto and the ground electrode sb become the bit line precharge voltage VBLP level, so that the bit line pairs BL and BLB are bit-wise by the sense amplifier 11. Precharged to the line precharge voltage VBLP level. Accordingly, the precharging unit 20 prepares to amplify the data carried on the bit line pairs BL and BLB at the next active command.

FIG. 2 is a timing diagram of bit line pairs BL and BLB of the semiconductor integrated circuit shown in FIG. 1.

As illustrated, when the active command ACT is input, the inverted signal BISHB of the bit line isolation signal and the inverted signal BLEQB of the bit line equalization signal are enabled. In addition, the inverted signal MWLB of the main wordline signal and the inverted signal FXB of the sub wordline decoded signal are disabled. Accordingly, the equalization and precharging of the bit line is stopped, the word line is opened, and the data stored in the cell is loaded on the bit line BL. Subsequently, the overdriving signal SAP1 is enabled by a pulse at a predetermined interval, and the first and second control signals SAN and SAP2 are sequentially enabled. Accordingly, the external supply voltage VDD, the core voltage Vcore, and the ground voltage VSS are supplied to the sense amplifier 11. As a result, the sense amplifier 11 senses and amplifies data carried on the bit line pairs BL and BLB. Accordingly, the bit line pairs BL and BLB are amplified by a core voltage Vcore or more in a section in which the overdriving pulse is supplied to the sense amplifier 11, and then the second control signal SAP2 is enabled. The voltage levels of the bit line pairs BL and BLB are amplified to a core voltage Vcore level and a ground voltage VSS.

After that, when the precharge command PCG is input, the inverted signal BISHB of the bit line isolation signal and the inverted signal BLEQB of the bit line equalization signal are disabled. In addition, the inversion signal MWLB of the main word line signal and the inversion signal FXB of the sub wordline decoding signal are enabled. In addition, the overdriving signal SAP1 and the first and second control signals SAN and SAP2 are disabled. Accordingly, the word line is closed and the bit line pairs BL and BLB perform an equalizing and precharging operation. Accordingly, the precharging unit 20 performs an operation of precharging the power electrode rto and the ground electrode sb with the bit line precharge voltage VBLP. Therefore, the voltage level of the bit line pairs BL and BLB becomes the bit line precharge voltage VBLP level. After that, when the next active command ACT is executed, the bit line pairs BL and BLB may receive data contained in a cell and perform sensing and amplification operations.

After the active operation, tRP refers to the time taken for the bit line pairs BL and BLB to be precharged to the bit line precharge voltage VBLP level after the precharging command is input to perform the next active command.

As the DRAM evolves, the tRP specification decreases. If the tRP characteristic is bad, precharging may not be performed smoothly after the active command, and the timing of the next active command is delayed. Therefore, a method of reducing the tRP of the DRAM is required.

In order to improve the tRP, the performance of the precharge unit 20 precharging the sense amplifier 11 should be improved. To this end, the current supply must be increased by increasing the area or number of transistors constituting the precharge unit 20.

However, as the degree of integration of semiconductor integrated circuits increases, the area of the precharge unit 20 may inevitably decrease as the process technology develops. This makes the tRP characteristic improvement request more urgent.

Disclosure of Invention The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor integrated circuit that improves tRP and has no reduction in net die and cell efficiency.

The semiconductor integrated circuit of the present invention for achieving the above technical problem is at least one bank; A row system control circuit unit disposed at an outer side of the bank; And a precharging unit formed with a power line and disposed outside the bank facing the row control circuit unit to precharge a sense amplifier in the bank.

In addition, a semiconductor integrated circuit according to another embodiment of the present invention is at least one bank; A row-based control circuit unit disposed at an outer side of the bank; And a precharge section disposed in an edge region of a bank on the side of the row system control circuit section for precharging a sense amplifier in the bank.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a block diagram of a semiconductor integrated circuit according to the present invention.

As illustrated, the semiconductor integrated circuit according to the present invention includes a bank 100, a row-based control circuit unit 300, and a precharging unit 200.

The bank 100 is composed of a plurality of cell mats. More specifically, as shown in FIG. 4, the bank 100 includes a plurality of cell mats 60 arranged in N (N is a natural number) rows and M (M is a natural number) columns, and each cell mat 60. Positioned in the intersection of the sense amplifier array 10 corresponding to the sub-word line driver array 40 corresponding to the cell mat 60 and the sense amplifier array 10 and the sub-word line driver array 40. It consists of the sub-hole 30 to make.

The row control circuit part 300 is disposed at one outer side of the bank 100. The row-based control circuit 300 is generally composed of control circuits related to driving a word line. For example, the row control circuit unit 300 includes a main word line driver, a sub word line decoding signal driver, a bit line equalization signal driver, a bit line isolation signal driver, and the like.

The precharging unit 200 is disposed outside the bank 100 facing the row control circuit unit 300. Here, the outer means an area outside the bank 100. This is because the inside of the bank 100 is composed of a plurality of cell mats. In addition, the precharging unit 200 precharges the power electrode rto for supplying the power voltage of the sense amplifier in the bank 100 and the ground electrode sb for supplying the ground voltage in the precharging mode. The sense amplifier array 10 includes a plurality of the sense amplifiers. The power supply voltage includes the external supply voltage VDD and the core voltage Vcore.

That is, as shown in FIG. 6, when the voltage of the bit line pair is at the core voltage Vcore and the ground voltage VSS level after the active command, and the precharging command is input, the precharging unit 200 performs the precharging. The voltages of the power supply electrode rto and the ground electrode sb of the sense amplifier are precharged, so that the bit line pair is also precharged to the bit line precharge voltage VBLP level. The bit line precharge voltage VBLP is generally one half of the core voltage Vcore, but may be at the core voltage Vcore level.

The present invention secures an area of the precharging unit 200 in order to improve tRP. In this manner, the bank 100 facing the row system control circuit unit 300 as an outer region of the bank 100. The precharging unit 200 is disposed in the outer region of the backplane. In the semiconductor integrated circuit according to the prior art, the area in which the precharging circuit is disposed is limited in area, and thus cannot be arbitrarily enlarged. You have to take According to an embodiment of the present invention, the bank 100 corresponding to the row-based control circuit part 300 which is an outer region of the bank 100 having a considerable area in order to secure an area of the precharging part 200. The precharging unit 200 was added to the other outlying region. Accordingly, tRP may be improved by shortening the precharging time of the bit lines connected to the sense amplifiers in the bank 100.

Since the region in which the precharging unit 200 is disposed is an outer region of the bank 100, there are no other circuits, and the power line or storage capacitors are mainly disposed. Therefore, there is no problem in the characteristics of the power line by depositing the power lines on the vertical upper portion of the precharge unit 200 after forming the precharge unit 200.

In addition, even when the precharging unit 200 is added to the outer region of the bank 100, the power electrode rto and the ground electrode sb are connected to all regions by a sense amplifier array in the bank 100. As a result, regional differences in tRP characteristics are not significant. As shown in FIG. 4, since the power supply electrode rto and the ground electrode sb of the sense amplifier array 10 are wired in the transverse direction in the bank, the pre-amplification is performed along the region of the sense amplifier array 10. It is connected to the charging unit 200.

3 is a schematic block diagram of a semiconductor integrated circuit according to the present invention, which is not equal to the ratio of the actual size of each component. The actual bank outer area has a smaller area compared to the bank area based on the illustration, and FIG. 3 shows a block diagram for convenience of description.

4 is a detailed block diagram of the bank 100 and the precharging unit 200 shown in FIG. 3.

The bank includes a plurality of cell mats 60 (N and M are self-numbered numbers) arranged in a matrix of N rows and M columns, a sense amplifier array 10 corresponding to each cell mat 60, and each cell mat 60 A sub word line driver array 40 and a sub hole 30 positioned at an intersection of the sense amplifier array 10 and the sub word line array 40 are formed.

The precharging unit 200 includes first to Nth precharging units 200-1 to 200 -N corresponding to each of the rows, and the nth precharging unit 200-n is disposed in the nth row. Precharging the power supply electrode rto line to which the power supply voltage of the sense amplifier array 10 of the arranged cell mats is supplied and the ground electrode sb line supplied to the ground voltage VSS. Natural numbers less than or equal to N)

That is, the nth precharging unit 200-n, which is one of the first to Nth precharging units 200-1 to 200 -N, has M cells in a horizontal direction corresponding to n rows of cell mats. The power electrode rto line and the ground electrode sb line connected to the sense amplifier arrays 10 corresponding to the mat are precharged. The precharging unit 200 may be implemented by a general precharging circuit.

That is, each of the nth precharging units 200-n precharges the power electrodes rto and the ground electrodes sb of all sense amplifiers in the transverse direction.

A method of connecting the first to nth precharging units 200-1 to 200-n, the power electrode rto, and the ground electrode sb is a sense amplifier 111-n illustrated in the lower part of FIG. 4. ) And the n-th precharging unit 200-n are shown in the circuit diagram of an embodiment.

A sub precharging unit 31, a bit line equalizing transistor BLEQ Tr, an input / output switch IOSW, and the like are disposed in the sub hole 30.

That is, in the present exemplary embodiment, a sub precharging unit 31 for precharging the power electrode rto and the ground electrode sb is further disposed in the subhole 30 in addition to the precharging unit 200. . As a result, the area and number of the precharging circuit can be further expanded, thereby further improving the tRP characteristics.

The present invention includes the precharge unit 200 and the sub precharge unit 31 to precharge the bit line pairs BL and BLB to the bit line precharge voltage VBLP level. Can be charged. Accordingly, the present invention can improve the tRP characteristics by shortening the time to perform the precharging.

FIG. 5 is a detailed circuit diagram of the nth precharging unit 200-n illustrated in FIG. 4.

As shown in FIG. 5, the n-th precharge unit 200-n includes an equalizing unit 210-n, a first precharge voltage providing unit 220-n, and a second precharge voltage providing unit 230. -n).

As the bit line equalization signal BLEQ is enabled, the n th precharger 200-n may connect the power electrode rto line and the ground electrode sb line to the bit line precharge voltage VBLP. Precharge

The equalizing unit 210-n connects the power supply electrode rto and the ground electrode sb according to the bit line equalization signal BLEQ. The bit line equalization signal BLEQ goes low in active operation and goes high in precharging operation. The equalizing unit 210-n may be implemented by a switching element connecting or disconnecting the power electrode rto and the ground electrode sb according to the bit line equalization signal BLEQ.

The equalizing unit 210-n is configured to receive a bit line equalization signal BLEQ at a gate thereof, and a transistor connected to the power electrode rto and the ground electrode sb at a drain and a source, respectively. Therefore, during the precharging operation, the bit line equalization signal BLEQ becomes high, so that the voltages of the power electrode rto and the ground electrode sb are the same.

The first precharge voltage providing unit 220-n supplies a bit line precharge voltage VBLP to the power electrode rto according to the bit line equalization signal BLEQ. The bit line precharge voltage VBLP is a half level of the core voltage Vcore. The first precharge voltage providing unit 220-n may be implemented by a switching element that supplies or blocks the bit line precharge voltage VBLP to the power electrode rto according to the bit line equalization signal BLEQ. Can be.

The first precharge voltage providing unit 220-n receives the bit line equalization signal BLEQ at a gate thereof, and supplies the bit line equalization signal BLEQ to a drain and a source, respectively, to the power electrode rto and the bit line precharge voltage VBLP. It is composed of a transistor characterized in that the connection. Therefore, during the precharging operation, the bit line equalization signal BLEQ becomes high, so that the bit line precharge voltage VBLP is supplied to the power electrode rto.

The second precharge voltage providing unit 220-n supplies the bit line precharge voltage VBLP to the ground electrode sb according to the bit line equalization signal BLEQ.

The second precharge voltage providing unit 220-n may be implemented by a switching element supplying or blocking the bit line precharge voltage VBLP to the ground electrode sb according to the bit line equalization signal BLEQ. Can be.

The second precharge voltage providing unit 220-n receives the bit line equalization signal BLEQ at a gate thereof, and applies the ground line sb and the bit line precharge voltage VBLP to a drain and a source, respectively. It consists of connected transistors. Therefore, during the precharging operation, the bit line equalization signal BLEQ becomes high, so that the bit line precharge voltage VBLP is supplied to the ground electrode sb.

Thus, during the precharging operation, the equalizing unit 210-n equalizes the voltages of the power electrode rto and the ground electrode sb, and the first precharge voltage providing unit 220-n and the first precharging voltage. The second precharge voltage providing unit 230-n supplies the bit line precharge voltage VBLP to the power electrode rto and the ground electrode sb, respectively. According to an exemplary embodiment of the present invention, the precharge unit 200 may be provided in a region outside the bank 100 in addition to the sub-hole 30 region so that the bit line pairs BL and BLB may be faster than the bit line precharge voltage VBLP. TRP can be improved by reaching

In addition, the present invention is disposed in a marginal area outside the bank 100, so that the size of the transistors constituting the precharging unit 200 is relatively limited, thereby increasing the size of the transistors. The precharging characteristic can be optimized. Accordingly, the present invention can implement the precharging unit 300 of excellent precharging characteristics.

FIG. 6 is a timing diagram of a bit line pair of the semiconductor integrated circuit shown in FIG. 4.

As shown, an active operation performed by inputting an active command ACT has the same characteristics in the prior art and the present invention. That is, the inverted signal BISHB of the bit line isolation signal and the inverted signal BLEQB of the bit line equalization signal are enabled, and the inverted signal MWLB of the main word line signal and the inverted signal FXB of the sub word line decoded signal. Is disabled. Thus, the word line is opened and data stored in the cell is loaded on the bit line BL. Subsequently, the overdriving signal SAP1 is enabled by a pulse at a predetermined interval, and the first and second control signals SAN and SAP2 are sequentially enabled, thereby providing the external supply voltage VDD and the core voltage. Vcore and the ground voltage VSS are supplied to the sense amplifier 111. As a result, the sense amplifier 111 senses and amplifies data carried on the bit line pairs BL and BLB. Accordingly, the bit line pairs BL and BLB are amplified by a core voltage Vcore or more in a section in which the overdriving pulse is supplied to the sense amplifier 111, and then the second control signal SAP2 is enabled. The voltage levels of the bit line pairs BL and BLB are amplified to a core voltage Vcore level and a ground voltage VSS.

The present invention has superior tRP characteristics than the prior art in the precharging mode for the following reason.

The inverted signal BISHB of the bit line isolation signal and the inverted signal BLEQB of the bit line equalization signal are disabled, the inverted signal MWLB of the main word line signal, and the inverted signal FXB of the sub word line decoded signal. Is enabled. In addition, the overdriving signal SAP1 and the first and second control signals SAN and SAP2 are disabled. Accordingly, the word line is closed and the bit line pairs BL and BLB perform an equalizing and precharging operation. Accordingly, the precharging unit 200 performs an operation of precharging the power electrode rto and the ground electrode sb with the bit line precharge voltage VBLP. In this case, the present invention may implement the precharging unit 200 that is optimized by being disposed in an area where the area of the precharging unit 200 is larger than that of the prior art. In particular, the precharging unit may be implemented with a larger transistor than the prior art. Therefore, the time for precharging the precharge unit 200 is shortened. Therefore, the voltage level of the bit line pairs BL and BLB becomes the bit line precharge voltage VBLP level.

That is, the present invention S1 further includes the precharging unit 200 in an outer region of the bank 100, thereby improving precharging speed, and thus, a bit line waveform diagram of the semiconductor integrated circuit according to the related art (S2). It can be seen that the fast precharging operation is performed compared to the &quot;

In addition, according to another exemplary embodiment of the present invention, an arrangement area of the precharging unit 200 is disposed at an edge of the bank 100 on the side of the row control circuit unit 300. In some cases, a space is provided at an outer side of the bank 100 on the side of the row control circuit unit 300. By arranging the precharging unit 200 in this space, the area of the precharging unit 200 can be secured to improve tRP characteristics.

In addition, according to another embodiment of the present invention, as shown in FIG. 8, the arrangement area of the precharging unit 200 is disposed in an outer region of the bank 100 facing the row control circuit unit 300. In addition, the auxiliary precharging unit 400 is disposed at the edge of the bank 100 on the side of the row-based control circuit unit 300. Accordingly, the tRP characteristic improvement may be further improved.

Although the present invention has been described by taking a four bank structure as an example, the present invention can be applied without being limited to the number of banks.

In addition, the present invention has been described as a structure in which the row-based control circuit unit 300 is disposed in the longitudinal direction, when the row-based control circuit unit 300 is disposed in the horizontal direction, the precharging unit 200 is the bank 100. It may be disposed at the top or bottom edge of the).

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof.

Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The semiconductor integrated circuit according to the present invention can perform a fast precharging operation by adding an excellent precharging circuit to a relatively marginal area of the bank while maintaining cell efficiency and net die, thereby improving tRP characteristics. It is effective.

Claims (13)

At least one bank; A row system control circuit unit disposed at an outer side of the bank; And And a precharging portion, wherein a power line is formed and disposed outside the bank facing the row control circuit portion to precharge a sense amplifier in the bank. The method of claim 1, The bank is, A plurality of cell mats arranged in a matrix in N rows and M columns (N and M are natural numbers), The precharging unit, It is composed of the first to Nth precharging unit corresponding to each row, Among them, the nth precharging unit (n is a natural number equal to or greater than 1 and equal to or less than N), And precharging the sense amplifiers connected to the cell mats arranged in the nth row. The method of claim 2, The n th precharging part, And as a bit line equalization signal is enabled, precharging a power electrode supplying a power supply voltage of the sense amplifier and a ground electrode supplying a ground voltage to a bit line precharge voltage. The method of claim 3, wherein N-th precharging unit, An equalizer configured to equalize the power supply electrode and the ground electrode according to the bit line equalization signal; A first precharge voltage providing unit configured to supply the bit line precharge voltage to the power electrode according to the bit line equalization signal; And And a second precharge voltage supply unit configured to supply the bit line precharge voltage to the ground electrode according to the bit line equalization signal. delete The method of claim 1, And the precharging unit is integrated in an area in which a storage capacitor is formed outside the bank. The method of claim 1, A sub precharging unit disposed in a sub hole area in the bank to precharge the sense amplifier; The semiconductor integrated circuit further comprises. The method of claim 1, An auxiliary precharge unit disposed in an area between the row control circuit unit and the bank; The semiconductor integrated circuit further comprises. delete delete delete delete delete

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