KR100910864B1 - A circuit of autoprecharge control and a method of autoprecharge control - Google Patents

Abstract

An auto-precharge control circuit and an auto-precharge control method are provided to reduce current consumption by disabling the auto-precharge clock when the auto-precharge starts and stopping a write recovery counter. A write pulse generating unit(100) comprises a command decoder(102), a write delay unit(104), and a bank decoder(106). The command decoder decodes a plurality of external signals and outputs a write command. The write delay unit delays the write command by an additive latency and a CAS write latency and outputs a write delay signal. A first bank decoder outputs a write pulse corresponding to each bank by combining the write signal and a signal which is generated in decoding the bank address.

Description

Auto precharge control circuit and auto precharge control method {A circuit of autoprecharge control and a method of autoprecharge control}

The present invention relates to a semiconductor memory device, and more particularly, to an auto precharge control circuit and an auto precharge control method for controlling an auto precharge operation to be performed.

In general, the semiconductor memory device is applied with the read or write command RD / WT after the active command ACT is applied and the precharge command PCG is applied after the operation according to the command is performed. That is, the precharge command PCG is separately input to perform the precharge operation.

Meanwhile, as the semiconductor memory device operates at a higher speed, the semiconductor memory device generates an auto precharge command internally to perform an operation according to a read or write command and to control the precharge operation to be automatically performed after a predetermined time. Auto precharge is applied.

When a read or write command with auto precharge is applied from the outside, the semiconductor memory device drives the autocharge control circuit by the address ADD <10> which is applied in an enable state to perform an operation according to the read or write command. After that, an auto precharge signal is generated to automatically perform a precharge operation.

Referring to FIG. 1, an auto precharge control circuit of a semiconductor memory device according to the prior art may include a plurality of signals CSB, which are applied from the outside of the semiconductor memory device. Auto-precharge by the write pulse generator 10 which decodes RASB, CASB, WEB, and outputs the write pulse CASP <0: 7> corresponding to each of the plurality of banks and performing the write operation, and the address ADD <10>. And an auto precharge control unit 20 for delaying the write pulse CASP <0: 7> and outputting the autoprecharge signal APCG <0: 7> according to the result.

The write pulse generator 10 includes an instruction decoder 12, a write delay unit 14, and a bank decoder 16.

The command decoder 12 decodes a plurality of signals CSB, RASB, CASB, and WEB input in synchronization with the internal clock CLK, and outputs a write command WT. Here, the internal clock CLK is a clock signal that is enabled and toggled by the active command ACT and disabled by the precharge command PCG.

The write delay unit 14 delays the write command WT by the additive latency AL and the cascade write latency CWL synchronized with the internal clock CLK to output the write signal WTD. Here, the additive latency AL (Additive Latency) is a delay time until the write signal for controlling the internal operation is activated by a write command applied from the outside, and the cas write latency CWL (CAS Write Latency) is a write command received. After this, it is time to receive the write data.

The bank decoder 16 decodes the bank addresses BA <0: 2> and outputs a write pulse CASP <0: 7> corresponding to each bank so that the selected bank performs a write operation by the write signal WTD. At this time, eight banks are decoded by the bank addresses BA <0: 2>.

The auto precharge control unit 20 includes an auto precharge decoder 22, a burst length counter 24, and a write recovery counter 26.

The auto precharge decoder 22 receives the write pulse CASP <0: 7> when the address ADD <10> is enabled, that is, when the write command WTA (Write with Auto precharge) with auto precharge is applied. And output with auto precharge pulse APCGP <0: 7>.

The burst length counter 24 receives the auto precharge pulse APCGP <0: 7> and outputs the delayed auto precharge pulse APCGPD <0: 7> by delaying the burst length BL (Burst Langth) synchronized with the internal clock CLK. do. Here, the burst length BL is the number of data output by one read or write command.

The write recovery counter 26 receives the delayed auto precharge pulse APCGPD <0: 7> and delays the write recovery time tWR (Write Recovery Time) synchronized with the internal clock CLK to perform an auto precharge operation. Outputs APCG <0: 7>.

Here, the write recovery time tWR is a time required for the amplified data to be stored again in the cell to output valid data when the cell is accessed by the write command. After the write operation is completed, the auto recovery operation is performed. It's time to be guaranteed.

On the other hand, the write recovery counter 26 preferably operates only when a write command WTA with auto precharge is applied. However, the internal clock CLK for operating the write recovery counter 26 is enabled and toggled in synchronization with the rising edge of the external clock ECLK to which the active command ACT is applied, as shown in FIG. 2, and the external to which the precharge command PCG is applied. Disabled in synchronization with the rising edge of clock ECLK.

As a result, since the light recovery counter 26 continues to operate by the internal clock CLK even in a situation irrelevant to the auto precharge operation, current consumption increases.

The present invention provides an auto-precharge control circuit which reduces current consumption by controlling the operation time of the write recovery counter.

The auto precharge control circuit of the present invention includes a write pulse generator for decoding a plurality of signals applied from an outside of the semiconductor memory device in synchronization with an internal clock to respectively output a write pulse corresponding to a plurality of banks and performing a write operation. ; And delaying the write pulse in response to auto precharge, and enabling the internal clock according to the auto precharge state, and outputting the write pulse delayed in the enable state of the internal clock as an auto precharge signal. And an auto precharge control unit.

The write pulse generator may include a command decoder configured to decode the plurality of signals and output the write command synchronized with the internal clock; A write delay unit delaying the write command by an additive latency and a cascade write latency synchronized with the internal clock to output a write signal; And a first bank decoder that combines the write signal with a signal decoded a bank address and outputs the write pulse signal corresponding to each bank and performing a write operation.

The auto precharge control unit may include: an auto precharge decoder configured to output the light pulse as an auto precharge pulse when a control signal applied corresponding to the auto precharge is enabled; A burst length counter configured to delay and output the auto precharge pulse by a burst length synchronized with the internal clock; A write recovery counter controller configured to control an enable state of the internal clock according to the auto precharge state and output an auto precharge clock corresponding to each bank; And a write recovery counter driven by the auto precharge clock to delay the output of the burst length counter for a write recovery time to output the auto precharge signal.

Preferably, the control signal is a field value of the address field A10 applied from the outside when the plurality of signals outputting the write pulse are applied.

The write recovery counter controller may include: a second bank decoder configured to decode a bank address and output a decoded signal corresponding to each bank; A clock enable signal generator that is enabled when the decoded signal, the control signal, and the write command are enabled, and outputs a clock enable signal that is disabled when the auto precharge signal is enabled; And a clock output unit configured to enable the internal clock by the clock enable signal and output the internal clock as the auto precharge clock.

The clock enable signal generator may include a pull-up unit configured to enable the clock enable signal when the decoded signal, the control signal, and the write command are enabled; And a pull-down unit that disables the clock enable signal when the auto precharge signal is enabled.

The pull-up unit may include a first NAND gate NAND-coupled to the control signal and the write command; A first inverter for inverting and outputting the output of the first NAND gate;

A second NAND gate NAND-coupled to an output of the first inverter and the decoded signal; And a PMOS transistor connected between a power supply voltage terminal and a node and controlling the enable of the clock enable signal output to the node by an output of the second NAND gate.

The pull-down part includes an NMOS transistor connected between the node and the ground voltage terminal and controlling the disable of the clock enable signal output to the node by the auto precharge signal.

Another auto precharge control circuit of the present invention controls an enable state of an internal clock according to an auto precharge state, and write recovery outputs an auto precharge clock corresponding to each bank when the internal clock is enabled. Counter control unit; And a write recovery counter driven by the auto precharge clock and outputting the auto precharge signal synchronized with the internal clock for a write recovery time as an auto precharge signal for performing an auto precharge operation.

The recovery counter controller may include: a bank decoder configured to decode a bank address and output a decoded signal corresponding to each bank; A clock enable signal generator configured to enable the decoding signal, a control command applied corresponding to the write command and auto precharge, and output a clock enable signal disabled when the auto precharge signal is enabled ; And a clock output unit configured to output the internal clock as the auto precharge clock when the clock enable signal is enabled.

The clock enable signal generator may include a pull-up unit configured to enable the clock enable signal when the decoded signal, the control signal, and the write command are enabled; And a pull-down unit that disables the clock enable signal when the auto precharge signal is enabled.

According to the present invention, it is determined whether a command applied to a semiconductor memory device is a command involving an auto precharge, and an auto precharge clock is generated according to the result, and a write recovery counter is controlled by the auto precharge clock. By providing an auto precharge control circuit that outputs an auto precharge signal to be performed, current consumption is reduced.

In addition, the present invention has the effect of reducing the current consumption by providing an auto precharge control circuit for disabling the auto precharge clock when the auto precharge operation is started to stop the operation of the write recovery counter.

The present invention relates to an auto precharge control circuit that improves current consumption by operating a recovery counter only for a command involving an auto precharge applied to a semiconductor memory device.

Referring to FIG. 3, an auto precharge control circuit of a semiconductor memory device according to an exemplary embodiment of the present invention may include a plurality of signals CSB, RASB, CASB, and WEB that are applied from the outside of the semiconductor memory device in synchronization with an internal clock CLK. A write pulse generator 100 for decoding and outputting write pulses CASP <0: 7> corresponding to a plurality of banks, respectively, and performing a write operation; and delaying the write pulses CASP <0: 7> in response to auto precharge. Auto-charge signal APCG <0 which controls the enable state of the internal clock CLK according to the auto-precharge state, and performs the auto-precharge operation on the delayed write pulse CASP <0: 7> in the enable state of the internal clock CLK. And an auto-precharge control unit 200 for outputting at &quot; 7 &gt;.

In more detail, the write pulse generator 100 includes an instruction decoder 102, a write delay unit 104, and a bank decoder 106.

The command decoder 102 decodes a plurality of signals CSB, RASB, CASB, and WEB input in synchronization with the internal clock CLK, and outputs a write command WT. Here, the internal clock CLK is a clock signal that is enabled and toggled by the active command ACT and disabled by the precharge command PCG.

The instruction decoder 102 is provided with a chip select bar signal CSB (Chip Select Bar), a cas address strobe bar signal CASB (cas address strob), and a write enable bar signal WEB (Write Enable Bar) at a low level, and a low address strobe. Outputs the write command WT when the bar signal RASB (Row Address Strob Bar) is applied at a high level.

The write delay unit 104 delays the write command WT by the additive latency AL and the cascade write latency CWL synchronized with the internal clock CLK to output the write signal WTD. In this case, the additive latency AL is a delay time until the light signal for controlling the internal operation is activated by a write command applied from the outside, and the caslight latency CWL is a time until the write data is received after receiving the write command. to be.

The bank decoder 106 decodes the bank addresses BA <0: 2> and outputs a write pulse CASP <0: 7> corresponding to each bank so that the selected bank performs a write operation by the write signal WTD. At this time, eight banks are decoded by the bank addresses BA <0: 2>.

The auto precharge control unit 200 includes an auto precharge decoder 202, a burst length counter 204, a light recovery counter control unit 025, and a light recovery counter 206.

The auto precharge decoder 202 automatically outputs the write pulse CASP <0: 7> when the control signal (address ADD <10>) is enabled, that is, when the command WTA (Write with Auto precharge) accompanying the auto precharge is input. Outputs the precharge pulse APCGP <0: 7>.

The burst length counter 204 outputs the delayed auto precharge pulse APCGPD <0: 7> by delaying the auto precharge pulse APCG <0: 7> by the burst length BL synchronized with the internal clock CLK. Here, the burst length BL is the number of data output by one read or write command, and is set by the mode register set MRS (Mode Register Set).

The write recovery counter control unit 205 controls the output by the internal clock CLK based on the control signal ADD <10> and the write command WT, and outputs the auto-precharge clock CLK_AP corresponding to each bank.

The write recovery counter 206 is driven by the auto precharge clock CLK_AP to auto delay the auto precharge pulse APCGPD <0: 7> for the write recovery time tWR (Auto Recovery). Output the signal APCG <0: 7>.

Referring to FIG. 4, the write recovery counter controller 205 includes a bank decoder 402, a clock enable signal generator 404, and a clock output unit 406.

The bank decoder 402 decodes the bank addresses BA <0: 2> and outputs a decoded signal DBA <0: 7> corresponding to each bank.

The clock enable signal generator 404 is enabled when both the control signal ADD <10> and the write command WT and the decoding signal DBA <0: 7> are enabled, and the auto precharge signal APCG <0: 7> is enabled. A clock enable signal CE that is disabled when enabled, that is, when an auto precharge operation is performed, is output.

The clock output unit 406 outputs the internal clock CLK to the auto precharge clock CLK_AP when the clock enable signal CE is enabled.

Specifically, the clock enable signal generator 404 is controlled by the write command WT when the control signal ADD <10> and the decoding signal DBA <0: 7> are enabled to pull up the clock enable signal CE. A pulldown section 404_2, which is controlled by the section 404_1 and the auto precharge signals APCG <0: 7>, disables the clock enable signal CE.

Here, the pull-up unit 404_1 includes an inverter IV1 for inverting the outputs of the NAND gate ND1 and the NAND gate ND1 which NAND-couples the control signal ADD <10> and the write command WT, and the inverter IV1. Is connected between the NAND gate (ND2) and the power supply voltage terminal and the node NODE1 which NAND couples the output and the decoding signal DBA <0: 7> and is controlled by the output of the NAND gate (ND2) and is enabled to the node NODE1. A PMOS transistor P1 for outputting the enable signal CE is included.

The pull-down unit 404_2 is connected between the node NODE1 and the ground voltage terminal and is controlled by the auto-precharge signal APCG <0: 7> to output the clock enable signal CE that is disabled to the node NODE1 (N1 transistor N1). ).

The clock output unit 406 inverts the outputs of the NAND gate ND3 and the NAND gate ND3 which inverts and outputs the internal clock CLK when the clock enable signal CE is enabled, and outputs the inverted signals to the auto-precharge clock CLK_AP. (IV2).

Looking at the auto precharge clock CLK_AP output from the write recovery counter control unit 205 with reference to FIG. 5, the internal clock CLK is toggled during tD1 from the time when the active command ACT is applied to the time when the precharge command PCG is applied. The auto precharge clock CLK_AP is toggled for tD2 from the time when the write command WTA accompanying auto precharge is applied to the time when auto precharge is performed.

When the operation of the write recovery counter 206 is required, the auto precharge clock CLK_AP is auto-free since the write command WTA with auto precharge is applied to satisfy the at least latency AL, the cascade light latency CWL, and the burst length BL. The auto precharge signal APCG can be output at an accurate time even if the write command with charge is generated after WTA is applied.

Referring to FIG. 3 to FIG. 4, the auto precharge control method of the present invention first decodes a plurality of signals RASB, CASB, WEB, and CSB applied from the outside of the semiconductor memory device in synchronization with the internal clock CLK. A write pulse CASP <0: 7> is generated to correspond to the plurality of banks and perform a write operation. In response to the auto precharge, the write pulse CASP <0: 7> is delayed, and the enable state of the internal clock CLK is controlled according to the auto precharge state, and the pre-delayed light pulse is delayed in the enable state of the internal clock CLK. Output to charge signal APCG <0: 7>.

In detail, the generating of the write pulse CASP <0: 7> may include decoding the plurality of signals RASB, CASB, WEB, and CSB to output a write command WT synchronized with the internal clock CLK, and convert the write command WT into an internal clock. It is delayed by the additive latency AL and the cascade write latency CWL synchronized with CLK and output to the write signal WTD. The write signal WTD is combined with the decoded bank address BA <0: 3> to correspond to each bank. Outputs the write pulse CASP <0: 7>.

The outputting of the auto precharge signal may include outputting the write pulse CASP <0: 7> to the auto precharge pulse APCGP <0: 7 when the control signal A <10> applied corresponding to the auto precharge is enabled. >, And outputs the auto precharge pulse APCG <0: 7> by delaying the burst length BL synchronized with the internal clock CLK, and controls the enable state of the internal clock CLK according to the auto precharge state. The auto precharge clock CLK_AP <0: 7> corresponding to the output signal is driven and driven by the auto precharge clock CLK_AP <0: 7> to delay the output of the burst length counter during the write recovery time. Outputs: 7>

Here, the control signal ADD <10> is a field value of the address field A10 applied from the outside when the plurality of signals RASB, CASB, WEB, and CSB outputting the write pulse CASP <0: 7> are applied.

In the outputting of the auto-precharge clock, the bank address BA <0: 2> is decoded to output a decoding signal DBA <0: 7> corresponding to each bank, and the decoding signal DBA <0: 7> is controlled. It is enabled when signal ADD <10> and write command WT are enabled, and outputs clock enable signal CE which is disabled when auto-precharge signal APCG <0: 7> is enabled, and is internal by clock enable signal CE. Enable clock CLK and output to auto precharge clock CLK_AP <0: 7>.

The outputting of the clock enable signal CE may include enabling the clock enable signal CE when the decoding signal DBA <0: 7>, the control signal ADD <10>, and the write command WT are enabled, and auto precharging. Disable clock enable signal CE when signal APCG <0: 7> is enabled.

As described above, the auto precharge control circuit of the semiconductor memory device of the present invention can reduce the current consumption by operating the write recovery counter only when a write command involving auto precharge is applied.

In addition, when the auto precharge operation is performed, current consumption may be further reduced by stopping the operation of the light recovery counter.

1 is a block diagram of an auto precharge control circuit of a semiconductor memory device according to the prior art;

FIG. 2 is a waveform diagram of an internal clock for controlling the auto precharge control circuit of FIG. 1. FIG.

3 is a block diagram of an auto precharge control circuit of a semiconductor memory device according to an embodiment of the present invention;

4 is a detailed circuit diagram of the light recovery counter control unit of FIG. 3.

FIG. 5 is a waveform diagram of an auto precharge clock for controlling the light recovery counter of FIG. 3. FIG.

Claims (11)

A write pulse generator for decoding a plurality of signals applied from an outside of the semiconductor memory device in synchronization with an internal clock and outputting write pulses corresponding to the plurality of banks and performing a write operation; And The write pulse is delayed in response to the auto precharge, and the enable state of the internal clock is controlled according to the auto precharge state, and the light pulse delayed in the enable state of the internal clock is output as an auto precharge signal. An auto precharge control unit; Auto precharge control circuit comprising a. The method of claim 1, The light pulse generator, A command decoder for decoding the plurality of signals and outputting the write command synchronized with the internal clock; A write delay unit delaying the write command by an additive latency and a cascade write latency synchronized with the internal clock to output a write signal; And A first bank decoder that combines the write signal with a signal decoded a bank address and outputs the write pulse signal corresponding to each bank and performing a write operation; Auto precharge control circuit comprising a. The method of claim 2, The auto precharge control unit, An auto precharge decoder configured to output the write pulse as an auto precharge pulse when a control signal applied corresponding to the auto precharge is enabled; A burst length counter configured to delay and output the auto precharge pulse by a burst length synchronized with the internal clock; A write recovery counter controller configured to control an enable state of the internal clock according to the auto precharge state and output an auto precharge clock corresponding to each bank; And A light recovery counter driven by the auto precharge clock to delay the output of the burst length counter for a write recovery time and output the auto precharge signal; Auto precharge control circuit comprising a. The method of claim 3, wherein And the control signal is a field value of the address field A10 applied from the outside when the plurality of signals outputting the write pulse are applied. The method of claim 3, wherein The light recovery counter control unit, A second bank decoder for decoding a bank address and outputting a decoded signal corresponding to each bank; A clock enable signal generator that is enabled when the decoded signal, the control signal, and the write command are enabled, and outputs a clock enable signal that is disabled when the auto precharge signal is enabled; And A clock output unit which enables the internal clock to be output to the auto precharge clock by the clock enable signal; Auto precharge control circuit comprising a. The method of claim 5, wherein The clock enable signal generator, A pull-up unit which enables the clock enable signal when the decoded signal, the control signal, and the write command are enabled; And A pull-down unit which disables the clock enable signal when the auto precharge signal is enabled; Auto precharge control circuit comprising a. The method of claim 6, The pull-up unit, A first NAND gate NAND-coupled to the control signal and the write command; A first inverter for inverting and outputting the output of the first NAND gate; A second NAND gate NAND-coupled to an output of the first inverter and the decoded signal; And A PMOS transistor coupled between a power supply voltage terminal and a node and controlling an enable of the clock enable signal output to the node by an output of the second NAND gate; Auto precharge control circuit comprising a. The method of claim 6, And the pull-down part connected between the node and a ground voltage terminal and including an NMOS transistor configured to control the disable of the clock enable signal output to the node by the auto precharge signal. A write recovery counter control unit controlling an enable state of an internal clock according to an auto precharge state, and outputting an auto precharge clock corresponding to each bank when the internal clock is enabled; And A write recovery counter which is driven by the auto precharge clock and outputs an auto precharge signal synchronized with the internal clock for a write recovery time and outputs an auto precharge signal for performing an auto precharge operation; Auto precharge control circuit comprising a. The method of claim 9, The recovery counter control unit, A bank decoder for decoding a bank address and outputting a decoded signal corresponding to each bank; A clock enable signal generator configured to enable the decoding signal, a control command applied corresponding to the write command and auto precharge, and output a clock enable signal disabled when the auto precharge signal is enabled ; And A clock output unit configured to output the internal clock as the auto precharge clock when the clock enable signal is enabled; Auto precharge control circuit comprising a. The method of claim 10, The clock enable signal generator, A pull-up unit which enables the clock enable signal when the decoded signal, the control signal, and the write command are enabled; And A pull-down unit which disables the clock enable signal when the auto precharge signal is enabled; Auto precharge control circuit comprising a.

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