KR100905053B1 - Methode for fabricating of an array substrate for LCD with signal line be made from Cu - Google Patents

Abstract

The present invention relates to a liquid crystal display device using copper wiring as signal wiring.

In detail, the liquid crystal display device according to the present invention has a liquid crystal display device including a double layer signal line further comprising a copper layer as an upper layer and a buffer layer further blocking a contact between the copper wire and a lower component layer. (Array substrate for liquid crystal display device).

In particular, the signal wiring of the double layer according to the present invention can significantly reduce the width of the signal wiring compared to the conventional due to the low specific resistance (intrinsic resistance) of the copper wiring.

Therefore, the feature of the present invention is that it is possible to manufacture a large area liquid crystal display device by using a low-resistance copper wiring, and can significantly reduce the line width of the signal wiring as described above has the advantage of improving the aperture ratio .

Description

Method for fabricating an array substrate for LCD with signal line be made from Cu}             

1 is an exploded perspective view schematically illustrating a general liquid crystal display device;

2A to 2C are photographs showing image quality characteristics of a liquid crystal panel due to signal delay;

3 is a plan view schematically showing a part of an array substrate for a liquid crystal display device;

4A to 4G are cross-sectional views taken along the line IV-IV ′ of FIG. 3 and shown in the process sequence of the present invention.

<Explanation of symbols for main parts of drawing>

100: substrate 106: gate wiring

108: gate electrode 112: active layer

114: ohmic contact layer 120: data wiring

122: source electrode 124: drain electrode

126: protective film 130: pixel electrode

The present invention relates to an array substrate for a liquid crystal display device including a copper wiring and a manufacturing method thereof.

In particular, the present invention relates to a method of manufacturing an array substrate for a liquid crystal display device including a copper layer formed under a buffer layer and having a minimum line width.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, the active matrix liquid crystal display (AM-LCD) in which the above-described thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has attracted the most attention due to its excellent resolution and ability to implement video.

1 is an exploded perspective view schematically illustrating a configuration of a general liquid crystal display device.

As shown in the drawing, a general color liquid crystal display 11 includes a black matrix 6 formed between a sub color filter 8 and each of the color filters 8 and a common electrode deposited on the color filter and the black matrix. And an upper substrate 5 having an 18 formed thereon, a pixel region P and a lower substrate 22 having an array wiring and a switching electrode T formed thereon. The liquid crystal 14 is filled between the substrate 5 and the lower substrate 22.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 crosses the plurality of thin film transistors TFT. ) And data wirings 15 are formed.

In this case, the pixel area P is an area defined by the gate wiring 13 and the data wiring 15 intersecting. A transparent pixel electrode 17 is formed on the pixel area P as described above. .

The pixel electrode 17 and the common electrode 18 use a transparent conductive metal having relatively high light transmittance, such as indium-tin-oxide (ITO).

In the above-described configuration, the data line 15 and the gate line 13 are the most important factors influencing the signal delay or the aperture ratio.

In particular, the signal delay of the gate wiring 13 is a fatal defect in the display device.

In order to solve this problem, aluminum (Al) having a very low specific resistance is generally used as a material for forming the gate wiring 13. However, pure aluminum (Al) is significantly different from the thermal expansion coefficient of the glass substrate. To solve this problem, when the insulating film is formed on the upper part of the aluminum wiring, the process is performed at a low temperature (about 300 ° C.), but the aluminum still expands more than the glass substrate.

Therefore, as a result of this, heel lock occurs on the surface of aluminum, which affects the upper dielectric layer (ie, the insulating layer). As a result, a defect occurs in which the gate electrode formed of aluminum (Al) and the upper source electrode or the drain electrode contact each other, and a short may occur at a portion where the gate wiring and the data wiring cross each other.

In addition, due to the hillock of the aluminum electrode (or wiring), an undesirable electric field may be generated in part to make the luminance of the liquid crystal uneven.

In order to solve this problem, wires are formed of an aluminum alloy alloyed with a metal such as aluminum (Al) and molybdenum (Mo), but the resistance is very high compared to pure aluminum (Al), and still a large area liquid crystal display device. There is a problem with this.

As described above, the degree of image quality irregularity due to the signal delay of the gate wiring is well illustrated in FIGS. 2A to 2C.

2A and 2B are diagrams illustrating an image quality of a liquid crystal panel when a gate wiring is formed using a conventional conductive metal material (which is a different metal), and FIG. 2C is a diagram illustrating a liquid crystal panel when no signal is applied. It is a figure which shows the image quality state.

As shown in FIG. 2C, when the signal is not applied, the black state is completely black. However, as shown in FIGS. 2A and 2B, a gate wiring (not shown) is formed using the aluminum alloy (AlNd) described above. In this case, as shown in the figure, a signal delay occurs toward the end of the gate wiring (not shown) by the resistance of each metal wiring, and it is seen that staining occurs on the corresponding pixel (ie, the upper end of the screen).

As a metal for solving such a problem, silver (Ag) is mentioned typically.

However, Ag is not easy to pattern. To solve this problem, silver alloy (AgPdCu) can be used, such as aluminum (Al), but its resistance to acid is weak.

Therefore, silver (Ag) or silver alloy (AgPdCu) is not a strong candidate for electrode metal of TFT-LCD.

Table 1 below compares the physical properties of some metals represented by metals with low resistance.

Table 1 shows the physical properties of the aforementioned aluminum alloys (AlNd), pure aluminum (Al), chromium (Cr), indium oxide (In ₂ O ₃ ), copper (Cu), copper alloy (AgPdCu), silver (Ag) (Intrinsic resistance, melting temperature, ITO contactivity, convenient processability) through experiments, as shown in Table 1, when listed as a low to high resistivity materials, chromium (25.2 * 10 ^-6 Ωcm), Aluminum alloy (5.1 * 10 ^-6 Ωcm), Aluminum (3.3 * 10 ^-6 Ωcm), Silver alloy (2.3 ~ 4.9 * 10 ^-6 Ωcm), Copper (Cu * 10 ^-6 Ωcm ) And silver (1.91 * 10 ^-6 Ωcm).

Therefore, in terms of the resistivity, silver (Ag) having the lowest resistance appears to be the most bonded for use as signal wiring.

However, silver (Ag) has been described above, but has a disadvantage in that it is not easy to process because it is not easy to pattern, and silver alloy also has low resistivity but weak resistance to acid.

At the same time, the aluminum alloy (AlNd) and aluminum (Al) or the process of patterning it is very complicated, and copper has a very weak property against acidity.

On the other hand, the process is convenient compared to chromium (Cr) or indium oxide (In ₂ O ₃ ) and other metals, but has a disadvantage of high resistance as described above.

Comparing the melting point, chromium (Cr) and copper (Cu) are higher at 1830 ° C and 1083 ° C than other metals, respectively.

In view of the above and results, copper (Cu) and silver (Ag) are suitable materials for forming low resistance signal wiring among the plurality of metal materials. In particular, copper (Cu) has a patterning process compared to silver (Ag). Because of their ease, only a few problems can be solved, making them suitable for large area panels.

That is, copper has a property of diffusing to the silicon layer, and for this purpose, it is necessary to further form a buffer layer under the copper wiring, and the patterned side of the copper wiring and the buffer layer should not be reverse tapered. In other words, batch etching should be possible if possible.

Therefore, there are many limitations in using copper as signal wiring.

The present invention has been proposed for the purpose of solving the above-mentioned problems, firstly, molybdenum (Mo) or titanium at the bottom of the copper wiring as a conductive buffer layer (copper layer) at the bottom of the copper wiring and the copper electrode to prevent the diffusion of copper (Ti) layer is further formed.

This configuration makes it possible to use copper as a signal wiring, which makes it possible to manufacture a large-area liquid crystal panel, and at the same time, in the case of a liquid crystal panel having a general size, when the signal wiring is formed using the copper, the resistance of the wiring As it is lowered, it is possible to reduce the area of the signal wiring, which has the advantage of improving the aperture ratio.

In the method for manufacturing an array substrate for a liquid crystal display device according to the present invention for achieving the above-mentioned neck, by depositing molybdenum (Mo), a conductive metal having excellent adhesion to the substrate on the substrate to form a first buffer layer, continuous Depositing copper over the first buffer layer to form a first metal layer; Batch etching the first buffer layer and the first metal layer to form a double layer structured gate line and a double layered gate electrode connected thereto in a direction on the substrate; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring and the gate electrode of the double layer structure are formed; Stacking an active layer and an ohmic contact layer on the gate insulating layer on the gate electrode; Depositing molybdenum (Mo), which is a conductive metal, on the entire surface of the substrate on which the ohmic contact layer is formed to form a second buffer layer, and subsequently depositing copper on the second buffer layer to form a second metal layer; A double layer data line which collectively etchs the second buffer layer and the second metal layer to cross the gate line to define a pixel region, and a double layer structure extending from the data line to an upper side of the gate electrode; Forming a source electrode and a drain electrode spaced apart from the source electrode; Forming a protective film exposing the drain electrode on an entire surface of the substrate on which the data line and the source and drain electrodes are formed; And forming a transparent pixel electrode in contact with the drain electrode and positioned in the pixel region.

The solution for collectively etching the first metal layer, the first buffer layer, and the second metal layer and the second buffer layer is a solution containing hydrogen peroxide (H ₂ O ₂ ) and acetic acid (CH ₃ COOH).

delete

The width W2 of the gate and data lines may be designed in a relationship of W2 = W1 * (ρ ₁ / ρ ₂ ) compared with the width W1 of the gate and data lines formed of aluminum. Where ρ ₂ : resistivity of copper and ρ ₁ : resistivity of aluminum

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Examples

The present invention is characterized by forming a signal wiring in a double layer including a separate metal layer as a buffer layer (buffer layer) under the copper wiring, and patterning the width of the signal wiring to a minimum area.

3 is an enlarged plan view showing an enlarged portion of an array substrate for a liquid crystal display device. (The arrangement of the array substrate can be variously modified. In the present invention, a general structure will be described as an example.)

As shown in the drawing, the gate wiring 106 extending in one direction on the substrate 100 and the data wiring 120 defining the pixel region P by crossing the gate wiring 106 perpendicularly are formed.

The thin film transistor P including the gate electrode 108, the active layer 114, the source electrode 122, and the drain electrode 124 is formed at the intersection of the gate wiring 106 and the data wiring 120. .

The pixel region P forms a transparent pixel electrode 130 in contact with the drain electrode 124.

In the above-described configuration, the gate wiring 106 including the gate electrode 108, the source and drain electrodes 122 and 124, and the data wiring 120 are made of molybdenum (Mo) or titanium (Ti) as a buffer layer. Is formed and the signal wiring is formed by using copper on the top.

In this case, the first buffer layer (not shown) constituting the gate wiring 106 and the gate electrode 108 has a poor contact characteristic with the lower surface of the glass substrate 100 because the gate wiring 106, which is the copper wiring, is poor. It complements.                     

The second buffer layer (not shown) constituting the data line 120 and the source and drain electrodes 122 and 124 may have an insulating layer (not shown) below a copper layer of the data line 120 and the source and drain electrodes 122 and 124. And direct contact with the active layer 114 formed of silicon.

Since copper (Cu) has a property of diffusing to a constituent layer containing a silicon component as described above, the second buffer layer is particularly configured to prevent this.

In the above-described configuration, since the gate wiring 106 and the data wiring 120 are formed of copper (Cu) whose resistivity is lower than that of aluminum (Al), the gate wiring 106 and the data wiring 120 are formed of aluminum (Al). In comparison, the width can be significantly reduced, and thus the aperture ratio can be improved, and the characteristics of the liquid crystal panel can be improved.

A description with reference to Table 2 is as follows.

TABLE 2

Table 2 compares the composition of the thin film transistor array unit made of ordinary metal (aluminum) and copper, and the liquid crystal panel including the same.

As shown in Table 2, for the liquid crystal panel of the same size (15.0 "UXGA), the first panel constituted the thin film transistor array portion of aluminum (Al), and the second panel constituted the thin film transistor array portion of copper (Cu). .

At this time, it can be seen that the width of the gate wiring formed of aluminum (Al) is 30 μm, whereas the width of the gate wiring formed of copper (Cu) is 19 μm.

In addition, the data wiring (or source and drain wiring) also has a line width of 9 µm when designed with aluminum, but the width is significantly reduced to 5 µm when copper is formed in half.

That is, assuming that the resistances of the wirings formed in one direction of the liquid crystal panel are the same, the ratio of the wirings formed of copper having a lower specific resistance than aluminum can be reduced in proportion to the wirings formed of the aluminum below. Can be inferred from the equation.

In general, the resistance (R) of the metal is; R = (ρL / wt) ---- (1),

(L: length, W: width t: height, ρ: electrical conductivity)

When the aluminum wiring resistance R _1, R ₂ la resistance of the copper wiring, R ₁ = R ₂ la Assuming,

(ρ ₁ L ₁ / W ₁ t ₁ ) = (ρ ₂ L ₂ / W ₂ t ₂ ) ---- (2)

W ₂ = (ρ ₂ L ₂ W ₁ t ₁ / ρ ₁ L ₁ t ₂ )

In this case, since the lengths L ₁ and L ₂ of the signal wirings configured in the first and second liquid crystal panels in Equation (2) are the same, and the heights t ₁ and t ₂ are the same, Equation (3) can be obtained. .

W ₂ = W ₁ (ρ ₂ / ρ ₁ ) ---- (3)

At this time, the resistivity ρ ₂ of copper is 2.1 * 10 ⁻⁶ Ωcm and the resistivity ρ ₁ of aluminum is 3.3 * 10 ^−6, so (ρ ₁ / ρ ₂ ) ≒ 0.64.

In conclusion, the width W2 of the copper wiring can be designed to be as small as 0.64 times compared to the conventional aluminum wiring width W ₁ .

That is, as shown in Table 2, when the gate wiring is formed of copper (Cu) when the width of the gate wiring formed of aluminum is 30 μm, the width of the gate wiring formed of the aluminum (Al) is 0.64. It can be designed with a width of about 19㎛ multiplied by.

Preferably, when the gate wiring and the data wiring are formed of copper (Cu), the line width of the gate wiring is 15 to 23 mu m, and the line width of the data wiring is designed to be 5 to 7 mu m.

Therefore, when copper (Cu) is formed as signal wiring or signal electrode, the width of signal wiring and signal electrode can be designed to be considerably small under the assumption that a liquid crystal panel having the same size is manufactured as in the prior art, so that the aperture ratio can be improved as much as possible. There are advantages to it.

In addition, referring to Table 2, the liquid crystal panel in which the thin film transistor array wiring is formed of copper (Cu) has improved brightness, flicker, line resistance, etc., compared to the liquid crystal panel in which the thin film transistor array wiring is formed of aluminum. It can be seen that the state.                     

Hereinafter, a manufacturing process of an array substrate for a liquid crystal display device according to the present invention will be described with reference to FIGS. 4A to 4G.

As shown in FIG. 4A, the first buffer layer 102 is formed by depositing molybdenum (Mo) or titanium (Ti) on the transparent insulating substrate 100.

Next, copper (Cu) is deposited on the entire surface of the substrate 100 on which the first buffer layer 102 is formed to form the first metal layer 104.

In this case, the first buffer layer 102 serves to compensate for the poor contact characteristics between the first metal layer, which is the copper layer, and the substrate 100.

As shown in FIG. 4B, the first buffer layer 102 and the first metal layer 104 (in FIG. 4A) are collectively etched using a predetermined etching solution to form a double layer extending in one direction on the surface of the substrate 100. The gate wiring 106 and the gate electrode 108 extending from the gate wiring 106 are formed.

In this case, when the first buffer layer 102 (FIG. 4A) is molybdenum (Mo), an etching solution including a mixed solution of hydrogen peroxide (H ₂ O ₂ ) and acetic acid (CH ₃ COOH) may be used as an etching solution. That is, the main etching solution may be hydrogen peroxide (H ₂ O ₂ ) and acetic acid (CH ₃ COOH) and the additive may be selected from materials capable of lowering the potential difference between the Cu metal and the Mo metal.

On the other hand, when the first buffer layer (102 in FIG. 4A) is titanium (Ti), oxon (2KHSO ₅ · KHSO ₄ · K ₂ SO ₄ ), hydrofluoric acid (HF), and ammonium fluoride (NH ₄ F) are mixed. Mixed liquors may be used.

At this time, when removing the photoresist used in the photolithography process of patterning the gate wiring 106 and the gate electrode 108, the photoresist removal liquid does not affect the surface of the copper (Cu). It is important not to use this solution, which can be used as a mixture of amide materials and organic amines with a corrosion inhibitor.

As shown in FIG. 4C, an inorganic insulating material including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate 100 on which the gate wiring 106 and the gate electrode 108 of the double layer are formed. The gate insulating layer 110 is formed by depositing one selected from the group.

Subsequently, pure amorphous silicon (a-Si: H) and amorphous silicon (n + or p + a-Si: H) containing impurities are deposited and patterned on the gate insulating layer 110 to form the gate electrode ( The active layer 112 and the ohmic contact layer 114 are formed on the gate insulating layer 110 on the upper portion 108.

Next, as shown in FIG. 4D, the second buffer layer 116 is formed by depositing molybdenum (Mo) or titanium (Ti) on the entire surface of the substrate 100 on which the active layer 112 and the ohmic contact layer 114 are formed. ), And the substrate 100 on which the second buffer layer 116 is formed deposits copper (Cu) on the entire surface to form the second metal layer 118.

In this case, the second buffer layer 116 serves to prevent the copper (Cu) constituting the second metal layer 118 from diffusing into the ohmic contact layer 114.

Next, the second buffer layer 116 and the second metal layer 118 are etched, and as shown in FIG. 4E, a double layer that crosses the gate wiring 106 perpendicularly to define the pixel region P is formed. The data line 120 is formed.

At the same time, the source electrode 122 extending above one side of the gate electrode 108 in the data line 120 and the drain electrode 124 spaced apart from the predetermined distance are formed.

Subsequently, the ohmic contact layer 114 exposed between the source and drain electrodes 122 and 124 spaced apart is removed to expose the lower active layer 112.

The exposed portion of the active layer 112 is particularly referred to as channel CH.

Next, as shown in FIG. 4F, benzocyclobutene (BCB) and acrylic resin (resin) are formed on the entire surface of the substrate 100 on which the data line 120 and the source and drain electrodes 122 and 124 are formed. A passivation layer 126 is formed by depositing one selected from the group of transparent organic insulating materials including or one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ). do.

Next, the passivation layer 126 is patterned to form a drain contact hole 128 exposing a part of the drain electrode 124.

to the next, As shown in FIG. 4G, one selected from the group of transparent conductive metal materials including indium tin oxide (ITO) and indium zinc oxide (IZO) on the entire surface of the substrate 100 on which the passivation layer 126 is formed. Is deposited and patterned to form the pixel electrode 130 positioned in the pixel region P while contacting the exposed drain electrode 124.

Through the above process, an array substrate for a liquid crystal display device including a copper wiring according to the present invention can be manufactured.

In the above-described configuration, since the gate wiring 106 and the data wiring 120 are formed of copper (Cu), the width of the gate wiring 106 and the data wiring 120 is equal to that of the liquid crystal panel having the same size as that of the conventional aluminum wiring. There is a feature that can significantly reduce.

As described above, when the signal wiring is formed of copper having low resistance, first, since the signal delay due to the signal wiring does not occur even if the area of the display element is large, there is an effect that the liquid crystal display device can be large.

Second, when the signal wiring is used as copper, since the resistivity of copper is very low, the width of the signal wiring can be significantly reduced, thereby improving the aperture ratio.

Claims (20)

Depositing molybdenum (Mo), which is a conductive metal having excellent adhesion to the substrate, to form a first buffer layer, and subsequently depositing copper over the first buffer layer to form a first metal layer; Batch etching the first buffer layer and the first metal layer to form a double layer structured gate line and a double layered gate electrode connected thereto in a direction on the substrate; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring and the gate electrode of the double layer structure are formed; Stacking an active layer and an ohmic contact layer on the gate insulating layer on the gate electrode; Depositing molybdenum (Mo), which is a conductive metal, on the entire surface of the substrate on which the ohmic contact layer is formed to form a second buffer layer, and subsequently depositing copper on the second buffer layer to form a second metal layer; A double layer data line which collectively etchs the second buffer layer and the second metal layer to cross the gate line to define a pixel region, and a double layer structure extending from the data line to an upper side of the gate electrode; Forming a source electrode and a drain electrode spaced apart from the source electrode; Forming a protective film exposing the drain electrode on an entire surface of the substrate on which the data line and the source and drain electrodes are formed; Forming a transparent pixel electrode in contact with the drain electrode and positioned in the pixel region; Array substrate manufacturing method for a liquid crystal display comprising a. delete The method of claim 1, The first metal layer and the first buffer layer, the second metal layer and the second buffer layer is a solution containing a solution containing hydrogen peroxide (H ₂ O ₂ ) and acetic acid (CH ₃ COOH) the method of manufacturing an array substrate for a liquid crystal display device. . delete delete The method of claim 1, The width W2 of the gate and data lines is compared with the width W1 of the gate and data lines formed of aluminum, and the array substrate for the liquid crystal display device is designed in a relationship of W2 = W1 * (ρ ₁ / ρ ₂ ). Manufacturing method. (ρ ₂ : resistivity of copper, ρ ₁ : resistivity of aluminum, if the length and height of wires made of aluminum and copper are the same.) The method of claim 1, A line width of the gate wiring ranges from 15 µm to 23 µm. The method of claim 7, wherein And a line width of the gate wiring is 19 mu m. The method of claim 1, A line width of the data wiring ranges from 5 µm to 7 µm. The method of claim 9, And a line width of the data line is 5 mu m. A gate wiring having a double layer structure extending in one direction on the substrate and laminated in the order of a first buffer layer made of molybdenum (Mo) and a copper (Cu) layer, and a gate electrode having a double layer structure extending from the gate wiring; An active layer and an ohmic contact layer having a first insulating film interposed therebetween on the gate electrode; A data layer having a double layer structure in which a pixel region is defined to vertically intersect the gate wiring with a first insulating film interposed therebetween, and is formed by stacking a second buffer layer made of molybdenum (Mo) and a copper (Cu) layer; A double layer source electrode extending from the data line to the ohmic contact layer and a drain electrode having a double layer structure spaced apart from the source electrode; And a transparent pixel electrode formed in the pixel region in contact with the drain electrode. delete delete delete delete The method of claim 11, The width W2 of the gate and data lines is compared with the width W1 of the gate and data lines formed of aluminum, and the array substrate for the liquid crystal display device is designed in a relationship of W2 = W1 * (ρ ₁ / ρ ₂ ). . (ρ ₂ : resistivity of copper, ρ ₁ : resistivity of aluminum, if the length and height of wires made of aluminum and copper are the same.) The method of claim 11, An array substrate for liquid crystal display devices, wherein the line width of the gate wiring ranges from 15 µm to 23 µm. The method of claim 17, And a line width of the gate wiring is 19 mu m. The method of claim 11, An array substrate for a liquid crystal display device, wherein the line width of the data wiring ranges from 5 µm to 7 µm. The method of claim 19, And a line width of the data line is 5 mu m.

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