KR100896462B1 - Semiconductor memory device having write device - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a semiconductor memory device capable of stably storing data. The present invention provides a pull-up / pull-down driving means for driving pull-up / pull-down of a second data line according to data loaded on a first data line. And an overdriving means for overdriving to an external voltage higher than a pullup voltage of the pull-up / pull-down driving means at the beginning of the pull-up period of the second data line, and overdriving for a regulated period in response to a test signal. Provided is an element.

Write Driver, Overdriving, Local Data Lines, Binning, Test

Description

Semiconductor memory device including write driving device {SEMICONDUCTOR MEMORY DEVICE HAVING WRITE DEVICE}

1 is a block diagram of a semiconductor memory device according to the prior art.

FIG. 2 is an internal circuit diagram of the write driver of FIG. 1.

3 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

FIG. 4 is an internal circuit diagram of the overdriving unit and the write driving unit shown in FIG. 3. FIG.

FIG. 5 is a diagram illustrating pull-up overdriving pulses DRVP10 and DRVP20 by the first and second pulse generators shown in FIG. 4; FIG.

FIG. 6 is a diagram illustrating a level variation during write driving of a positive local data line according to the present invention and the prior art. FIG.

* Explanation of symbols for the main parts of the drawings
600: overdriving unit
800: test signal generator
620: First pulse generator
640: second pulse generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a light driver of a semiconductor memory device and a driving method thereof, and more particularly, to an over driving operation of a light driver.

Among semiconductor memory devices, a plurality of memory banks are designed in a semiconductor memory device including DDR SDRAM (Double Data Rate Synchronous DRAM), and each memory bank is a collection of a plurality of memory cells composed of cell transistors and cell capacitors. It is generally composed of. The region in which the memory bank is located is called a core region, and the region configured for inputting / outputting data into the memory bank is called a ferry region. Data transferred from the ferry area during write operation is input into the core area through a write driver located at the core area boundary, and data to be output during read operation is located at the core area boundary. Output to the ferry area through input and output sense amplifiers. In general, a data line connected to a data input / output pin, a light driver, and an input / output sense amplifier is called a global input / output line (GIO), and a data line connected to the light driver, the input / output sense amplifier, and the inside of the core region is local. This is called an input / output line (LIO).

1 is a block diagram of a semiconductor memory device according to the prior art.

Referring to FIG. 1, a semiconductor memory device according to the related art receives a reference voltage generator 10 for generating a reference voltage VREF and a core voltage corresponding to a reference voltage VREF by receiving an external voltage VDD. The core voltage generation unit 20 for generating VCORE, the driving control unit 30 for generating the reset signal RST, the first and second driving signals PD1 and PD2, and the reset signal RST. Write to precharge the positive / negative local data lines (LIO, LIOB) in response to, or drive the positive / negative local data lines (LIO, LIOB) in response to the first and second driving signals (PD1, PD2). The driving unit 40 and a core block 50 for storing data carried in the positive / negative local data lines LIO and LIOB in the corresponding memory cell are provided.

Referring to the operation briefly, the reference voltage generator 10 generates the reference voltage VREF, and the core voltage generator 20 receives the external voltage VDD to receive the core voltage VCORE corresponding to the reference voltage VREF. ) Subsequently, the driving controller 30 activates the reset signal RST during precharging, and generates the first and second driving signals PD1 and PD2 corresponding to the data. Subsequently, the write driver 40 precharges the positive / negative local data lines LIO and LIOB in response to the reset signal RST, or the positive driver in response to the first and second driving signals PD1 and PD2. The secondary local data lines LIO and LIOB are driven. Subsequently, the core block 50 stores data carried in the positive and negative local data lines LIO and LIOB in the corresponding memory cell.

Meanwhile, an internal circuit diagram of the write driver 40 will now be described with reference to the drawings, and the specific driving will be described.

FIG. 2 is an internal circuit diagram of the write driver 40 shown in FIG. 1.

Referring to FIG. 2, the write driver 40 may include a precharging unit 42 for precharging the positive / negative local data lines LIO and LIOB in response to the reset signal RST, and the first and second units. And a pull-up / pull-down driver 44 for driving pull-up / pull-down of the positive / negative local data lines LIO and LIOB in response to the two driving signals PD1 and PD2.

Next, the driving of the write driver 40 will be described.

First, referring to the precharging process, the reset signal RST is activated to the logic level 'L', and both the first and second driving signals PD1 and PD2 are deactivated to the logic level 'L'.

Subsequently, the precharging unit 42 drives the positive / negative local data lines LIO and LIOB to the core voltage VCORE in response to the reset signal RST. In addition, the pull-up / pull-down driver 44 is turned off by deactivation of the first and second driving signals PD1 and PD2.

Meanwhile, the process of writing data in the positive / negative local data lines LIO and LIOB will be described. At this time, the reset signal RST is deactivated to the logic level 'H', and the first and second driving signals PD1 and PD2 are activated or deactivated according to the logic level of the applied data.

First, assuming that data corresponding to logic level 'H' is written in the positive / negative local data lines LIO and LIOB, the first driving signal PD1 has a logic level 'L' and the second driving is performed. Signal PD2 has a logic level 'H'. Subsequently, the pull-up / pull-down driver 44 pulls up the positive local data line LIO in response to the second driving signal PD2 and pulls down the sub-local data line LIOB.

In addition, assuming that data corresponding to the logic level 'L' is written in the positive / negative local data lines LIO and LIOB, the first driving signal PD1 has a logic level 'H' and the second driving is performed. Signal PD2 has a logic level 'L'. Subsequently, the pull-up / pull-down driver 44 pulls down the positive local data line LIO in response to the first driving signal PD1 and pulls up the sub-local data line LIOB.

In this way, the logic level corresponding to the data is applied to the positive / negative local data lines LIO and LIOB by the write driver 40. In addition, data loaded on the positive / negative local data lines LIO and LIOB are transferred to the core block 50 and stored in the corresponding memory cell.

On the other hand, in recent years, semiconductor memory devices have been developed in response to the demand for low power consumption in accordance with integration and high speed, and are gradually decreasing the voltage level of external voltages supplied from the outside as part of low power consumption. Therefore, the core voltage generated by down converting the external voltage also has a low voltage level, and in this situation, the driving force of the pull-up / pull-down driving unit 44 driving the positive / negative local data lines LIO and LIOB. This weakens. Therefore, when driving the positive / negative local data lines (LIO, LIOB) according to the data loaded on the global input / output line, if the bit line sense amplifier is driven before the constant voltage level is obtained due to insufficient core voltage, A problem occurs where the level is not determined. For reference, the bit line detection amplifier is a block for detecting and amplifying data transmitted through the positive / negative local data line and delivering the data to the corresponding memory cell. In addition, after the data is loaded on the positive / negative local data line to ensure a stable level, the bit line sense amplifier must be driven, which is also referred to as a mismatch of the bit line sense amplifier.

On the other hand, if the data of the positive / negative local data line does not have a stable level, the cell capacitor is charged with a voltage level lower than the predetermined voltage level, and data that is difficult to determine the logic level is stored in the memory cell.

That is, a malfunction of write driving occurs in which the cell capacitor is charged with a voltage level lower than the predetermined voltage level.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor memory device capable of stably storing data.

According to an aspect of the present invention, there is provided a semiconductor memory device including: pull-up / pull-down driving means for driving pull-up / pull-down of a second data line according to data loaded on a first data line; And an overdriving means for overdriving to an external voltage higher than a pullup voltage of the pull-up / pull-down driving means at the beginning of the pull-up period of the second data line, and for overdriving for a regulated period in response to a test signal.

According to another aspect of the present invention, there is provided a method of driving a semiconductor memory device in which a second data line is pulled up according to data loaded on a first data line, and adjusted according to a test signal at an initial stage of a pull-up driving period of the second data line. Overdriving the second data line for a time; And normal driving the second data line in a section after the overdriving section.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

Referring to FIG. 3, the semiconductor memory device according to the present invention receives a reference voltage generator 100 for generating the reference voltage VREF and a core voltage corresponding to the reference voltage VREF by receiving an external voltage VDD. The core voltage generation unit 200 for generating VCORE, the driving control unit 300 for generating the reset signal RST, the first and second driving signals PD1 and PD2, and the reset signal RST. Write to precharge the positive / negative local data lines (LIO, LIOB) in response to, or drive the positive / negative local data lines (LIO, LIOB) in response to the first and second driving signals (PD1, PD2). In the driving unit 400, the core block 500 for storing data carried in the positive / negative local data lines LIO and LIOB in the corresponding memory cell, and the first and second overdriving signals OVD_LIO1 and OVD_LIO2. In response, overdrive the positive / negative local data lines (LIO, LIOB) to the external voltage (VDD), but adjust in response to the test signals (T1, T2). Overdriving the overdriving unit 600, the overdriving signal generator 700 for generating the first and second overdriving signals OVD_LIO1 and OVD_LIO2, and the test signals T1 and T2. And a test signal generator 800 for generating.

Referring to the operation briefly, the reference voltage generator 100 generates a reference voltage VREF, and the core voltage generator 200 receives an external voltage VDD to receive a core voltage VCORE corresponding to the reference voltage VREF. ) Subsequently, the driving controller 300 activates the reset signal RST during precharging, and generates the first and second driving signals PD1 and PD2 corresponding to the data. In addition, the test signal generator 800 generates the test signals T1 and T2, and the overdriving signal generator 700 generates the first and second overdriving signals OVD_LIO1 and OVD_LIO2.

Subsequently, the write driver 400 precharges the positive / negative local data lines LIO and LIOB in response to the reset signal RST, or the positive driver in response to the first and second driving signals PD1 and PD2. The secondary local data lines LIO and LIOB are driven. In addition, the overdriving unit 600 responds to the first or second overdriving signals OVD_LIO1 and OVD_LIO2 during the period adjusted according to the test signals T1 and T2, and corresponding positive or negative local data lines LIO and LIOB. Overdrive to external voltage (VDD).

Subsequently, the core block 500 stores data carried in the positive / negative local data lines LIO and LIOB in the corresponding memory cell.

As described above, the semiconductor memory device according to the present invention further includes an overdriving unit 600 to overdrive the external voltage VDD when data is driven on the positive / negative local data lines LIO and LIOB. In addition, the length of the overdriven section may be adjusted by receiving the test signals T1 and T2. Therefore, it is possible to eliminate the problem that the level of data on the positive / negative local data lines LIO and LIOB is not stable due to the level drop of the conventional core voltage VCORE. In addition, the overdriving period can be adjusted to find an optimal overdriving time without unnecessary power consumption.

Meanwhile, a circuit implementation and connection of the overdriver 600 and the write driver 400 will now be described in detail with reference to the accompanying drawings.

FIG. 4 is an internal circuit diagram of the overdriver 600 and the write driver 400 shown in FIG. 3.

Referring to FIG. 4, the overdriving unit 600 may perform pull-up overdriving in response to the first and second overdriving signals OVD_LIO1 and OVD_LIO2 that are activated at the beginning of the pull-up period of the positive / negative local data lines LIO and LIOB. The first and second pulse generators 620 and 640 and the pull-up over-driving pulses DRVP10 and DRVP20 for generating pulses DRVP10 and DRVP20, and outputting the pulse widths in response to the test signals T1 and T2. An overdriver 660 is provided to pull-up and drive the positive / negative local data lines LIO and LIOB to the external voltage VDD in response to.

The write driver 400 may include a pull-up / pull-down driver 440 for driving pull-up / pull-down of the positive and negative local data lines LIO and LIOB in response to the first and second driving signals PD1 and PD2. And a precharging unit 420 for precharging the positive / negative local data lines LIO and LIOB in response to the reset signal RST.

For reference, the first and second driving signals PD1 and PD2 may be configured to pull up / pull down the positive / negative local data lines LIO and LIOB according to data applied to a global input / output line (not shown). It is a signal.

In addition, the reset signal RST is a signal that is activated for precharging operations of the positive and negative local data lines LIO and LIOB. In general, the precharging operation is a preparation process performed before the write operation, and the reset signal RST is activated to drive the positive / negative local data lines LIO and LIOB to the core voltage VCORE. In the precharging driving, the first and second driving signals PD1 and PD2 have a logic level 'L', thereby deactivating the pull-up / pull-down driving unit 440.

Meanwhile, the internal circuit diagram will be described below.

First, since the first and second pulse generators 620 and 640 of the overdriving unit 600 have the same circuit implementation, the first pulse generator 620 will be described.

The first pulse generator 620 may include a delay controller 622 for outputting the first overdriving signal OVD_LIO1 by applying a delay amount adjusted according to the test signals T1 and T2 and a first overdriving signal. And a signal output unit 624 for receiving the output signal of the OVD_LIO1 and the delay adjuster 622 to output the pull-up overdriving pulse DRVP10 in the form of a pulse.

The delay adjusting unit 622 includes a first delay unit 622a for delaying the first overdriving signal OVD_LIO1, a second delay unit 622b for delaying the output signal of the first delay unit 622a, and A first switch SW1 for switching the input node of the first delay unit 622a and the connection node of the first and second delay units 622a and 622b in response to the test signal T1; And a second switch SW2 for switching the connection node of the second delay units 622a and 622b and the output node of the second delay unit 622b in response to the test signal T2.

The signal output unit 624 has an inverter I2 for inverting the output signal of the delay adjusting unit 622, a NAND gate ND1 having an output signal of the inverter I2 and the first overdriving signal OVD_LIO1 as an input. And an inverter I3 for outputting the pull-up over-driving pulse DRVP10 by inverting the output signal of the NAND gate ND1.

The overdriver 660 has a pull-up over-driving pulse DRVP10 as a gate input, a PMOS transistor PM1 having a source-drain path between a supply terminal of the external voltage VDD and the local data line LIO, and a pull-up over-driving. A PMOS transistor PM2 having a pulse DRVP10 as a gate input and having a source-drain path between a supply terminal of the external voltage VDD and the local data line LIOB.

In addition, the precharging unit 420 of the write driver 400 includes a PMOS transistor PM5 having a reset signal RST as a gate input and a source-drain path between the core voltage and the local data line LIO, PMOS transistor PM6 having a reset signal RST as a gate input and having a source-drain path between the core voltage VCORE and the local data line LIOB, and a local data line having the reset signal RST as a gate input. PMOS transistor PM7 having a source-drain path between (LIO, LIOB) is provided.

The pull-up / pull-down driving unit 440 has an inverter I4 for inverting the second driving signal PD2, a gate input of an output signal of the inverter I4, and a supply terminal and a local data line LIO of the core voltage VCORE. And a drain-source path between the PMOS transistor PM3 having a source-drain path and a first driving signal PD1 as a gate input, and a supply terminal of the local data line LIO and the ground voltage VSS. An NMOS transistor NM1 having a gate, an inverter I5 for inverting the first driving signal PD1, an output signal of the inverter I5 as a gate input, and a supply terminal of the core voltage VCORE and a local data line LIOB. PMOS transistor (PM4) having a source-drain path and a second drive signal (PD2) as a gate input and a drain-source path between the local data line (LIOB) and the supply terminal of the ground voltage (VSS) NMOS transistor NM2 is provided.

FIG. 5 is a diagram illustrating pull-up over-driving pulses DRVP10 and DRVP20 by the first and second pulse generators 620 and 640 shown in FIG. 4. With reference to this, the driving of the overdriving unit 600 and the write driving unit 400 shown in FIG. 4 will be described.

First, it is assumed that the test signals T1 and T2 each have a 'C' having logic levels 'H' and 'L'. Furthermore, it is assumed that data corresponding to logic level 'H' is applied to the global data line so that the first driving signal PD1 has a logic level 'L' and the second driving signal PD2 has a logic level 'H'. do.

Subsequently, in response to the first and second driving signals PD1 and PD2, the pull-up / pull-down driving unit 440 pulls the positive local data line LIO to the core voltage VCORE level, and the secondary local data line LIOB) pulls down to the ground voltage (VSS) level.

In this case, since the first pulse generator 620 generates the pull-up over-driving pulse DRVP10 in response to the first overdriving signal OVD_LIO1, the PMOS transistor PM1 of the overdriver 660 that is applied to the first pulse generator 620 is activated. The positive local data line LIO is driven to the external voltage VDD level. Here, the pulse width of the pull-up overdriving pulse DRVP10 is equal to the delay amount of the first and second delay units 622a and 622b in the delay controller 622. This is because both the first and second switches SW1 and SW2 are turned off by the test signals T1 and T2 so that the first overdriving signal OVD_LIO1 turns off the first and second delay units 622a and 622b. Because it goes through.

Meanwhile, as described above, when the positive local data line LIO is pulled up and driven to the core voltage, the present invention drives together the external voltage VDD through the overdriver 660. Accordingly, even when the level of the core voltage VCORE is low or unstable, the positive local data line LIO may be stably driven to have a level corresponding to the logic level 'H'. In addition, the overdriven section may be adjusted according to the test signals T1 and T2. As mentioned above, in the case of 'C' passing through both the first and second delay units 622a and 622b, the positive local data line LIO is overdriven to an external voltage for the longest period. However, if the length of this section is excessively long, not only unnecessary power consumption may occur, but also a transistor to which it is applied may fail. Therefore, the test signal may be applied to overdrive during the appropriate interval.

Next, the test signal T1 is applied to the logic level 'H' and the test signal T2 is applied to the logic level 'H', so that the case of 'B' in which the overdriving interval is reduced will be described. As mentioned above, it is assumed that data corresponding to logic level 'H' is applied to the global data line.

Subsequently, in response to the first and second driving signals PD1 and PD2, the pull-up / pull-down driving unit 440 pulls the positive local data line LIO to the core voltage VOCRE level, and the sub-local data line LIOB) pulls down to the ground voltage (VSS) level.

In this case, the period in which the positive local data line LIO is driven to the external voltage VDD level by the overdrier 600 is equal to the delay amount of the second delay unit 622b. That is, the second switch SW2 is turned on by the test signal T2, and the pulse width of the pull-up overdriving pulse DRVP10 is determined only by the first delay unit 622a in the delay controller 622.

Finally, the test signal T1 is applied to the logic level 'L' and the test signal T2 is applied to the logic level 'H', so that the case of 'A' having the smallest overdriving interval will be described. As mentioned above, it is assumed that data corresponding to logic level 'H' is applied to the global data line.

Subsequently, in response to the first and second driving signals PD1 and PD2, the pull-up / pull-down driving unit 440 pulls the positive local data line LIO to the core voltage VCORE level, and the secondary local data line LIOB) pulls down to the ground voltage (VSS) level.

In this case, the period in which the positive local data line LIO is driven to the external voltage level by the overdriver 600 is equal to the pulse width of the first overdriving signal OVD_LIO1. That is, the first and second switches SW1 and SW2 are turned on by the test signals T1 and T2 so that the first overdriving signal OVD_LIO1 does not go directly through the first and second delay units 622a and 622b. This is because the output unit 624 outputs the pull-up overdriving pulse DRVP10.

On the other hand, when data corresponding to the logic level 'L' is applied to the global data line, data opposite to each other is applied to the positive / negative local data lines LIO and LIOB, and the first pulse generator 640 and Since only the point where the PMO transistor PM2 of the overdriver 660 overdrives is different and has the same driving, a detailed description thereof will be omitted.

On the other hand, as shown in Figure 5, the present invention can adjust the activation width of the pull-up over-driving pulse (DRVP10, DRVP20) by applying the test signal (T1, T2). As described above, C has the longest driving section through the first and second delay units 622a and 622b, and B has a shorter driving time than the C case only through the first delay unit 622a. Have Finally, in the case of A, since the first and second delay units 622a and 622b do not pass through, A has the shortest driving period compared to C and B.

As described above, the semiconductor memory device according to the present invention can find an optimal time for overdriving through application of a test signal.

FIG. 6 is a diagram illustrating a level change during write driving of a positive local data line (LIO) according to the present invention and the prior art.

As shown in FIG. 6, when the data corresponding to the logic level 'H' is applied to the conventional positive local data line LIO, the level temporarily decreases due to the level instability of the core voltage VCORE. have.

However, in the case of the positive local data line LIO according to the present invention, it can be seen that the level is stably maintained due to overdriving of the external voltage VDD. In addition, although not shown in the drawing, it is possible to control so that overdriving is performed during an optimal period by applying a test signal.

Therefore, the above-described semiconductor memory device according to the present invention overdrives when data is applied to the local data line, so that the data is stably applied to the local data line even if the level of the conventional core voltage is unstable. Therefore, there is no problem such as mismatch of the conventional bit line sense amplifier. In addition, since the voltage level of the local data line is stably maintained, data capable of discriminating the logic level is written to the corresponding memory cell, thereby enabling stable write driving.

On the other hand, the present invention can adjust the length of the overdriving section through the application of a test signal, it is possible to prevent unnecessary overpowering due to the short over-driving section, or unnecessary power consumption due to excessively long over-driving section have.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

In the above-described present invention, by overdriving to an external voltage in an initial section in which data is driven, the data write operation is stably performed by eliminating the problem caused by the level drop of the core voltage. In addition, the overdriving section can be adjusted with a test signal, performing overdriving for optimal time without unnecessary power consumption.

Claims (14)

delete Pull-up / pull-down driving means for driving pull-up / pull-down of the second data line according to data loaded on the first data line; And Overdriving means for overdriving to an external voltage higher than the pull-up voltage of the pull-up / pull-down driving means at the beginning of the pull-up section of the second data line, and overdriving for a regulated section in response to a test signal. Equipped with The overdriving means, By generating a first or second pull-up over-driving pulse in response to the first or second over-driving signal that is activated at the beginning of the pull-up period of the positive and negative second data line, by adjusting the pulse width in response to the test signal First and second pulse generators for outputting; And an overdriver for pull-up driving the positive or negative second data line to the external voltage in response to the first and second pullup overdriving pulses. A semiconductor memory device characterized in that. The method of claim 2, The pull up / pull down drive means, A first driver to pull up / pull down the second data line according to the data; And a second driver configured to pull up / pull down the sub-second data line according to the data. The method of claim 3, The first pulse generator, A delay adjuster for outputting the first overdriving signal by applying a delay amount adjusted according to the test signal; And a signal output unit configured to receive the first overdriving signal and the output signal of the delay adjuster to output the first pull-up overdriving pulse in a pulse form. A semiconductor memory device characterized in that. The method of claim 4, wherein The delay adjusting unit, A first delay unit for delaying the first overdriving signal; A second delay unit for delaying the output signal of the first delay unit; A first switch for switching an input node of the first delay unit and a connection node of the first and second delay units in response to a first test signal; And a second switch for switching the connection node of the first and second delay units and the output node of the second delay unit in response to a second test signal. The method of claim 5, The signal output unit, A first inverter for inverting the output signal of the delay adjusting unit; A first NAND gate having an output signal of the first inverter and the first overdriving signal as an input; And a second inverter for inverting the output signal of the first NAND gate and outputting the pull-up over-driving pulse. The method of claim 6, The overdriver, A third driver for driving the positive second data line in response to the first pull-up overdriving pulse; And a fourth driver for pull-up driving the sub-second data line in response to the second pull-up over-driving pulse. The method of claim 7, wherein The third driver, And a first PMOS transistor having the first pull-up over-driving pulse as a gate input and having a source-drain path between the supply terminal of the external voltage and the positive second data line. The method of claim 8, The fourth driver, And a second PMOS transistor having the second pull-up over-driving pulse as a gate input and having a source-drain path between the supply terminal of the external voltage and the secondary second data line. The method of claim 9, Overdriving signal generating means for generating said first and second overdriving signals; Test signal generating means for generating the first and second test signals; A core block for storing data on the positive and second data lines in a corresponding memory cell; Reference voltage generating means for generating a reference voltage; And a core voltage generating means for generating a core voltage which is a pull-up voltage of the pull-up / pull-down driving means corresponding to the reference voltage when the external voltage is applied. delete Pulling-up the second data line according to the data on the first data line, and overdriving the second data line for a time adjusted according to a test signal at an initial stage of the pull-up driving period of the second data line; And Normal driving the second data line in an interval after the overdriving interval Including The overdriving step, Generating a pull-up overdriving pulse having a pulse width corresponding to the test signal; And driving a second data line up in response to the pull-up overdriving pulse. The method of claim 12, The over-driving may include driving the second data line with an external voltage. The method of claim 13, The normal driving step, And driving the second data line at a voltage lower than the external voltage.

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