KR100894330B1 - Method and apparatus for supporting encryption/decryption function of aes and aria - Google Patents

Abstract

The present invention relates to an operation method and apparatus for supporting an advanced encryption standard (AES) and an academic, research institute, agency (ARIA) encryption / decryption algorithm. To this end, the present invention provides a key scheduler for generating a round key using an input key; And a round function operator configured to generate encrypted / decrypted data using the input data and the round key, wherein the round function operator includes an integrated substitution layer and an integrated diffusion layer capable of performing both AES and ARIA algorithms. An integrated computing device supporting the encryption / decryption functions of AES and ARIA is provided.

AES, ARIA, Encryption / Decryption, Integrated Computers

Description

Calculation method and apparatus supporting encryption / decryption function of AES and ARRIA {METHOD AND APPARATUS FOR SUPPORTING ENCRYPTION / DECRYPTION FUNCTION OF AES AND ARIA}

1 is an encryption process of the AES algorithm.

2 is an encryption process of the ARIA algorithm.

3 is a block diagram of an AES and ARIA integrated hardware computing device in accordance with one embodiment of the present invention.

4 is an internal block diagram of a unified replacement layer according to an embodiment of the present invention.

5 is an internal block diagram of the S _A S-Box block according to an embodiment of the present invention.

6 is an internal block diagram of a S _U S-Box block according to an embodiment of the present invention;

7 is an internal block diagram of an integrated spreading layer in accordance with an embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings

310: Round function calculator of AES and ARIA integrated hardware computing unit.

320: Unified substitution layer that performs substitution operations of AES and ARIA.

330: Unified spreading layer for spreading operations of AES and ARIA.

340: Register for storing 128-bit data.

350: Key scheduler for AES and ARIA integrated hardware computing units.

360: Block responsible for AES key scheduling.

370: Block responsible for ARIA key scheduling.

380: Register used for storing Wo key and AES key of ARIA.

410: S _A S-Box block to play the role of AES S-Box.

420: S _U S-Box block serving as AES and ARIA S-Box.

710: Middle term of the unified spread layer A.

720: Middle term of the unified spread layer B.

730: middle term of the unified spread layer C.

740: middle term of the unified spreading layer D.

750: Middle term of the unified spread layer E.

760: AES MixColumns operation result value Y of the unified diffusion layer.

770: AES InvMixColumns operation result Z of the unified spread layer.

780: ARIA spread operation result of the unified spread layer W.

790: MUX optionally determining the final result U of the unified spread layer.

The present invention relates to an operation method and apparatus for supporting an advanced encryption standard (AES) and an academic, research institute, agency (ARIA) encryption / decryption algorithm.

The AES block cipher algorithm was adopted as the American standard by the National Institute of Standards and Technology (NIST) in 2001. ARIA block cipher algorithm is also adopted as the standard of Korean industry standard. Two domestic and international standard block cipher algorithms such as AES and ARIA are widely used in various cipher fields such as smart card, ePassport, and server class cipher equipment.

Encryption operations are generally slow, so they are often implemented in hardware. In the hardware implementation field of AES or ARIA, research was mainly conducted to compare and analyze the performance by high performance implementation method or implementation method. However, with the development of small wireless technologies such as mobile phones and radio frequency identification (RFID), recent research on miniaturization and low power implementation has been published.

The research on integrated hardware cryptographic computing devices that support more than one cryptographic algorithm is less active than the research on computing devices for a single cryptographic algorithm. The reason is that hardware implementation, unlike software, generally requires twice as much hardware resources to implement two algorithms. However, as shown in FIG. 1 and FIG. 2, the AES and ARIA algorithms have a lot in common with each other in a round permutation structure (SPN) structure. First, in the case of S-Box, which is the base operation of the substitution layer, both algorithms use the same finite field GF (2 ⁸ ). In addition, in the constant matrix operation used in the spreading layer, terms common to both algorithms can be extracted.

In order to solve the above problems, the present invention provides a method and apparatus for integrated hardware operation that supports both AES and ARIA encryption / decryption functions by using hardware resource sharing techniques for common elements between AES and ARIA algorithms.

The present invention to achieve the above object, the step of receiving input data and round key; Performing S-Box operations commonly used for AES and ARIA in an integrated exchange layer of AES and ARIA using the input data and the round key; It provides a calculation method for supporting the encryption / decryption function of the AES and ARIA comprising the step of performing a spread operation in the integrated diffusion layer of AES and ARIA using the data on which the S-Box operation is performed.

In addition, to achieve the above object, the present invention, a key scheduler for generating a round key using the input key; And a round function operator configured to generate encrypted / decrypted data using the input data and the round key, wherein the round function operator includes an integrated substitution layer and an integrated diffusion layer capable of performing both AES and ARIA algorithms. An integrated computing device supporting the encryption / decryption functions of AES and ARIA is provided.

The terms used in the present invention are selected as general terms that are widely used at present, but in some cases, the term is arbitrarily selected by the applicant, in which case the meaning is described in the detailed description of the invention, The present invention should be understood as meanings of terms rather than names.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described.

3 is a block diagram of the AES and ARIA integrated hardware device proposed in the present invention. The round function operator 310 receives input data and a round key, and registers a register for the 128-bit data storage 340 around the integrated substitution layer 320 and the integrated diffusion layer 330 and a MUX for selecting a data path. Multiplexer), etc., and performs one round operation. In addition, the key scheduler 350 includes an AES key scheduler block 360 and an ARIA key scheduler block 370. The key scheduler 350 may calculate a round key required for each round in an “on-the-fly” manner. At this time, in order to save hardware resources, one of the ARIA's round key storage space, 128-bit register Wo 380 may be shared with the AES round key storage register.

4 is a block diagram showing the structure of the integrated substitution layer. Referring to FIG. 4, the unified replacement layer is composed of S _A (AES S-Box 410) and S _U (Unified S-Box 420). First, SA selectively performs Sl and Sl- ¹ functions such as Equation 1 below, which is an S-Box commonly used for AES and ARIA.

5 is a block diagram showing the internal structure of S _A. Where δ _A is an isomorphism function that maps an 8-bit input on GF (2 ⁸ ) to an element on GF (((2 ² ) ² ) ² ), and Aff _S1 is shown in Equation 1 below. Affine conversion function. Also, Aff _S1 ^-1 * δ _A and δ _A ^-1 * Aff _S1 are combined functions of δ _A and the affine transformation function. Such S _A has the same function as the S-Box used in AES, and thus detailed description thereof will be omitted.

는(i는 임의의 정수)는 적당한 8x8 이진 정칙 행렬 M_i를 사용하여M_i*x로 정리될 수 있다. 따라서 S-Box S₂와 S₂ ^-1는 아래의 [수학식 2]와 같이 정리될 수 있다. 도 6은 S_U의 내부 구조를 나타내는 블록도이다. 여기서 δ_U는 동형 함수이고 Aff_S2는 아래의 [수학식 2]에 나타낸 아핀 변환 함수이다. 이때 하드웨어 면적을 최적화하기 위해 가능한 동형 함수 δ_U를 모두 조사하여, δ_U, δ_U ^-1, Aff_S1 ^-1*δ_U, δ_U ^-1*Aff_S1, Aff_S2 ^-1*δ_U, δ_U ^-1*Aff_S2의 6개 함수에서 각각 사용하는 8x8 이진 행렬의 "1"의 개수가 가장 작은 동형 함수 δ_U를 결정하고 이에 따라 나머지 함수들도 계산한다.Meanwhile, S _U selectively performs four functions: S ₁ , S ₁ ^-1 , S ₂ , and S ₂ ^-1 . Where S ₂ uses x ²⁴⁷ instead of x ^-1 , for any element x on the finite field GF (2 ⁸ )

(I is any integer) can be summed into M _i * x using the appropriate 8x8 binary regular matrix M _i . Therefore, S-Box S ₂ and S ₂ ^-1 can be summarized as in [Equation 2] below. 6 is a block diagram showing the internal structure of S _U. Where δ _U is an isomorphic function and Aff _S2 is the affine transformation function shown in Equation 2 below. In order to optimize the hardware area, all possible homogeneous functions δ _U are investigated and δ _U , δ _U ^-1 , Aff _S1 ^-1 * δ _U , δ _U ^-1 * Aff _S1 , Aff _S2 ^-1 * δ _U , δ The smallest "1" number of 8x8 binary matrices used in each of the six functions of _U ^-1 * Aff _S2 determines the smallest isomorphic function δ _U and calculates the remaining functions accordingly.

The spreading layer of AES performs MixColumns and InvMixColumns operations at the time of encryption and decryption, respectively. In the spreading layer of the AES, matrix multiplication is performed on 32-bit data units. ARIA's spreading layer, on the other hand, performs 16x16 binary matrix multiplication by byte for all 128-bit data. The computing method and apparatus according to the present invention has a unified spreading layer of AES and ARIA operating in 128-bit units by evicting the common term used in the spreading layer of AES and ARIA.

First, the 128-bit result [Y ₀ , Y ₁ , Y ₂ , Y ₃ ] of the MixColumns operation on the 128-bit input [X ₀ , X ₁ , X ₂ , X ₃ ] in the AES algorithm is given by 3] can be summarized as follows. Here, X _i , Y _i represent 32-bit unit data.

Where the 4x4 matrix M ₀ , M ₀ ', M ₀ "is given by

In addition, the 128-bit result [Z ₀ , Z ₁ , Z ₂ , Z ₃ ] of the InvMixColumns operation is summarized in the same manner as shown in Equation 4 below. Here, Z _i represents 32-bit unit data.

Here, the 4x4 matrix M ₁ , M ₁ ′, M ₁ ″ is as shown below.

On the other hand, in the ARIA algorithm, 128-bit input [x ₀ , x ₁ , x ₂ , x ₃ , x ₄ , x ₅ , x ₆ , x ₇ , x ₈ , x ₉ , x ₁₀ , x ₁₁ , x ₁₂ , x ₁₃ , x ₁₄ , x ₁₅ ] result of diffusion operation [w ₀ , w ₁ , w ₂ , w ₃ , w ₄ , w ₅ , w ₆ , w ₇ , w ₈ , w ₉ , w ₁₀ , w ₁₁ , w ₁₂ , w ₁₃ , w ₁₄ , w ₁₅ ] may be expressed as Equation 5 below. Here, x _i and w _i represent 8-bit unit data. If Equation 5 is re-expressed in 32-bit unit operation, it can be summarized as in Equation 6 below. Here, _Wi and X _i represent 32-bit unit data.

,

,

는 원래 행렬의 비트별 역원으로 구성된 행렬이다.Where 4x4 matrices A, B, C, D, E, F, G are given by here,

,

,

Is a matrix of bitwise inverses of the original matrix.

Therefore, the result of MixColumns operation in AES [y ₀ , y ₁ , ..., y ₁₅ ] and the InvMixColumns operation [z ₀ , z ₁ for 128-bit input [x ₀ , x ₁ , ..., x ₁₅ } , ..., z ₁₅ ], and the result of ARIA's spreading operation [w ₀ , w ₁ , ..., w ₁₅ ] can be summarized as Equation 7 below using a common term.

The intermediate terms A _i , B _i , C _i , D _i , and E _i used here are as follows.

7 is a block diagram illustrating the structure of the integrated spreading layer. Referring to FIG. 7, the unified spreading layer generates a common term A 710, B 720 from a 128-bit input X, and C 730, D 740, E 750 from B 720. After the generation, MixColumns result Y 760 of AES, InvMixColumns result Z 770, and diffusion result W 780 of ARIA are generated from them. Finally, the MUX 790 is used to selectively determine the 128-bit result value U.

Although the present invention has been described in detail with reference to some embodiments, the above embodiments are presented for the purpose of understanding the present invention, and the scope of the present invention is not limited to the above embodiments. Those skilled in the art will understand that various modifications are possible without departing from the scope of the technical idea of the present invention, and the scope of the present invention should be interpreted by the appended claims.

The present invention provides an operation method and apparatus that support efficient AES and ARIA encryption / decryption algorithms. The calculation method and apparatus according to the present invention support both AES and ARIA encryption / decryption functions while minimizing hardware area by using an integrated substitution layer and an integrated diffusion layer. Therefore, it can be easily used for smart cards, ePassports, server-class cryptographic equipment that require two encryption algorithms such as AES and ARIA.

Claims (12)

Receiving input data and a round key; Performing S-Box operations commonly used for AES and ARIA in an integrated exchange layer of AES and ARIA using the input data and the round key; And And performing a spreading operation in an integrated spreading layer of AES and ARIA using the data on which the S-Box operation is performed. The method of claim 1, wherein the calculation method And generating the round key by performing key expansion by using an input key in a key scheduler. The method of claim 1, The integrated diffusion layer of the AES and the ARIA performs the spreading operation by selectively using an AES Mixcolumns function, an AES InvMixcolumns function, or an ARIA spreading function, and a method of supporting encryption / decryption functions of the AES and ARIA. . The method of claim 3, wherein The integrated diffusion layer is a method for supporting encryption / decryption functions of AES and ARIA, characterized in that the common terms of the AES Mixcolumns function, AES InvMixcolumns function, and ARIA spreading function. A key scheduler for generating a round key using an input key; And A round function calculation unit for generating encrypted / decrypted data using input data and the round key, And the round function calculation unit comprises an integrated substitution layer and an integrated diffusion layer capable of performing both AES and ARIA algorithms. The method of claim 5, wherein The unified replacement layer is integrated to support encryption / decryption functions of AES and ARIA, comprising a first block serving as an AES S-Box and a second block serving as an AES and an ARIA S-Box. Computing device. The method of claim 6, The second block includes an isomorphic function and an affine transformation function for converting the elements of the second block into elements on the extended finite field GF (((2 ² ) ² ) ² ) / encoding of AES and ARIA Integrated computing device that supports the decoding function. The method of claim 7, wherein The second block is an integrated computing device that supports encryption / decryption functions of AES and ARIA, wherein the homogeneous function having the smallest number of "1" s among the homogeneous function, the affine transform function, and a combination function thereof is selected. . The method of claim 5, wherein The integrated diffusion layer selectively supports the AES Mixcolumns function, the AES InvMixcolumns function, or the spread function of the ARIA, the integrated computing device supporting the encryption / decryption functions of the AES and ARIA. The method of claim 9, The integrated diffusion layer supports an encryption / decryption function of AES and ARIA, characterized in that the common terms of the AES Mixcolumns function, AES InvMixcolumns function, and ARIA spreading function. The method of claim 5, wherein The key scheduler includes an AES key scheduler block and an ARIA key scheduler block, and includes a round key selected from the keys of the two blocks, wherein the AES and ARIA support the encryption / decryption function. The method of claim 11, And an encryption / decryption function of AES and ARIA, wherein at least one of the key storage areas of the ARIA key modular block is used as a key storage area of the AES key modular block.

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