KR100892733B1 - Input circuit of semiconductor memory apparatus - Google Patents

Abstract

An input circuit of a semiconductor memory apparatus is provided to increase data efficiency by generating a high frequency without layout modification. A variable delaying unit(400) outputs a first and a second delay signal according to delay control signal. A first frequency transform unit(200) is formed to produce a third signal. The third signal has a higher frequency than a first and a second input delay signal by using a first signal and a second signal in response to a test mode signal. A secondary frequency transform unit(300) is formed to produce a fourth signal. The fourth signal has a higher frequency than a first and a second input delay signal by using a first signal and a second signal in response to a test mode signal.

Description

Input circuit of semiconductor memory device {Input Circuit Of Semiconductor Memory Apparatus}

The present invention relates to a semiconductor integrated circuit, and more particularly, to an input circuit of a semiconductor memory device.

Test equipment for testing a semiconductor integrated circuit is divided into a high frequency channel capable of supporting high frequency and a low frequency channel capable of not supporting high frequency.

The high frequency channel is provided with a much smaller number than the low frequency channel, and the high frequency channel should be used to test a large number of high speed semiconductor integrated circuits.

For example, if you have 128 high-frequency channels in your test equipment, and you need four signal inputs per semiconductor integrated circuit to test using the high-frequency channels, you can test up to 32 semiconductor integrated circuits at one time. Limited.

The data strobe signal WDQS used in the DRAM is basically positioned at the center of the data signal to be used as a strobe signal for data. Therefore, in order to test the operation of the DRAM of 1 GHz or more, the data strobe signal WDQS should be input at a period of 1 n and should be allocated to a high frequency channel to receive such an input.

As described above, in the operation test of the high speed semiconductor integrated circuit, a high frequency channel having a smaller number than the low frequency channel of the channels provided in the test equipment should be used.

Therefore, the number of semiconductor integrated circuits that can be tested at one time is limited according to the number of high frequency channels provided in the test equipment, thereby deteriorating test efficiency.

It is an object of the present invention to provide an input circuit of a semiconductor memory device for generating a signal having a high frequency having an accurate duty and frequency through a low frequency channel of the test equipment.

An input circuit of a semiconductor memory device according to the present invention is an input circuit of a semiconductor memory device, and configured to output a first input delay signal and a second input delay signal delayed by a first signal and a second signal according to a delay control signal. Variable delay unit; A first frequency converter configured to generate a third signal having a higher frequency than the first signal and the second input delay signal by using the first signal and the second input delay signal in response to a test mode signal ; And a second frequency configured to generate a fourth signal having a higher frequency than the second signal and the first input delay signal using the second signal and the first input delay signal in response to the test mode signal. It includes a conversion unit.

According to the present invention, a high frequency operation test is possible even through a low frequency channel of a test equipment, and a high frequency signal having an accurate duty and frequency can be generated, and a delay difference generated while generating a high frequency signal without modification of the layout can be corrected. There is an effect that can greatly improve the test efficiency.

Hereinafter, an exemplary embodiment of an input circuit of a semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of an input circuit of a semiconductor memory device according to the present invention.

As illustrated in FIG. 1, an input circuit of the semiconductor memory device includes a first frequency converter 200, a second frequency converter 300, and a variable delay unit 400.

The input circuit of the semiconductor memory device receives a signal through a test device having a plurality of high frequency channels and a plurality of low frequency channels and performs a test.

The variable delay unit 400 may include a first data strobe signal WDQS0 and a plurality of low frequency channels input through a first low frequency channel among the plurality of low frequency channels according to a delay control signal TM <0: N>. The first delayed data strobe signal WDQS0_Delay and the second delayed data strobe signal WDQS1_Delay which are delayed by the second data strobe signal WDQS1 input through the second low frequency channel are output.

The first frequency converter 200 mixes the first data strobe signal WDQS0 and the second delayed data strobe signal WDQS1_Delay in response to a test mode signal TMb to have the same frequency as that of the high frequency channel. Generate a frequency converted first data strobe signal (WDQS0_FC).

For example, when the test mode signal TMb is enabled, the first frequency converter 200 mixes the first data strobe signal WDQS0 and the second delayed data strobe signal WDQS1_Delay. Generating the frequency converted first data strobe signal WDQS0_FC having a frequency equal to that of a high frequency channel, and when the test mode signal TMb is disabled, the frequency having the same frequency as the first data strobe signal WDQS0 Generate a frequency converted first data strobe signal WDQS0_FC.

The first frequency converter 200 includes a first multiplexer 210 and a first mixer 220.

The first multiplexer 210 outputs a phase modulated first data strobe signal WDQS0b obtained by modulating a phase of the first data strobe signal WDQS0 to the first mixer 220. The first multiplexer 210 modulates a phase of the first data strobe signal WDQS0 in response to the test mode signal TMb or is fixed to a predetermined value (for example, a high level). The strobe signal WDQS0_C is output to the variable delay unit 400. The first multiplexer 210 may be implemented by a general MUX circuit.

The first mixer 220 mixes the phase modulated first data strobe signal WDQS0b and the second delayed data strobe signal WDQS1_Delay to output a first frequency converted data strobe signal WDQS0_FC. The first mixing unit 220 may be implemented as a general mix circuit.

The second frequency converter 300 mixes the second data strobe signal WDQS1 and the first delayed data strobe signal WDQS0_Delay in response to the test mode signal TMb to equal the frequency of the high frequency channel. A frequency converted second data strobe signal WDQS1_FC having a frequency is generated.

For example, when the test mode signal TMb is enabled, the second frequency converter 300 mixes the second data strobe signal WDQS1 and the first delayed data strobe signal WDQS0_Delay. The frequency converted second data strobe signal WDQS1_FC having the same frequency as the frequency of the high frequency channel is generated, and when the test mode signal TMb is disabled, the frequency having the same frequency as the second data strobe signal WDQS1. A frequency converted second data strobe signal WDQS1_FC is generated.

The second frequency converter 300 includes a second multiplexer 310 and a second mixer 320.

The second multiplexer 310 outputs a phase modulated second data strobe signal WDQS1b obtained by modulating a phase of the second data strobe signal WDQS1 to the second mixer 320. The second multiplexer 310 modulates the phase of the second data strobe signal WDQS1 in response to the test mode signal TMb or is fixed to a predetermined value (for example, a high level). The strobe signal WDQS1_C is output to the variable delay unit 400. The second multiplexer 310 may be implemented by a general MUX circuit.

The second mixing unit 320 outputs a second frequency converted data strobe signal WDQS1_FC by mixing the phase modulated second data strobe signal WDQS1b and the first delayed data strobe signal WDQS0_Delay. The second mixing unit 320 may be implemented by a general mixing circuit.

In addition, the input circuit of the semiconductor memory device illustrated in FIG. 1 may further include a buffer circuit unit 100.

The buffer circuit unit 100 includes first and second buffers 110 and 120. The first buffer 110 receives a first data strobe signal WDQS0 through the first low frequency channel of the plurality of low frequency channels of the test equipment. The second buffer 120 receives a second data strobe signal WDQS1 through the second low frequency channel of the plurality of low frequency channels. Signals output from the first buffer 110 and the second buffer 120 have a slight level difference from the input signal, but have little phase change, and thus are denoted by the same name.

The frequency converter according to the present invention receives the first data strobe signal WDQS0 input through the first low frequency channel and the second data strobe signal WDQS1 input through the second low frequency channel and is a high frequency signal. The first data strobe signal WDQS0_FC and the frequency converted second data strobe signal WDQS1_FC are generated. In particular, the present invention may correct the delay difference or skew that may occur while generating the high frequency signal by the variable delay unit 400. That is, even if the delay occurs, the delay level of the multiplexed first data strobe signal WDQS0_C or the multiplexed second data strobe signal WDQS1_C may be increased or decreased by adjusting the value of the delay control signal. Accordingly, the first mixer 220 or the second mixer 320 receives the corrected first delayed data strobe signal WDQS0_Delay or the second delayed data strobe signal WDQS1_Delay from FIG. 9. Likewise, the frequency-converted first data strobe signal WDQS0_FC or the frequency-converted second data strobe signal WDQS1_FC whose delay is adjusted may be generated. Accordingly, the present invention can generate a high frequency signal by compensating for the delay without changing the layout.

FIG. 2 is a detailed circuit diagram illustrating an embodiment of the first multiplexer 210 shown in FIG. 1.

The first multiplexer 210 includes a first logic unit 211 and a second logic unit 212.

The first logic unit 211 generates a phase modulated first data strobe signal WDQS0b by modulating a phase of the first data strobe signal WDQS0 and transmits the phase-modulated first data strobe signal WDQS0b to the first mixing unit 220. The first logic unit 211 may be implemented as a first inverter IV1 that inverts the phase of the first data strobe signal WDQS0.

When the test mode signal TMb is activated, the second logic unit 212 modulates a phase of the first data strobe signal WDQS0 and outputs the modulated phase to the variable delay unit 400.

The second logic unit 212 includes second to fourth inverters IV2 to IV4 and a first NAND gate ND1. The second inverter IV2 receives the test mode signal TMb. The first NAND gate ND1 receives the first data strobe signal WDQS0 and the output of the second inverter IV2. The third inverter IV3 receives the output of the first NAND gate ND1. The fourth inverter IV4 receives the output of the third inverter IV3. The multiplexed first data strobe signal WDQS0_C is output from the fourth inverter IV4.

3 is a detailed circuit diagram illustrating an embodiment of the first mixing unit illustrated in FIG. 1.

The first mixing unit 220 includes fifth to sixth inverters IV5 and IV6 and a second NAND gate ND2. The fifth inverter IV5 receives the phase modulated first data strobe signal WDQS0b. The sixth inverter IV6 receives the output of the fifth inverter IV5. The second NAND gate ND2 receives the second delay data strobe signal WDQS1_Delay and the output of the sixth inverter IV6. The frequency converted first data strobe signal WDQS0_FC is output from the second NAND gate ND2.

4 is a detailed circuit diagram illustrating an embodiment of the second multiplexer 310 shown in FIG. 1.

The second multiplexer 310 includes a third logic unit 311 and a fourth logic unit 312.

The third logic unit 311 generates a phase modulated second data strobe signal WDQS1b by modulating a phase of the second data strobe signal WDQS1 and transmits the phase modulated second data strobe signal WDQS1b to the second mixing unit. The third logic unit 311 may be implemented as a seventh inverter IV7 that inverts the phase of the second data strobe signal WDQS1.

When the test mode signal TMb is activated, the fourth logic unit 312 modulates a phase of the second data strobe signal WDQS1 and outputs the modulated phase to the variable delay unit 400.

The fourth logic unit 312 includes eighth to tenth inverters IV8 to IV10 and a third NAND gate ND3. The eighth inverter IV8 receives the test mode signal TMb. The third NAND gate ND3 receives the output of the second data strobe signal WDQS1 and the eighth inverter IV8. The ninth inverter IV9 receives the output of the third NAND gate ND3. The tenth inverter IV10 receives the output of the ninth inverter IV9. The multiplexed second data strobe signal WDQS1_C is output from the tenth inverter IV10.

FIG. 5 is a detailed circuit diagram illustrating an embodiment of the second mixing unit 320 shown in FIG. 1.

The second mixing unit 320 includes twelfth to thirteenth inverters IV12 and IV13 and a fourth NAND gate ND4. The twelfth inverter IV15 receives the phase modulated second data strobe signal WDQS1b. The thirteenth inverter IV13 receives the output of the twelfth inverter IV12. The fourth NAND gate ND4 receives the first delayed data strobe signal WDQS0_Delay and the output of the sixth inverter IV16. The frequency converted second data strobe signal WDQS1_FC is output from the fourth NAND gate ND4.

FIG. 6 is a detailed block diagram of the variable delay unit 400 shown in FIG. 1.

The variable delay unit 400 includes a first variable delay unit 410 and a second variable delay unit 420.

The first variable delay unit 410 delays the multiplexed first data strobe signal WDQS0_C in response to the delay control signal TM <0: N> to delay the first delayed data strobe signal WDQS0_Delay. Output

The second variable delay unit 420 outputs the second delayed data strobe signal WDQS1_Delay by delaying the multiplexed second data strobe signal WDQS1_C in response to the delay control signal TM <0: N>. do.

The delay control signal TM <0: N> input to the first variable delay unit 410 is different from the delay control signal TM <0: N> input to the second variable delay unit 420. The delay time of the multiplexed first data strobe signal WDQS0_C is delayed by the first variable delay unit 410 and the multiplexed second data strobe by the second variable delay unit 420. The delay time of the signal WDQS1_C is different.

FIG. 7 is a detailed circuit diagram of the first variable delay unit 410 illustrated in FIG. 6.

The first variable delay unit 400 includes a first delay unit 411 and a first transmitter 412.

The first transmitter 412 includes fifth and seventh NAND gates ND5 to ND7 that receive the multiplexed first data strobe signal WDQS0_C and the delay control signals TM0 to TM2. .

The fifth NAND gate ND5 receives the multiplexed first data strobe signal WDQS0_C and a third delay control signal TM2. The sixth NAND gate ND6 receives the multiplexed first data strobe signal WDQS0_C and a second delay control signal TM1. The seventh NAND gate ND7 receives the multiplexed first data strobe signal WDQS0_C and a first delay control signal TM0.

The first delay unit 411 includes a first delay unit 413 to a third delay unit 415 connected in series. The number of delay units activated in the first delay unit 411 varies according to the delay control signals TM0 to TM2.

The first delay unit 413 includes an eighth NAND gate ND8 that receives an output of the fifth NAND gate ND5 and a supply voltage. The second delay unit 414 includes an eighth NAND gate ND8 that receives an output of the sixth NAND gate ND6 and an output of the first delay unit 413. The third delay unit 415 includes a tenth NAND gate ND10 that receives an output of the seventh NAND gate ND7 and an output of the second delay unit 414.

The number of delay units can be added or reduced, and the delay unit can be implemented not only by the NAND gate but also by logic having the same function.

An operation of the first variable delay unit 410 illustrated in FIG. 7 is as follows.

When the first delay control signal TM0 is logic high, and the second delay control signal TM1 and the third delay control signal TM2 are logic low, the seventh NAND gate ND7 is configured as the multiplexer. A signal inverting the one data strobe signal WDQS0_C is output, and the fifth NAND gate ND5 and the sixth NAND gate ND6 output a logic high signal. Therefore, the output of the eighth NAND gate ND8 is logic high, and the output of the ninth NAND gate ND9 is logic high. Accordingly, the tenth NAND gate ND10 receives the output of the seventh NAND gate ND7 and the output of the ninth NAND gate ND9 of a high level, so that the multiplexed first data strobe signal WDQS0_C is received. The signal delayed by the seventh NAND gate ND7 and the tenth NAND gate ND10 is output.

In addition, when the third delay control signal TM2 is logic high and the first and second delay control signals TM0 and TM1 are logic low, the output of the sixth NAND gate ND6 and the seventh NAND are performed. The output of the gate ND7 is logic high, and the output of the fifth NAND gate ND5 is a signal obtained by inverting the multiplexed first data strobe signal WDQS0_C. In this case, the fifth NAND gate ND5, the eighth NAND gate ND8, the ninth NAND gate ND9, and the tenth NAND gate ND10 have the same function as an inverter, and thus the first variable delay unit In operation 410, the multiplexed first data strobe signal WDQS0_C is delayed by the fifth, eighth, ninth, and tenth NAND gates ND5, ND8 to ND10.

In addition, when the second delay control signal TM1 is logic high and the first and third delay control signals TM0 and TM2 are logic low, the first variable delay unit 410 is configured to provide the multiplexed first data. The strobe signal WDQS0_C is output by a signal delayed by the sixth NAND gate ND6, the ninth NAND gate ND9, and the tenth NAND gate ND10.

FIG. 8 is a detailed circuit diagram of the second variable delay unit 420 shown in FIG. 6.

The second variable delay unit 420 includes a second delay unit 421 and a second transmission unit 422.

The second transmitter 422 includes eleventh NAND gates ND11 to 13th NAND gates ND13 that receive the multiplexed second data strobe signal WDQS1_C and the delay control signals TM0 to TM2. . The delay control signal input to the second transmitter 422 may be a signal different from the delay control signal input to the first transmitter 412.

The eleventh NAND gate ND11 receives the multiplexed second data strobe signal WDQS1_C and a third delay control signal TM2. The twelfth NAND gate ND12 receives the multiplexed second data strobe signal WDQS1_C and a second delay control signal TM1. The thirteenth NAND gate ND13 receives the multiplexed second data strobe signal WDQS1_C and a first delay control signal TM0.

The second delay unit 421 includes fourth delay units 423 to sixth delay units 425 connected in series.

The fourth delay unit 423 includes a fourteenth NAND gate ND14 that receives an output of the eleventh NAND gate ND11 and a supply voltage. The fifth delay unit 424 includes a fifteenth NAND gate ND15 that receives an output of the twelfth NAND gate ND12 and an output of the fourth delay unit 423. The sixth delay unit 425 includes a sixteenth NAND gate ND16 that receives an output of the thirteenth NAND gate ND13 and an output of the fifth delay unit 424.

The operation of the input circuit of the semiconductor memory device according to the present invention configured as described above will be described with reference to FIGS. 1 to 9.

In the semiconductor integrated circuit test mode, the first data strobe signal WDQS0 is input to the first multiplexer 210 through the first buffer 110 of FIG. 1 in the first low frequency channel of the test equipment.

In addition, the second data strobe signal WDQS1 is input to the second multiplexer 310 through the second buffer 120 of FIG. 1 in the second low frequency channel of the test equipment.

As illustrated in FIG. 9, the first data strobe signal WDQS0 and the second data strobe signal WDQS1 have different data strobe timings, and each has a low frequency period (for example, 2 ns).

As the test mode is entered, the test mode signal TMb is activated at a low level.

The first multiplexer 210 of FIG. 2 modulates the phase of the first data strobe signal WDQS0 through the first inverter IV1, that is, the phase modulated first data strobe signal WDQS0b inverting the phase. The output to the first mixing unit 220.

Also, since the test mode signal TMb is activated at a low level, the first multiplexer 210 of FIG. The phase of the first data strobe signal WDQS0 is inverted to output the multiplexed first data strobe signal WDQS0_C.

The first variable delay unit 410 of FIG. 7 determines the number of stages of the eighth NAND gate ND8, the ninth NAND gate ND9, and the tenth NAND gate ND10 according to the delay control signals TM0 to TM2. By adjusting, the multiplexed first data strobe signal WDQS0_C is delayed for a predetermined time to transmit the first delayed data strobe signal WDQS0_Delay to the second mixing unit 320.

In addition, the second variable delay unit 420 of FIG. 8 may include the fourteenth NAND gate ND14, the fifteenth NAND gate ND15, and the sixteenth NAND gate ND16 according to the delay control signals TM0 to TM2. By adjusting the number of stages, the multiplexed second data strobe signal WDQS1_C is delayed for a predetermined time to transmit the second delayed data strobe signal WDQS1_Delay to the first mixing unit 220.

The first mixing unit 220 of FIG. 3 inverts the phase of the second delayed data strobe signal WDQS1_Delay while the phase modulated first data strobe signal WDQS0b maintains a high level to convert the first data into frequency. Output the strobe signal WDQS0_FC. In addition, the first mixer 220 outputs a high level frequency converted first data strobe signal WDQS0_FC while the phase modulated first data strobe signal WDQS0b maintains a low level.

Accordingly, as shown in FIG. 9, the frequency-converted first data strobe signal WDQS0_FC has a high frequency period (eg, 1 ns) equal to the period of a signal output through the high frequency channel of the test equipment. In this case, since the delay degree of the second delayed data strobe signal WDQS1_Delay varies according to the delay control signals TM0 to TM2, the duty and delay of the frequency-converted first data strobe signal WDQS0_FC are changed as shown in FIG. 9. I can regulate it.

Simultaneously with the operation of the first frequency converter 200, the second multiplexer 310 shown in FIG. 4 modulates the phase of the second data strobe signal WDQS1 through a seventh inverter IV7. That is, the phase modulated second data strobe signal WDQS1b having the inverted phase is output to the second mixing unit 320.

In addition, since the test mode signal TMb is activated at the low level, the second multiplexer 310 of FIG. The phase of the second data strobe signal WDQS1 is inverted to output the multiplexed first data strobe signal WDQS1_C.

The second mixing unit 320 of FIG. 5 inverts the phase of the first delayed data strobe signal WDQS0_Delay while the phase modulated second data strobe signal WDQS1b maintains a high level to convert the frequency-converted second data. The strobe signal WDQS1_FC is output. The second mixing unit outputs a high level frequency converted second data strobe signal WDQS1_FC while the phase modulated second data strobe signal WDQS1b maintains a low level.

As shown in FIG. 9, the frequency-converted second data strobe signal WDQS1_FC has the same period (eg, 1 ns) as the period of the signal output through the high frequency channel of the test equipment. In this case, since the delay degree of the first delayed data strobe signal WDQS0_Delay varies according to the delay adjustment signals TM0 to TM2, the duty and delay of the frequency converted second data strobe signal WDQS1_FC may be adjusted.

The frequency converted first data strobe signal WDQS0_FC and the frequency converted second data strobe signal WDQS1_FC may be combined and used as an internal data strobe signal in the configuration of the semiconductor integrated circuit according to the present invention.

As a result, the present invention described above converts the first data strobe signal WDQS0 of the low frequency (2ns) input through the first low frequency channel of the test equipment into the frequency-converted first data strobe signal WDQS0_FC of the high frequency (1ns). At the same time, the second data strobe signal WDQS1 of low frequency (2ns) input through the second low frequency channel of the test equipment is converted into a frequency conversion second data strobe signal WDQS1_FC of high frequency (1ns). You can print

On the other hand, when the test mode ends and enters the normal mode, the test mode signal TMb is deactivated to a high level.

Since the test mode signal TMb is at a high level, the first multiplexer 210 of FIG. 2 and the second multiplexer 310 of FIG. 4 are respectively multiplexed first data strobe signal WDQS0_C and multiplexed second data. The strobe signal WDQS1_C is held at a high level.

Since the multiplexed second data strobe signal WDQS1_C is maintained at a high level, the second variable delay unit 420 of FIG. 8 outputs the second delay data strobe signal having a high level, and the first mixing unit 220. Outputs the frequency-converted first data strobe signal WDQS0_FC by inverting the phase of the phase-modulated first data strobe signal WDQS0b. The frequency-converted first data strobe signal WDQS0_FC output while the test mode signal TMb is inactivated has the same waveform and period 2ns as the first data strobe signal WDQS0.

Since the multiplexed first data strobe signal WDQS0_C is maintained at a high level, the first variable delay unit 410 of FIG. 7 outputs the first delay data strobe signal having a high level, and the second mixing unit of FIG. 320 inverts the phase of the phase modulated second data strobe signal WDQS1b to output the frequency-converted second data strobe signal WDQS1_FC. The frequency-converted second data strobe signal WDQS1_FC output while the test mode signal TMb is inactivated has the same waveform and period 2ns as the second data strobe signal WDQS1.

The present invention described above is merely an example of a data strobe signal, and may generate a high frequency signal by combining low frequency signals having different pulse generation timings, and generate a high frequency signal having a more accurate duty and frequency by the delay adjuster. Can be. Therefore, the signal can be easily applied to a signal having a different timing of pulse generation, for example, clock signals CLK and CLK /.

In addition, the variable delay unit 400 may be disposed between the first frequency converter 200 and the second frequency converter 300.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents are included in the scope of the present invention. Should be.

1 is a block diagram of an input circuit of a semiconductor memory device according to the present invention;

2 is a detailed circuit diagram illustrating an embodiment of a first multiplexer illustrated in FIG. 1;

3 is a detailed circuit diagram illustrating an embodiment of the first mixing unit illustrated in FIG. 1;

4 is a detailed circuit diagram illustrating an embodiment of a second multiplexer illustrated in FIG. 1;

5 is a detailed circuit diagram illustrating an embodiment of the second mixing unit illustrated in FIG. 1;

6 is a detailed block diagram of the variable delay unit shown in FIG. 1;

7 is a detailed circuit diagram of the first variable delay unit illustrated in FIG. 6;

8 is a detailed circuit diagram of the second variable delay unit illustrated in FIG. 6;

9 is a timing diagram of an input circuit of a semiconductor memory device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

100: buffer circuit section 110: first buffer

120: second buffer 200: first frequency converter

210: first multiplexer 220: first mixer

300: second frequency converter 310: second multiplexer

320: second mixing unit 400: variable delay unit

410: first variable delay unit 420: second variable delay unit

Claims (18)

In the input circuit of a semiconductor memory device, A variable delay unit configured to output a first input delay signal and a second input delay signal delayed by the first signal and the second signal according to the delay adjustment signal; A first frequency converter configured to generate a third signal having a higher frequency than the first signal and the second input delay signal by using the first signal and the second input delay signal in response to a test mode signal ; And A second frequency conversion configured to generate a fourth signal having a higher frequency than the second signal and the first input delay signal using the second signal and the first input delay signal in response to the test mode signal An input circuit of a semiconductor memory device comprising a portion. The method of claim 1, And the first signal and the second signal include a data strobe signal or a clock signal. The method of claim 1, The first frequency converter, When the test mode signal is enabled, the first signal and the second input delay signal are mixed to generate the third signal. And outputting the third signal having the same frequency as the first signal when the test mode signal is disabled. The method of claim 3, wherein The first frequency converter A first multiplexer which transmits or blocks the first signal to the variable delay unit in response to the test mode signal, and And a first mixing unit configured to generate the third signal by mixing the first signal and the second input delay signal. The method of claim 4, wherein The first multiplexer A first logic unit modulating a phase of the first signal and transmitting the modulated phase to the first mixing unit; And a second logic unit configured to modulate the phase of the first signal and output the modulated phase to the variable delay unit when the test mode signal is activated. The method of claim 5, wherein And the first logic unit is configured to invert the phase of the first signal. The method of claim 5, wherein The second logic unit, And when the test mode signal is inactivated, output a signal fixed at a predetermined voltage level to the variable delay unit. The method of claim 5, wherein The first mixing unit, And modulate a phase of the second delayed input signal in response to the first signal to output the third delayed signal as the third signal. The method of claim 4, wherein The second frequency converter When the test mode signal is enabled, the fourth signal is generated by mixing the second signal and the first input delay signal. And outputting the fourth signal having the same frequency as the second signal when the test mode signal is disabled. The method of claim 5, wherein The second frequency converter A second multiplexer which transmits or blocks the second signal to the variable delay unit in response to the test mode signal, and And a second mixing unit configured to generate the fourth signal by mixing the second signal and the first input delay signal. The method of claim 10, The second multiplexer, A third logic unit modulating a phase of the second signal and transmitting the modulated phase to the second mixing unit; And a fourth logic unit configured to modulate the phase of the second signal and output the modulated phase to the variable delay unit when the test mode signal is activated. The method of claim 10, The second mixing unit And modulate a phase of the first delayed input signal in response to the second signal to output the fourth delayed signal as the fourth signal. The method of claim 10, The variable delay unit, A first variable delay unit receiving the output of the first multiplexer and delaying the delay control signal to output the first input delay signal; And And a second variable delay unit configured to receive an output of the second multiplexer and delay the response signal in response to the delay control signal to output the second input delay signal. The method of claim 13, The first variable delay unit, And a plurality of delay units, wherein the number of the delay units activated by receiving the output of the first multiplexer according to the delay control signal varies. The method of claim 1, The variable delay unit, A first variable delay unit outputting the first input delay signal delayed from the first signal in response to the delay control signal; And And a second variable delay unit configured to output the second input delay signal delayed from the second signal in response to the delay control signal. The method of claim 1, And a buffer circuit unit for buffering the first signal and the second signal and inputting the first signal and the second signal to the first frequency converter and the second frequency converter. The method according to any one of claims 1 to 16, And the first signal and the second signal are signals having different data strobe timings. The method according to any one of claims 1 to 16, The variable delay unit, And an input circuit disposed between the first frequency converter and the second frequency converter.

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