KR100878801B1 - Method for scrambling physical channel transmitting format - Google Patents

Abstract

The present invention relates to transmitting physical channel transmission format information. Particularly, when a transmitting and receiving end transmits and receives a physical channel having various formats, the present invention scrambles and transmits a transmission format, and the receiving end efficiently detects the transmission format of the physical channel. The present invention relates to a physical channel transmission format scrambling method and an apparatus for transmitting physical channel transmission format information. In the physical channel transmission format scrambling method, when a physical channel having a variable length transmission format is generated on the transmitting side and transmits arbitrary data to the receiving side, the arbitrary length data of the variable length transmission format is transmitted to the variable length transmission format. When scrambling and transmitting information, the scrambling is performed using the same output bit as the descrambler to be used at the time of descrambling the data transmitted from the receiver.

Blind Format, Scrambling

Description

Method for scrambling physical channel transmitting format

1 is a block diagram of a transmission chain of a typical F-SPDCCH

2 is a block diagram of a transmission chain of an F-SPDCCH according to a conventional scheme

3 is a diagram for describing scrambling and descrambling of an F-SPDCCH according to the present invention.

4 is a block diagram of a transport chain block of an F-SPDCCH according to the present invention.

FIG. 5 is a block diagram illustrating the scrambler shown in FIG.

FIG. 6 illustrates a descrambler for descrambling the scrambler shown in FIG. 4. FIG.

7 is a view for explaining the operation of the mask of the present invention.

8 illustrates scrambling and descrambling of a transmitting side and a receiving side according to the first embodiment of the present invention.

9 illustrates scrambling and descrambling of a transmitting side and a receiving side according to the second embodiment of the present invention.

10 illustrates scrambling and descrambling of a transmitting side and a receiving side according to the third embodiment of the present invention.

The present invention relates to transmitting physical channel transmission format information. Particularly, when a transmitting and receiving end transmits and receives a physical channel having various formats, the present invention scrambles and transmits a transmission format, and the receiving end efficiently detects the transmission format of the physical channel. The present invention relates to a physical channel transport format scrambling method.

In some types of wired and wireless communication systems, a specific physical channel may be transmitted in various formats, but the receiving side may need to receive the channel without clear information about the transmission format. Therefore, the receiving end should perform blind format detection. An example of such a system is the 1x-EVDV system (Cdma2000-Revision-C), which is being developed as a next generation mobile communication system.

In the 1x-EVDV system, a forward packet data channel (PDCH), which is a physical channel for transmitting packet data, and a plurality of forward secondary packet data control channels for transmitting control information of the F-PDCH Secondary Packet Data Control Channel (hereinafter referred to as S-PDCCH) is used.

Hereinafter, each of the plurality of F-SPDCCHs is referred to as F-SPDCCH (i) (i = 0, 1, 2,...). Each F-SPDCCH (i) uses W _i ⁶⁴ in a 1: 1 correspondence during transmission. W _i ⁶⁴ stands for any of the 64 length Walsh codes.

Hereinafter, a transmission chain of an F-SPDCCH according to the prior art will be described with reference to the accompanying drawings.

1 is a configuration diagram of a transmission chain block of a general F-SPDCCH.

Basically, the current SPDCCH is a cyclic redundancy checking (CRC) of two kinds of information (Inner CRC, Outer CRC) for checking various information necessary for decoding of x bits and whether there is a reception error of the information. Abbreviated) bit, and a convolutional encoder tail bit. The information of the bits configured in this way is subjected to convolutional coding of 1/2, 1/3, or 1/4 to produce coded bits.

In this case, the transmission length of the F-SPDCCH may be 1 slot, 2 slots, or 4 slots. Here, the slot means a time unit of 1.25 msec. At this time, the transmitting end does not inform the receiving end of the length of the F-SPDCCH being transmitted. That is, the receiving end can not clearly know what format. Therefore, the receiver performs a decoding process for all three formats (three lengths) and checks CRCs to know what the transmission length (or format) of the received F-SPDCCH is. The format determined to be CRC = 1 is determined to be the correct format. Here, CRC = 1 means that there is no error in the data transmitted on the F-SPDCCH through the CRC check. On the contrary, CRC = 0 means a case where it is determined that there is an error in data transmitted on the F-SPDCCH through the CRC check.                         

At this time, for efficient transmission and reception of the F-SPDCCH, a scrambler as shown in FIG. 2 is added when the F-SPDCCH is generated. Here, the scrambler is a device that generates 0 and 1 relatively randomly.

The addition position of the scrambler may be any one of P1, P2, P3, P4, P5, P6, P7, and P8 shown in FIG. 1, and the symbol repetition block 104 and the puncturing block 105 are symbols It can be operated as a repeat / control block.

FIG. 2 is an exemplary diagram when a scrambler 109 is added to P2 when the output bit of the first CRC generator is 21 bits.

In FIG. 2, CommonMask (i) is a type of long code mask having a 1: 1 correspondence with F-SPDCCH (i), and outputs the output of the scrambler 109 according to each F-SPDCCH (i). It plays a different role. At this time, CommonMask (i) does not distinguish between three formats (1, 2, 4 slot transmission length) of each F-SPDCCH (i). That is, the same for the three formats of each F-SPDCCH (i). Long code mask is used.

On the other hand, CommonMask (i) may be the same value for all i, the content of the present invention is irrelevant.

In the conventional scheme as shown in FIG. 2, several slots are used for blind format detection at the receiving side (MS) by using the same long code mask CommonMask (i) regardless of three formats according to the transmission length of the F-SPDCCH. The scrambler output value must be stored. As a result, additional memory is required. This is to solve the problem caused by the time difference between the base station (BS) and the transmission and reception of the F-SPDCCH on both sides of the terminal (MS), the additional hardware is required to solve this problem. Therefore, it is necessary to develop a scrambler that does not need to increase the complexity of hardware.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and allows a wired / wireless transmitter to scramble and transmit format information when transmitting data through a specific physical channel. It is an object of the present invention to provide a method of scrambling a transport channel format capable of accurately determining a format type.

According to one aspect of the present invention as described above, when the transmitting side transmits arbitrary data having a variable length transmission format to the receiving side, a mask formed according to the variable length transmission format of arbitrary data of the variable length transmission format When scrambled with information, the scrambler uses the same output bit as the descrambler to be used at the time of descrambling the transmitted data at the receiver. Here, the variable length of the transmission format means that the transmission length of the physical channel may vary.

Preferably, the mask information is formed by combining common mask information and slot length information, and the receiving side descrambles using common mask information among the mask information.                         

And the common mask information and mask information format,

or,

or,

It consists of any one of the formats.

And, the scrambling,

A first periodic addition check block for adding an error detection code to the data, a second periodic addition check block, a tail bit addition block for adding tail bits for indicating a final state of an encoder encoding the data to the data; A convolutional encoder for encoding the tail bit-added data into a convolutional code, a symbol repetition block for symbol repetition according to a length of a slot for transmitting the encoded bits, and puncturing the symbol repeated bits Data or output bits output from any one of a puncturing block, a block interleaver interleaving the punctured bits, and a modulation block modulating according to the transmission-side modulation scheme, or a first periodic addition check block. Scrambling to the input data.

Preferably, the scrambler of the transmitting side comprises: a long code generator for generating a long code according to the mask information, a scrambling bit extractor for extracting and outputting necessary bits among the bits output from the long code generator; A first register configured to store a bit output from the scrambling bit extracter by a set bit, a second register copying an output bit of the first register, and the first and second registers, respectively, of the first register. And a long code generator configured to copy an output bit to the second register at a specific time set in one slot, wherein the scrambler on the receiving side generates a long code according to the common mask information. The scrambling bit adder that extracts and outputs the necessary bits among the bits output from the code generator. A first register configured to store a bit output from the scrambling bit extractor by a set bit, a second register copying an output bit of the first register, and a first register and a second register. And a switch for copying the output bit of the register to the second register at a specific time set in one slot.

Hereinafter, a configuration and an operation according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

First, in order to describe the present invention, the 1x-EVDV system will be described using an F-SPDCCH used for transmitting control information of an F-PDCH, which is a physical channel for transmitting packet data. For convenience of explanation, it is assumed that two F-SPDCCHs are used, and each of them is called F-SPDCCH (0) and F-SPDCCH (1). In addition, it is assumed that there are three types of transmission formats that each F-SPDCCH (i) may have according to transmission lengths (1 slot, 2 slots, and 4 slots). That is, the variable length transmission format means that the transmission length of the physical channel may be changed in this way. The format of each F-SPDCCH at this time is called FM (i, N). In this case, i = 0, 1 in FM (i, N) means F-SPDCCH (0) and F-SPDCCH (1), respectively, and N = 1, 2, and 4 are 1 slot and 2 slot ( slot, means 4 slots, respectively. For example, FM (1, 2) means the F-SPDCCH (1) having a two slot transmission length.

In addition, the position where the scrambler is added may be any one of P1, P2, P3, P4, P5, P6, P7, and P8 shown in FIG. 1 as described in FIG. 2, and for convenience of description, the first CRC generator When the output bit of the (Inner CRC) is 21 bits, the case where a scrambler is added to P2

The above assumptions are merely for convenience of explanation, and the present invention may be applied to other systems in which the number of channels to be distinguished, the number of formats, or the position of a scrambler are different.

3 is a diagram illustrating scrambling and descrambling of an F-SPDCCH according to the present invention, and FIG. 4 is a block diagram of a transmission chain block of the F-SPDCCH according to the present invention.

First of all, the present invention uses a scrambler for efficient transmission and reception of an F-SPDCCH without increasing hardware complexity. The proposed specific rule is to generate an output bit of a scrambler in consideration of the transmission / reception time difference of the F-SPDCCH between the BS and the MS according to the FM (i, N) of the F-SPDCCH currently being transmitted and received.

3 shows that there is no transmission delay between the transmitting and receiving ends, any scrambler Scrambler (x) scrambles 21 bits of output information of the first CRC generator (Inner CRC) 100 at a corresponding time on the BS side. Refers to 21 bits of output of a scrambler used for scrambling.

Similarly, any other scrambler (Scrambler (x ')) means the output 21 bits of the scrambler (scrambler) used for the descrambling (De- scrambling) at the MS side at that time.

For example, in FIG. 3, the output bits of the scrambler used when transmitting the (a), (b), and (c) F-SPDCCHs that start transmission at the start of slot 2 in the BS side are shown in FIG. The first scrambler (Scrambler (1)). If there is an F-SPDCCH starting transmission at the start of slot 5 on the BS side, the output bits of the scrambler used when transmitting the F-SPDCCH are the fourth scrambler 4.

Also, the output bits of the scrambler used for de-scrambling the F-SPDCCH indicated by (a) on the MS side in FIG. 3 are the second 'scrambler 2'.

The output bits of the scrambler used for de-scrambling the F-SPDCCH indicated by (b) on the MS side are the third 'scrambler (3').                     

The output bits of the scrambler used for de-scrambling the F-SPDCCH indicated by (c) on the MS side are a 5 'scrambler 5'.

Based on the above description, if the BS and the MS drive the scrambler according to the same operation principle, that is, if any scrambler (x)) = any scrambler '(x') The output bits of the scrambler used when scrambling and descrambling the same F-SPDCCH are different.

For example, in Figure 3, the output bits of the scrambler used to scramble the F-SPDCCH indicated by the BS as (a) in FIG. 3 are the first scrambler (1), and the MS (a The output bits of the scrambler used for de-scrambling the F-SPDCCH, denoted by < RTI ID = 0.0 >), are < / RTI > second 'scrambler (2').

At this time, the contents of the present invention are as follows.

The scrambler of the BS and the MS is driven by different rules to have output bits of the scrambler used when scrambling and descrambling the same F-SPDCCH.

As one method for this purpose, the scrambler of the BS may be driven so that different outputs are generated according to the FM (i, N) of the F-SPDCCH to be currently transmitted.

The above description will be described with reference to FIG. 3 as an example.                     

When the BS transmits the F-SPDCCH indicated by (a), the first scrambler (1) drives the scrambler on the BS side to have the same value as the 2 'scrambler (2').

When the BS transmits the F-SPDCCH indicated by (b), the first scrambler 1 drives the scrambler on the BS side to have the same value as the 3 'scrambler 3'.

When the BS transmits the F-SPDCCH indicated by (c), the first scrambler 1 drives the scrambler on the BS side to have the same value as the 5 'scrambler 5'.

The present invention may be implemented in various ways, but will be described below with an example implemented using a long code mask. In addition, the present invention can be applied regardless of the number of F-SPDCCH input bits, the use of the first and second CRC generators 100 and 101, the insertion position of the scrambler, and the like.

Basic configuration

3 illustrates a case in which a scrambler 109 is added to P2 of FIG. 1 when the output bit of the first CRC generator 100 is 21 bits. The scrambler 109 operates according to Mask (i, N), which is a code mask.

In this case, Mask (i, N) is a variable having a 1: 1 correspondence with FM (i, N), and the output bits of the scrambler 109 differ according to the F-SPDCCH format FM (i, N). It plays a role.

In order to implement the proposed scrambler, we use the long code generator which is used in the general code division multiple access (CDMA) system.

FIG. 5 is an exemplary view of the scrambler of FIG. 4 and illustrates an operation of the BS.

As described above, output bits are generated at a long code high-speed chip transfer rate (which generates 1228800 output symbols per second).

The scrambling bit extractor serves to extract only necessary bits among bits output at a high speed from a long code generator. For example, it is assumed that the scrambling bit extractor outputs bits at a speed of 19.2 kbps.

Mask (i, N), which is a long code mask, has a 1: 1 correspondence with FM (i, N), and has the same operation principle as that of a conventional long code mask. The switch between Z4 and Z5 is used to copy the contents of the 21-bit transition register A to the 21-bit transition register B at a specific point in time that is previously defined between the BS and the MS in a slot. The 21-bit transition register B generates an output only during the scrambling operation to perform an XOR operation with the output 21 bits of the first CRC generator (Inner CRC) 100 generator.

6 is a diagram illustrating an operation at the MS side when the scrambler is used at the BS side according to FIGS. 4 and 5.                     

The operation principle of each part in FIG. 6 is consistent with FIG. 5. The difference is that the long code mask used is CommonMask (i), not Mask (i, N).

Mask (i, N) and CommonMask (i) of FIG. 5 and FIG. 6 are designed to be interconnected as described above, and the long code generator used by BS and MS is synchronized in time. Assume

FIG. 7 is a view for explaining the relationship between the scrambler and the descrambler as shown in FIGS. 5 and 6. When the system is initially designed, Mask (i, N) is used by using CommonMask (i) and slot length information N. FIG. Is determined.

In more detail,

First, CommonMask (i) defines not to overlap the long code masks used by other transport channels of the designed system. At this time, the value of CommonMask (i) may be different or the same value depending on i.

When the BS uses CommonMask (i) as a long code mask, Mask (i, which causes the output of the scrambler to occur after the (N + Δ) slot time from the present time, occurs at the present time. N).

That is, if each long code mask is designed according to the above scheme, when the BS uses Mask (i, N) as a long code mask, the slot time is (N + Δ). When the MS descrambles, it can be descrambled using CommonMask (i). Δ is any fixed constant that takes into account the hardware design.                     

As described above, the present invention can be applied regardless of the number of F-SPDCCH input bits, the use of the first and second CRC generators 100 and 101, the insertion position of the scrambler, and the like.

First Embodiment

In the first embodiment of the present invention, according to the 'basic configuration', the contents of the 21-bit transition register A into the 21-bit transition register B at the center of the switch between the BS and the Z4 and Z5 of the MS in one slot. An example of the case used for copying. Assume that Δ = 0 in the first embodiment of the present invention.

8 is a view illustrating operations of the BS and the MS for explaining the first embodiment of the present invention. At this time, it is assumed that there is no transmission delay between the transmitting and receiving end.

First, in terms of the BS, if the F-SPDCCH having 1, 2 or 4 slot transmission lengths are transmitted at the start of slot 2, they are scrambling by the contents of the transition register B of the time interval t1. .

Similarly, if F-SPDCCHs having 1, 2 or 4 slot transmission lengths are transmitted at the beginning of slot 5, they are scrambling by the contents of transition register B in the t7 time interval. In this case, the long code mask used is Mask (i, N).

At this time, on the MS side, the descrambling of the F-SPDCCH having one slot transmission length received in the slot 2 time interval is performed by the contents of the transition register B of the t3 time interval.                     

In addition, the descrambling of the F-SPDCCH having the two slot transmission lengths received in the time intervals of the slot 2 and the slot 3 is performed by the contents of the transition register B of the time interval t5.

The descrambling of the F-SPDCCH having the 4-slot transmission length received in the slot 2 to slot 5 is performed by the contents of the transition register B in the t9 time interval.

Similarly, the descrambling of the F-SPDCCH having one slot transmission length received in the time interval of slot 4 is made by the contents of the transition register B in the time interval t7.

That is, the output of the scrambler generated by the BS by Mask (i, N) at a specific time is the output value of the scrambler that will occur after N slot time from the specific time when the BS uses CommonMask (i).

As a result, the MS can use CommonMask (i) to descramble the received F-SPDCCH after the N slot time length.

That is, in FIG. 8, the 2-slot F-SPDCCH in which the scrambling is performed by the contents of the transition register B in the t1 time interval in the BS is decoded by the contents of the transition register B in the t5 interval after 2 slots in the MS. Scrambled.

Table 1 is one example of long code masks of 42 bits for a system operating as the first embodiment of the present invention. At this time, it is assumed that CommonMask (i) has the same value for all i.                     

TABLE 1

Second Embodiment

According to the second embodiment of the present invention, a switch between Z4 and Z5 of the BS and the MS is used to copy the contents of the 21-bit transition register A to the 21-bit transition register B at the start of one slot. Here is an example. In the second embodiment, it is assumed that Δ = 1.

9 is a diagram illustrating operations of the BS and the MS. At this time, it is assumed that there is no transmission delay between the transmitting and receiving end.

First, in terms of the BS, if the F-SPDCCH having a transmission length of 1, 2 or 4 slots is transmitted at the beginning of the slot 2, they are scrambling by the contents of the transition register B of the time interval t1.

Similarly, if F-SPDCCHs having 1, 2 or 4 slot transmission lengths are transmitted at the beginning of slot 5, they are scrambling by the contents of transition register B in the t4 time interval. The long code mask used at this time is Mask (i, N).

In terms of the MS, descrambling of the F-SPDCCH having the transmission length of one slot received in the slot 2 time interval is performed by the contents of the transition register B of the t3 time interval.                     

In addition, the descrambling of the F-SPDCCH having the two slot transmission lengths received in the time intervals of the slot 2 and the slot 3 is performed by the contents of the transition register B of the time interval t4.

In addition, the descrambling of the F-SPDCC having the 4 slot transmission length received in the time interval of slots 2 to 5 is performed by the contents of the transition register B of the time interval t6.

Similarly, the descrambling of the F-SPDCCH having one slot transmission length received in the time interval of slot 4 is made by the contents of the transition register B in the time interval t5.

That is, the output of the scrambler generated by the BS by Mask (i, N) at a specific time is the output of the scrambler that will occur after (N + 1) slot time from the specific time when the BS uses CommonMask (i). Values.

As a result, the MS can use CommonMask (i) to descramble the received F-SPDCCH after the N slot time length.

For example, in FIG. 9, a 2-slot long F-SPDCCH in which a scrambling is performed by the contents of the transition register B in the t1 time interval in the BS is decoded by the contents of the transition register B in the t4 interval after 3 slot time lengths in the MS. Scrambled.

Table 2 shows one example of 42-bit long code masks for a system operating like the first embodiment of the present invention. At this time, it is assumed that CommonMask (i) has the same value for all i.                     

TABLE 2

Third Embodiment

As described in the first and second embodiments, the operation timings of the switches between Z4 and Z5 on the BS side and the MS side do not necessarily coincide.

In the third embodiment of the present invention, a switch between Z4 and Z5 on the BS side is used to copy the contents of the 21-bit transition register A to the 21-bit transition register B at a specific center point in one slot, and Z4 and Z5 on the MS side. The switch between is an example of the case used to copy the contents of the 21 bit transition register A into the 21 bit transition register B at the start of one slot. Assume that Δ = 0.5 in the third embodiment.

10 is a diagram illustrating an operation of a BS and an MS, and assumes that there is no transmission delay between a transmitting and receiving end.

First, in terms of the BS, if the F-SPDCCH having a transmission length of 1, 2 or 4 slots is transmitted at the beginning of the slot 2, they are scrambling by the contents of the transition register B of the time interval t1. Similarly, if F-SPDCCHs having 1, 2 or 4 slot transmission lengths are transmitted at the beginning of slot 5, they are scrambling by the contents of transition register B in the t7 time interval. In this case, the long code mask used is Mask (i, N).                     

In terms of the MS, descrambling of the F-SPDCCH having a 1-slot transmission length received in the slot 2 time interval is performed by the contents of the transition register B of the t4 time interval.

In addition, the descrambling of the F-SPDCCH having the two slot transmission lengths received in the time intervals of the slot 2 and the slot 3 is performed by the contents of the transition register B of the t6 time interval.

In addition, the descrambling of the F-SPDCCH having the 4-slot transmission length received in the time interval of slots 2 to 5 is performed by the contents of the transition register B of the time interval t10.

In addition, the descrambling of the F-SPDCCH having one slot transmission length received in the time interval of slot 4 is performed by the contents of the transition register B of the t8 time interval.

That is, the output of the scrambler generated by the BS by Mask (i, N) at a specific time is the output of the scrambler that will occur after (N + 0.5) slot time from the specific time when the BS uses CommonMask (i). Values. As a result, the MS can use CommonMask (i) to descramble the received F-SPDCCH after the N slot time length.

For example, in FIG. 10, a 2-slot long F-SPDCCH in which the scrambling is performed by the contents of the transition register B in the t1 time interval in the BS is determined by the contents of the transition register B in the t6 interval after 2.5 slots in the MS. Scrambled.

Table 3 shows an example of 42 bit long code masks for a system operating as the third embodiment of the present invention. At this time, it is assumed that CommonMask (i) has the same value for all i.

TABLE 3

If the scrambler is designed according to the present invention, the time delay of the scrambler is considered between the transmission and reception, so that the receiving end MS does not need to store the output value of the scrambler for several slot lengths to compensate for the time delay. That is, the hardware complexity is reduced.

Claims (10)

A method for scrambling arbitrary data having a variable length transmission format on a transmitting side, Scrambling any data of the variable length transmission format using mask information formed according to the variable length transmission format, And the mask information includes an output bit identical to a descrambler to be used at the time of descrambling the data at a receiving side. The method of claim 1, The mask information is formed using a common long code mask and the information on the variable length transmission format scrambling method of physical channel transmission format. 3. The method of claim 2, wherein the receiving side descrambles using the common long code mask. The method of claim 2, And a value of the scrambled data is an output value of a scrambler after a predetermined slot time after the transmitting side uses the common long code mask. The method of claim 2, wherein the common long code mask has a format of: Long code mask kind MSB ·········· LSB CommonMask (i) 110001100110110000000000000000000000000000 Mask (i, 1) 001100110110110011100001001100000100101000 Mask (i, 2) 000110000110101011000110000110011000100101 Mask (i, 4) 010110010100111101111000011110110010000011 The physical channel transport format scrambling method, characterized in that consisting of. The method of claim 2, wherein the common long code mask has a format of: Long code mask kind MSB ·········· LSB CommonMask (i) 110001100110110000000000000000000000000000 Mask (i, 1) 000110000110101011000110000110011000100101 Mask (i, 2) 100000100011100001111111001011111111001110 Mask (i, 4) 101000011111110010101001100101001111011010 The physical channel transport format scrambling method, characterized in that consisting of. The method of claim 2, wherein the common long code mask has a format of: Long code mask kind MSB ·········· LSB CommonMask (i) 110001100110110000000000000000000000000000 Mask (i, 1) 101011111011111010011010000110101010000100 Mask (i, 2) 111011101100101101011101010101100001011111 Mask (i, 4) 101001010000000100000001011011110110000010 The physical channel transport format scrambling method, characterized in that consisting of. The method of claim 1, wherein the transmitting side, A first periodic addition check block for adding an error detection code to the data, a second periodic addition check block, a tail bit addition block for adding tail bits for indicating a final state of an encoder encoding the data to the data; A convolutional encoder for encoding the tail bit-added data into a convolutional code, a symbol repetition block for symbol repetition according to a length of a slot for transmitting the encoded bits, and puncturing the symbol repeated bits A puncturing block and a block interleaver for interleaving the punctured bits, and outputting data or output bits from any one of the modulation blocks modulating according to the transmission-side modulation scheme, or a first periodic addition check block. Scrambling to the input data of the physical channel transmission format Crambling method. The method of claim 2, wherein the transmitting side, A long code generator for generating a long code according to the mask information, a scrambling bit extractor for extracting and outputting at least some bits of bits output from the long code generator, and a output from the scrambling bit extractor A first register for storing bits by a set bit, a second register for copying output bits of the first register, and first and second registers configured to set output bits of the first register in one slot. And a switch for copying to the second register at a specific time. The method of claim 3, wherein the receiving side, A long code generator for generating a long code according to the common long code mask, a scrambling bit extractor for extracting and outputting at least some bits of bits output from the long code generator, and in the scrambling bit extractor A slot configured between a first register for storing the output bit by a set bit, a second register for copying an output bit of the first register, and the first and second registers to output an output bit of the first register. And a switch for copying to the second register at a specific time set therein.

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