KR100876878B1 - New DRAM cell structure - Google Patents

Abstract

The present invention discloses a new DRAM cell structure using a switched storage node contact structure. The disclosed DRAM cell structure includes a semiconductor substrate having a field region and an active region, an isolation layer formed in the field region of the semiconductor substrate, several word lines formed on the substrate active region and the isolation layer, and the word A source / drain region formed in the substrate surface on both sides of the line, a first interlayer dielectric layer formed on the entire region of the substrate to cover the word line, a bit line formed in contact with the drain region on the first interlayer dielectric layer, A second interlayer dielectric layer formed on the first interlayer dielectric layer to cover the bit line, a third interlayer dielectric layer formed on the second interlayer dielectric layer, and a source region in the first, second and third interlayer dielectric layers; The formed storage node contacts and the storage node contact switches in a pattern form formed on the second interlayer insulating layers on both sides of the storage node contacts. And, a third capacitor is formed so that the contact with the storage node contacts in the interlayer dielectric film. According to the present invention, data is generated by increasing a cell leakage current by forming a switching element around a storage node contact, and depleting polysilicon used as a storage node contact by applying a negative bias to the depletion gate during a data storage operation. The deterioration of memory characteristics can be prevented.

Description

New DRAM cell structure

1 is a graph showing the leakage current limit according to the charge capacity value by DRAM generation.

2 is a cross-sectional view showing a conventional DRAM structure.

3 is a cross-sectional view showing a new DRAM cell structure according to an embodiment of the present invention.

4A and 4B are diagrams for explaining a DRAM cell operating principle according to the present invention;

5 is a graph showing a simulation result of operating characteristics of a DRAM cell according to the present invention;

6A through 6E are cross-sectional views of processes for describing a DRAM cell manufacturing method according to an exemplary embodiment of the present invention.

7 is a cross-sectional view showing a DRAM cell structure according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

31 semiconductor substrate 32 device isolation film

33: word line 34: first interlayer insulating film

35 bit line 36 second interlayer insulating film

37: storage node contact switch 38: the third interlayer insulating film

39: storage node contact 40: sacrificial oxide film

41: storage node 42: dielectric film

43: plate node 44: capacitor

The present invention relates to a DRAM, and more particularly, to a new DRAM structure in which a switch device is installed around a storage node contact to reduce cell leakage current.

Recently, with the development of notebook computers and personal digital assistants (PDAs), the demand for low power, low voltage, and high speed memory is increasing. As a result, the minimum pitch size of the device gradually decreases, and in the case of DRAM cell transistors, it is inevitable to reduce the channel length to 0.1 μm or less.

Here, the leakage current is the most concern as the channel length of the MOSFET becomes smaller. That is, as the channel length becomes shorter, the potential barrier between the source and the channel is reduced due to the strong electric field in the drain, so that the current between the source and the drain is not even when the gate is not turned on. Will flow. This is called a so-called drain induced barrier lowering (DIBL) phenomenon.

On the other hand, when the doping concentration of the substrate is increased to suppress DIBL, the junction leakage current increases this time. Increasing leakage current poses a problem of increasing power consumption, but more importantly, it can be a major cause of deterioration of retention characteristics in the case of DRAM.                         

1 is a graph showing a limit of leakage current according to a capacitor charge capacity value of each DRAM generation.

As shown, it is expected that a charging capacity of 2fA / cell in a 1G DRAM cell and 2.5fA / cell in a 16G DRAM cell will be required.

2 is a cross-sectional view showing a conventional DRAM. In such a DRAM structure, the most problematic problem with the increase in density is that the DRAM memory capacity characteristic is degraded due to the cell leakage current.

Here, the cell leakage current includes a capacitor leakage current due to a potential difference between a plate electrode and a storage electrode, a junction leakage current in a switching transistor due to a potential difference between a storage electrode and a substrate, and a drain and source due to a potential difference between a storage electrode and a bit line. Liver current I _DS and the like.

In FIG. 2, reference numeral 1 denotes a semiconductor substrate, 2 denotes a device isolation layer, 3 denotes a word line, 4 denotes a first interlayer insulating layer, 5 denotes a bit line, 6 denotes a second interlayer insulating layer, and 7 denotes a polyplug in contact with a storage node. Hereinafter referred to as " storage node contact "), 8 is an oxide film, 9 is a storage node, 10 is a dielectric film, 11 is a plate node, and 20 is a capacitor.

Accordingly, an object of the present invention is to provide a new DRAM cell structure capable of preventing deterioration of memory capacity characteristics due to leakage current.

In order to achieve the above object, the present invention is a semiconductor substrate having a field region and an active region; An isolation layer formed in the field region of the semiconductor substrate; Several word lines formed on the substrate active region and the isolation layer; Source / drain regions formed in the substrate surface on both sides of the word line; A first interlayer insulating film formed over the entire area of the substrate to cover the word line; A bit line formed on the first interlayer insulating layer to contact the drain region; A second interlayer insulating film formed on the first interlayer insulating film to cover the bit line; A third interlayer insulating film formed on the second interlayer insulating film; A storage node contact formed to contact the source region in the first, second and third interlayer insulating films; A storage node contact switch in a pattern form formed on the second interlayer insulating layer on both sides of the storage node contact; And a capacitor formed on the third interlayer insulating layer to be in contact with the storage node contact.

The storage node contact switch may include any one of doped amorphous silicon, doped polycrystalline silicon, doped single crystal silicon, or doped silicon germanium (Si _X Ge _1-X ).

The storage node contact switch functions to deplete the storage node contact material by applying a predetermined voltage during a data storage operation, thereby suppressing a cell leakage current, and to apply a predetermined voltage during a data read / write operation. By accumulating the storage node contact material, it functions to improve the storage node contact resistance.

According to the present invention, data is generated by increasing a cell leakage current by forming a switching element around a storage node contact, and depleting polysilicon used as a storage node contact by applying a negative bias to the depletion gate during a data storage operation. The deterioration of memory characteristics can be prevented.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view illustrating a new DRAM cell structure according to an embodiment of the present invention. As shown, the DRAM cell of the present invention has a structure in which a switch element 37 (hereinafter referred to as a "storage node contact switch") capable of depleting storage node contact material is formed around the storage node contact 39. There is a characteristic.

That is, in the DRAM cell of the present invention, a second interlayer insulating layer 36 is formed to cover a substrate product on which the bit line 35 is formed to be in contact with the drain region, and a storage node contact switch ( 37, a third interlayer insulating film 38 is formed to cover the third interlayer insulating film 38, and the third, second and first interlayer insulating films 38, 36, and 34 are in contact with a source region (not shown). The storage node contact 39 is formed to be surrounded by the switch 37, and the capacitor 44 is formed on the third interlayer insulating layer 38 to contact the storage node contact 39.                     

In FIG. 3, reference numeral 31 denotes a semiconductor substrate, 32 a device isolation film, 33 a word line, 40 a sacrificial oxide film, 41 a storage node, 42 a dielectric film, and 43 a plate node.

The storage node contact switch 37 may be formed of any one of doped amorphous silicon, doped polycrystalline silicon, doped single crystal silicon, or doped silicon germanium (Si _X Ge _1-X ).

The storage node contact switch 37 functions to deplete the storage node contact material by applying a predetermined voltage during a data storage operation so that the cell leakage current is suppressed.

In addition, the storage node contact switch 37 functions to accumulate storage node contact materials by applying a predetermined voltage during data read / write operations to improve storage node contact resistance.

In the above, the control capability of the storage node contact switch 37 may be controlled according to the doping level in the storage node contact material.

In detail, considering the storage node contact in the conventional DRAM as the channel of the transistor, and the storage node contact switch in the DRAM according to the present invention as the gate, the DRAM cell of the present invention is a conventional N-channel junction field effect. It can be considered to operate in the same manner as the transistor JFET.

That is, as shown in FIG. 4A, when a negative bias is applied to the gate Vg, the channel under the gate is depleted, and as shown in the voltage-current characteristic as shown in FIG. 4B, the drain ( The current Id from Vd) to the source (Vs = 0V) is cut off.

5 is a graph showing the results of simulating the operating characteristics of the DRAM cell according to the present invention. In the simulation, it is assumed that the bias condition is the retention mode, the word line Vg is 0V, the body bias Vb is -0.8V, and the potential difference Vd between the storage electrode and the bit line is 3V.

In FIG. 5, V (dgate) is a voltage applied to the storage node contact switch. When lightly doped N-type polysilicon is used as the storage node contact, leakage current is reduced by 60% due to depletion at about -1V. It can be seen that the degree decreases.

As a result, the DRAM cell of the present invention allows the storage node contact to be depleted by applying a negative bias to the storage node contact switch in the data storage mode while maintaining the high density cell structure, thereby suppressing the cell leakage current to improve the data storage characteristics. You can.

In addition, the DRAM cell of the present invention may also reduce the storage node contact resistance by applying a predetermined voltage to the storage node contact switch in a data read / write mode to allow current to accumulate.

Hereinafter, a method of manufacturing a DRAM cell according to the present invention as described above will be described.

6A to 6E are cross-sectional views of processes for describing a DRAM cell manufacturing method according to the present invention. Here, the same parts as in Fig. 3 are designated by the same reference numerals.

Referring to FIG. 6A, after the device isolation layer 32 is formed in a field region of the semiconductor substrate 31 according to a shallow trench isolation (STI) process, ion implantation of impurities of a predetermined conductivity type, for example, a P-type impurity is performed. This forms a P-well (not shown) in the substrate 31.

Next, several word lines 33 are formed on the substrate active region and the device isolation film 32 according to a known process. Then, a source / drain region (not shown) is formed in the surface of the substrate active region on both sides of the word line 33 by an impurity ion implantation process. Subsequently, a first interlayer insulating film 34 is formed to cover the substrate resultant.

Then, contact plugs are formed on the source / drain regions between the word lines 33 according to a known process.

Referring to FIG. 6B, the first interlayer dielectric layer 34 may be etched to expose a contact plug formed on the drain region or the drain region, and then contact the drain region through conductive layer deposition and patterning. 35). Then, a second interlayer insulating film 36 is formed on the entire area of the substrate 31 to cover the bit line 35.

Referring to FIG. 6C, a conductive film made of any one of doped amorphous silicon, doped polycrystalline silicon, doped single crystal silicon, or doped silicon germanium (Si _X Ge _1-X ) may be formed on the second interlayer insulating layer 36. After deposition, it is patterned to form the storage node contact switch 37 in the form of a pattern that is subsequently floated around the area where the storage node contact is to be formed.

Although not shown, the storage node contact switch 37 may be formed in the form of a spacer rather than a simple pattern. In this case, a spacer-type switch is formed by depositing a storage node contact material after deposition of an insulating film, and then blanket etching the storage node contact material.

Referring to FIG. 6D, a third interlayer insulating layer 38 is formed on the second interlayer insulating layer 36 to cover the storage node contact switch 37. Then, the third, second and first interlayer insulating films 38, 36, and 34 are etched to form contact holes for exposing contact plugs formed on the source region or the source region, for example, and then in the contact holes. A conductive node, preferably a silicon film doped with impurities at a predetermined level, is embedded to form a storage node contact 39.

Referring to FIG. 6E, after the sacrificial oxide layer 40 is formed on the resultant, the sacrificial oxide layer 40 is etched to form a trench for exposing the storage node contact 39. Then, after the storage node 41 is formed on the trench surface, the dielectric film 42 and the plate node 43 are sequentially formed to form the capacitor 44. As a result, the present invention provides a DRAM cell structure. Complete

7 is a cross-sectional view illustrating a DRAM cell structure according to another embodiment of the present invention. According to this embodiment, the storage node contact switch 37 is formed before the bit line is formed, unlike the above-described embodiment is formed after the bit line is formed. Form.

In this case as well, by applying a predetermined voltage to the storage node contact switch during data storage and read / write operations, it is possible to deplete or accumulate the storage node contact material, thereby reducing the leakage current.

As described above, according to the present invention, by applying a negative bias to the switch element during data storage while providing a switch element around the storage node contact, it is possible to prevent deterioration of data storage capability characteristics due to an increase in cell leakage current. In addition, high performance and low power DRAM can be provided while maintaining high density.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (4)

A semiconductor substrate having a field region and an active region; An isolation layer formed in the field region of the semiconductor substrate; Several word lines formed on the substrate active region and the isolation layer; Source / drain regions formed in the substrate surface on both sides of the word line; A first interlayer insulating film formed over the entire area of the substrate to cover the word line; A bit line formed on the first interlayer insulating layer to contact the drain region; A second interlayer insulating film formed on the first interlayer insulating film to cover the bit line; A third interlayer insulating film formed on the second interlayer insulating film; A storage node contact formed to contact the source region in the first, second and third interlayer insulating films; A storage node contact switch in a pattern form formed on the second interlayer insulating layer on both sides of the storage node contact; And And a capacitor formed on the third interlayer insulating layer to be in contact with the storage node contact. The method of claim 1, wherein the storage node contact switch is A DRAM cell structure comprising any one selected from the group consisting of doped amorphous silicon, doped polycrystalline silicon, doped single crystal silicon, and doped silicon germanium (Si _X Ge _1-X ). The method of claim 1, wherein the storage node contact switch is A DRAM cell structure, characterized in that, during a data storage operation, the cell leakage current is suppressed by depleting the storage node contact material by applying a predetermined voltage. The method of claim 1, wherein the storage node contact switch is And a data storage device, wherein the DRAM cell structure accumulates a storage node contact material by applying a predetermined voltage during a data read / write operation, thereby improving the storage node contact resistance.

Images