KR100872404B1 - Wafer bonding packaging method - Google Patents

Abstract

TECHNICAL FIELD The present invention relates to the field of packaging technology at the wafer level, and more particularly, to a wafer bonding packaging method using a lid wafer bonded on top of a device wafer. It is an object of the present invention to provide a wafer bonding packaging method capable of manufacturing a lid wafer for wafer bonding with a simple interconnection process while eliminating the introduction of a deep reactive ion etching process of an SOI substrate and silicon. According to an aspect of the invention, the step of forming a first etch stop layer on the front and rear of the lid silicon wafer; Patterning the first etch stop layer to form a cavity etch window on a rear surface of the lid silicon wafer, and forming a via hole etch window on the front surface of the lid silicon wafer, wherein the cavity is overlapped with the cavity etch window; Wet etching the lid silicon wafer exposed by the cavity etching window and the via hole etching window to form a cavity and a via hole, wherein a silicon thickness of a predetermined thickness remains between the cavity and the via hole; Removing the first etch stop layer pattern remaining on the back side of the lid silicon wafer; Forming a second etch stop layer on a back surface of the lid silicon wafer; Forming a through hole by additionally etching the via hole to expose the second etch stop layer; Removing the first etch stop layer pattern remaining on the entire surface of the lid silicon wafer; Forming a via interconnection in front of the lid silicon wafer; Removing the second etch stop layer; Forming a cavity interconnection in contact with said via interconnection on a backside of said lid silicon wafer; Forming a bond pad on the cavity interconnection; And bonding the lid silicon wafer and the device wafer on which the device is formed using the bonding pads.

Wafer Bonding, Packaging, Lid Wafers, Interconnect, Cavity, Anti-Etch

Description

Wafer Bonding Packaging Method {WAFER BONDING PACKAGING METHOD}

1 is a cross-sectional view of a package manufactured according to a conventional through hole interconnect scheme.

2A-2M are cross-sectional views illustrating a wafer bonding packaging process in accordance with one embodiment of the present invention.

3 is a view showing a state in which primary packaging is completed.

* Explanation of symbols on the main parts of the drawing

200: lid silicon wafer

300: wafer for device

TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and more particularly to the field of packaging technology at the wafer level, and more particularly to a wafer bonding packaging method using a lid wafer bonded on top of a device wafer.

The packaging of semiconductor devices by wafer bonding has the advantage of significantly lowering the packaging cost as a batch and mass production method in which packaging of hundreds to thousands of devices is simultaneously performed. Wafer-level packaging using wafer bonding can be classified into two types: general semiconductor devices such as memory, and sensors / microelectromechanical systems (MEMS) having a sensor or a mechanical drive on the surface of the device.

In the general IC field, wafer bonding technology is mainly used for stacking wafers in three dimensions, and is mainly used for fabricating a composite chip that increases integration density or integrates heterogeneous ICs. In the field of sensors / MEMS, on the other hand, wafer bonding technology is mainly used to protect mechanically vulnerable structures such as diaphragms and devices sensitive to contamination from the external environment such as sensors. Therefore, there is often a need for additional means for providing sealing of the device.

In packaging by wafer bonding, means for connecting the electrodes for driving the device and extracting the reaction from the bonding surface of the bonded wafer to the opposite side of the bonding wafer are commonly required for general ICs and sensors / MEMS. In general ICs, the number of electrodes required is large, whereas in sensors / MEMS, the number of electrodes required is often small.

A method for connecting interconnects from the bonding surface of the wafer to the opposite side of the package wafer by wafer bonding, forming via holes penetrating the wafer by deep reactive ion etching, and forming the via holes into copper (Cu). Filling with a conductive metal such as) to achieve electrical connection is the most widely used. This method has the advantage that the via hole occupies a small area and further reduces the thickness of the packaging wafer by additionally cutting the back side of the wafer after bonding the wafer. On the other hand, in general, the deep reactive ion etching process used to form the via hole is expensive, and the copper filling process, which is usually performed by plating, also has a disadvantage of requiring a lot of time and cost.

1 is a cross-sectional view of a package manufactured according to a conventional through hole interconnection scheme (see US Pat. No. 6,429,511).

This through-hole interconnection method is a method of simultaneously providing the formation and the hermetic sealing of the feed-through metal layer without using deep reactive ion etching and the Cu filling method. Referring to FIG. A structure suitable for a wafer level packaging device for an optical device, in particular a photoelectric integrated circuit, having a metal layer 7, a wire bonding pad 4, and a solder material 8 for bonding with a device wafer (not shown). (optoelectronic integrated circuit) A semiconductor lid wafer is shown used as a cap of a subassembly.

Using a silicon on insulator (SOI) wafer having a buried silicon oxide film 2 in the middle layer of the silicon wafer 1, one or a plurality of front through holes corresponding to each other in any order at the front and rear surfaces of the wafer 6 ) And the back through hole 5 are formed using anisotropic wet etching of silicon. At this time, the buried silicon oxide film 2 of the SOI wafer acts as an etch stop layer during the etching of the back through holes 5 and the front through holes 6, and the back through holes 5 and the front through holes are formed on the front and back surfaces of the wafer. After (6) is formed, the buried silicon oxide film 2 in the back through hole 5 region is removed, and both sides of the wafer communicate with each other through the back through hole 5 and the front through hole 6.

Then, photoresist is applied to the entire surface area including the back through hole 5 and the front through hole 6 of the wafer, and then patterned by a photo transfer process to define a region where the feed through metal layer 7 is to be formed. The feedthrough metal layer 7 is formed in the region by the electroplating method. At this time, the thickness of the feed-through metal layer 7 is set to be thick enough so that the through-holes communicating with the front and rear surfaces of the wafer can be completely filled. Unexplained reference numeral 3 denotes a silicon nitride film for selectively exposing a specific region of the feedthrough metal layer 7.

The conventional through-hole interconnection method as described above has an advantage of using anisotropic wet etching of silicon without using via hole formation by deep reactive ion etching. On the other hand, the conventional through-hole interconnection method uses a SOI wafer that is more expensive than a general silicon wafer, and also has a deep reactivity since the formation of the interconnection in the state where the through-hole is formed before and after the wafer is complicated. Excluding the ion etching has a disadvantage that the process cost rises above the expected process cost reduction is accompanied.

The present invention has been proposed to solve the above problems of the prior art, a wafer capable of producing a wafer bonding lid wafer with a simple interconnection process while eliminating the introduction of a deep reactive ion etching process of an SOI substrate and silicon. Its purpose is to provide a bonding packaging method.

It is also an object of the present invention to provide a wafer bonding packaging method capable of sealing an element by using the interconnection of the lid wafer and the element wafer.

According to an aspect of the present invention for achieving the above object, the step of forming a first etch stop layer on the front and rear of the lid silicon wafer; Patterning the first etch stop layer to form a cavity etch window on a rear surface of the lid silicon wafer, and forming a via hole etch window on the front surface of the lid silicon wafer, the overlapped portion of the cavity etch window; Wet etching the lid silicon wafer exposed by the cavity etching window and the via hole etching window to form a cavity and a via hole, wherein a silicon thickness of a predetermined thickness remains between the cavity and the via hole; Removing the first etch stop layer pattern remaining on the back side of the lid silicon wafer; Forming a second etch stop layer on a back surface of the lid silicon wafer; Forming a through hole by additionally etching the via hole to expose the second etch stop layer; Removing the first etch stop layer pattern remaining on the entire surface of the lid silicon wafer; Forming a via interconnection in front of the lid silicon wafer; Removing the second etch stop layer; Forming a cavity interconnection in contact with said via interconnection on a backside of said lid silicon wafer; Forming a bond pad on the cavity interconnection; And bonding the lid silicon wafer and the device wafer on which the device is formed using the bonding pads.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

2A to 2M are cross-sectional views illustrating a wafer bonding packaging process according to an embodiment of the present invention.

In the wafer bonding packaging process according to the present embodiment, first, as shown in FIG. 2A, an etch stop layer 20 is deposited on the front and rear surfaces of the silicon wafer 200 having the (100) crystal plane, and the silicon wafer 200 The photoresist 21 is applied only to the front portion. Here, it is preferable to use a silicon oxide film, a silicon nitride film, a silicon oxide film / silicon nitride film laminated film as the etch stop film 20, and to deposit by LPCVD (Low Pressure Chemical Vapor Deposition) method.

Subsequently, as illustrated in FIG. 2B, an exposure and development process using a photomask is performed to form a photoresist pattern 21A for selectively exposing the cavity formation region.

Next, as shown in FIG. 2C, the etch stop layer 20 of the exposed cavity forming region is removed by dry or wet etching using the photoresist pattern 21A as an etching mask to form the cavity etching window 22.

Subsequently, as shown in FIG. 2D, the photoresist pattern 21A is removed, and a photo transfer process and an etching process are performed on the rear surface of the silicon wafer 200 in the same manner as the cavity etching window 22 forming process. The via hole etching window 24 is formed. Reference numeral '20A' denotes an etch barrier pattern for defining a cavity formation region, '20B' denotes an etch barrier pattern for defining a via hole formation region, and '23' denotes a photoresist pattern for defining a via hole formation region. . Here, the cavity etching window 22 and the via hole etching window 24 are each preferably formed in a quadrangular shape, and the four sides thereof are preferably formed to be aligned in parallel with the [110] crystal direction of the silicon wafer 200. Do.

Subsequently, as shown in FIG. 2E, the photoresist pattern 23 is removed, and the silicon wafer 200 is exposed using a silicon anisotropic etching solution such as potassium hydroxide (KOH) or tetramethyl ammonium hydroxide (TMAH). Etch 200 to a predetermined depth. At this time, the silicon of the predetermined thickness is left so that the cavity 25 and the via hole 26 do not penetrate each other. The depths of the cavity 25 and the via hole 26 may be set equal to each other, or may be set different from each other. For example, when the depths of the cavity 25 and the via hole 26 are each set to a 60 µm target, it is appropriate to set the thickness of the remaining silicon to about 30 µm. In the silicon substrate having the (100) crystal plane, the etching pattern aligned with the [110] crystal direction is automatically determined by the width of the wide side etching window according to the inherent characteristic of the anisotropic etching. Therefore, even when the cavity 25 and the via hole 26 are simultaneously etched, the size of the via hole etching window 24 may be properly designed to form the via hole 26 having a depth lower than the etching depth of the cavity 25. On the other hand, in order to form the via hole 26 deeper than the cavity 25, the upper and lower portions of the silicon wafer 200 must be etched separately, and for this purpose, a separate process is required to prevent additional etching on the opposite side of the wafer. Do. The larger the opening area of the via hole 26, the smaller the number of via holes 26 that can be disposed so as not to overlap each other in the same area. Therefore, the opening area of the via hole 26 is appropriately adjusted according to the number of via holes 26 required. It is desirable to adjust.

Subsequently, as shown in FIG. 2F, the etch stop layer pattern 20A on the back surface of the silicon wafer 200 on which the cavity 25 is formed is removed. In this case, dry etching or wet etching may be performed, and in some cases, the etching process may be performed in a state in which the etch stop layer pattern 20B on the entire surface of the silicon wafer 200 is protected with a photoresist.

Subsequently, as shown in FIG. 2G, an etch stop layer 27 is deposited on the back surface of the silicon wafer 200 on which the cavity 25 is formed. Here, it is preferable to use a silicon oxide film, a silicon nitride film, a silicon oxide film / silicon nitride film laminated film as the etch stop layer 27, and to deposit it on the surface of the silicon wafer 200 by PECVD (Plasma Enhanced Chemical Vapor Deposition) method. It is desirable to.

Next, as illustrated in FIG. 2H, the silicon wafer 200 is etched in a silicon anisotropic etching solution such as KOH or TMAH to additionally etch the via hole 26 to expose the etch stop layer 27 on the bottom of the via hole 26. do. In this case, dry etching may be performed instead of wet etching in some cases, and the etching target is adjusted so that the bottom of the via hole 26 has a size of about 20 μm. In either wet etching or dry etching, the bottom surface of the via hole 26 is supported only by the etch stop layer 27. Therefore, the thickness of the anti-etching layer 27 should have a thickness that serves as an etch stop during the etching process and has sufficient mechanical strength to withstand mechanical breakage after the etching process. Preferably a thickness of at least 0.5 μm is required.

Subsequently, as shown in FIG. 2I, the etch stop layer pattern 20B remaining on the entire surface of the silicon wafer 200 on which the via holes 26 are formed is removed. In this case, dry etching or wet etching may be performed to remove the etch stop layer pattern 20B, and the removal process may be performed in a state filled with photoresist to prevent additional etching or damage inside the via hole 26. In some cases, the etch stop layer 27 on the back surface of the silicon wafer 200 may be protected with a photoresist.

Subsequently, as shown in FIG. 2J, a via interconnection 28 is formed on the entire surface of the silicon wafer 200 on which the via holes 26 are formed. Via interconnect 28 is preferably formed through a photo transfer process and a multilayer metal film (eg, Cr / Au / Ni / Au) deposition, and lift-off and ashing processes. It is also possible to additionally plate high conductivity metals such as Au and Cu on the film. Via interconnect 28 serves to connect the electrode of the device to the outside when the lid wafer is bonded with the device wafer. Thus, via interconnection 28 contacts the opposite electrode of the lid wafer at the bottom of via hole 26 and forms over a portion of the wafer surface including the interior of via hole 26 (which simultaneously forms wire bonding pads). .

Next, as shown in FIG. 2K, the etch stop layer 27 on the back surface of the silicon wafer 200 is removed. In this case, dry etching or wet etching may be performed, and in some cases, the via interconnection 28 on the entire surface of the silicon wafer 200 may be protected with a photoresist.

Subsequently, as shown in FIG. 2L, a cavity interconnection 29 is formed on the rear surface of the silicon wafer 200 in which the cavity 25 is formed. The cavity interconnection 29 may be formed in the same manner as the via interconnection 28 described above, and the wafer surface outside the cavity 25 with the cavity interconnection 29 overlapping in and out of the cavity 25. A lower metal pad 29a is formed in the seal. The multi-layered metal film for forming the cavity interconnection 29 and the seal lower metal pad 29a is formed of at least two or more multilayered layers, and the lowermost layer is a metal material having excellent adhesion to a dielectric film coated on silicon or a silicon surface, For example, it is preferable to use a single element metal such as Ti or Cr or a mixed metal material such as TiN or TiW, and to use a precious metal such as Au which is effective for preventing oxidation of the lower metal as well as itself. Single element such as Ni, Pt, Cu, Pd, etc., which has excellent adhesiveness with the adhesive material applied on the surface protective film in the future between the adhesive layer and the surface protective film and prevents the diffusion of the adhesive material to the lower adhesive layer. Metal mixtures such as TiN, TiW, TaN and the like may be additionally applied. In more detail, the cavity interconnection 29 is a contact that contacts the via interconnection 28 opposite the wafer at the bottom of the cavity 25, a connection leading to the top of the cavity 25 along the sidewall of the cavity 25, In the area outside the cavity 25, the bonding part is in contact with the electrode pad of the device wafer during bonding with the device wafer. As described above, the cavity interconnection 29 provides a through hole interconnection that transfers the electrode of the device wafer from the backside to the frontside of the lid wafer. In addition, as described above, at the same time as the cavity interconnection 29 is formed, a seal lower metal pad required to form a sealing ring made of a solder material that protects and seals the entire area of the cavity including the device from the outside at the time of bonding with the device wafer. By simultaneously defining (29a), an additional process for the seal lower metal pad (29a) can be omitted. The seal lower metal pad 29a is implemented in a circular or rectangular rim-shaped pattern having a predetermined width connected to the outside of the cavity 25 and the cavity interconnection 29.

Subsequently, as shown in FIG. 2M, the junction pad 30 and seal rim required for electrical interconnection and wafer bonding with the device wafer on the cavity interconnection 29 and the seal lower metal pad 29a are shown. 30a is formed. The bonding pad 30 and the seal rim 30a are formed on the back surface of the silicon wafer 200 on which the cavity 25 is formed by forming a bonding pad pattern using photoresist, vacuum deposition of a metal material, and photoresist of an unwanted area. It is formed by using a lift-off process that removes or plating a single or multi-layer adhesive material subsequent to the application of the base metal required for electroplating. Preferred bonding materials are Au, Sn, Au-Sn alloys, Sn-Ag alloys, or Au / Sn multilayer metal films in which at least one layer of Au and Sn are laminated. In some cases, Ni, Pt, Cu, Cr / Ni, Ti / Ni, Cr for the purpose of preventing the adhesive material for forming the device contact pad and the sealing ring from being mixed with the metal film of the lower cavity interconnection 29. A single layer or a plurality of layers of metal films such as / Pt may be further applied on the cavity interconnection 29 and the seal lower metal pad 29a. Bond pads 30 are formed only in the flat portion of the cavity 25 outside of the cavity interconnection 29 region as shown in the drawing to provide electrical connection with the device wafer, and the machine with the device wafer thereon. It constitutes a seal rim 30a necessary for proper bonding and sealing.

The wafer bonding lid wafer 200 manufactured by the above process is bonded with the device wafer 300 by a method such as thermal reflow, thermo-compression, and ultrasonic bonding, thereby completing primary packaging. (See Figure 3). Reference numeral 60 denotes an electrode formed on the device wafer 300. For reference, the present embodiment is optimized for packaging an element wafer requiring an air cavity such as a film bulk acoustic resonator (FBAR) element, but can be applied to other types of element wafers.

Then, the bonded wafer is separated into individual chips through a sawing process, and then mounted on a PCB substrate after measurement and testing. On the other hand, the above-described lid wafer manufacturing process assumes that the mounting on the PCB using a conventional die bonding technology, when the flip-chip bonding method to be mounted on the PCB substrate via via interconnection (28) It is possible to form additional solder bumps on the pattern. The solder bumps may be formed in the same manner as the above-described bonding pad forming method, or by various methods such as a solder jet method or a stud bumping method.

When manufacturing the lid wafer and wafer bonding packaging through the above process, it was possible to exclude the trench formation process by the deep reactive ion etching of silicon during the manufacturing of the lid wafer, not only using the SOI substrate, but also through The formation of hole interconnection can be simplified. In addition, since the metal layers on the front and rear surfaces of the wafer are not used as an etch barrier during the formation of the through hole interconnection, the metal layers may be prevented from being damaged.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment, the cavity etching window forming process and the via hole etching window forming process may be reversed.

The present invention described above has the effect of simplifying the through-hole interconnection forming process required for manufacturing a wafer level packaging apparatus using wafer bonding and greatly reducing the process cost.

Claims (10)

Forming a first etch stop layer on the front and rear surfaces of the lid silicon wafer; Patterning the first etch stop layer to form a cavity etch window on a rear surface of the lid silicon wafer, and forming a via hole etch window on the front surface of the lid silicon wafer, the overlapped portion of the cavity etch window; Wet etching the lid silicon wafer exposed by the cavity etching window and the via hole etching window to form a cavity and a via hole, wherein a silicon thickness of a predetermined thickness remains between the cavity and the via hole; Removing the first etch stop layer pattern remaining on the back side of the lid silicon wafer; Forming a second etch stop layer on a back surface of the lid silicon wafer; Forming a through hole by additionally etching the via hole to expose the second etch stop layer; Removing the first etch stop layer pattern remaining on the entire surface of the lid silicon wafer; Forming a via interconnection in front of the lid silicon wafer; Removing the second etch stop layer; Forming a cavity interconnection in contact with said via interconnection on a backside of said lid silicon wafer; Forming a bond pad on the cavity interconnection; And Bonding the lid silicon wafer and the device wafer on which the device is formed using the bonding pads Wafer bonding packaging method comprising a. The method of claim 1, The second etch stop layer is a wafer bonding packaging method, characterized in that any one selected from silicon oxide film, silicon nitride film, silicon oxide film and silicon nitride film laminated film. The method of claim 2, The first etch stop layer is a wafer bonding packaging method, characterized in that any one selected from a silicon oxide film, a silicon nitride film, a silicon oxide film and a silicon nitride film laminated film. The method according to any one of claims 1 to 3, In the forming of the through hole, Wafer bonding packaging method characterized in that the via hole is additionally etched through an anisotropic silicon wet etching process. The method of claim 4, wherein And the lid silicon wafer is a silicon wafer having a (100) crystal plane, wherein the cavity etch window and the via hole etch window are aligned parallel to the [110] crystal direction. The method of claim 2, The second etch stop layer is a wafer bonding packaging method characterized in that the deposition by PECVD. The method of claim 1, The via interconnection is a wafer bonding packaging method, characterized in that each consisting of a laminated metal film of Cr, Au, Ni, Au. The method of claim 1, And the device wafer comprises a film bulk acoustic resonator (FBAR) device. The method of claim 1, In forming the via interconnection, And a wire bonding pad is formed together with the via interconnection. The method according to claim 1 or 9, In forming the cavity interconnection, Wafer bonding packaging method characterized in that the lower metal pad is formed with the cavity interconnection.

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