KR100869347B1 - HIGH PERFORMANCE VITERBI DECODER SSTRUCTURE WITH 2 DIMENSIONAL ANALOG SIGNAL PROCESSING CELL ARRAY AND MULTIPLEXER and METHOD THEREOF - Google Patents

Abstract

The present invention relates to a high efficiency Viterbi decoder structure and decoding method using a two-dimensional array and multiplexer of an analog signal processing cell. More specifically, the trellis diagram of the Viterbi decoder is implemented by an analog circuit longer than the length of the constraint length by one or two stages, and the analog signal is stored for storing an input signal. By cyclically arranging as many capacitors as the number of stages implemented in a two-dimensional array of processing cells, sequentially storing an input signal in the capacitors, and then using a multiplexer in accordance with the oldest signal order in the analog signal processing cell. It is characterized by performing a decoding by connecting to each stage of the two-dimensional array at a time.

According to the present invention, since decoding is performed in hardware, not only the decoding speed is fast, but also a path memory for decoding is unnecessary, and an A / D converter is not required, so power consumption is very small.

Viterbi decoder, analog signal processing cell, multiplexer, trellis diagram

Description

Structure and Viterbi Decoding Method of High Efficiency Viterbi Decoder by Two-Dimensional Array and Multiplexer of Analog Signal Processing Cell

1 is an exemplary trellis diagram of a general Viterbi decoder.

2A and 2B are schematic structural diagrams of a conventional digital Viterbi decoder and an analog Viterbi decoder.

3 is a schematic structural diagram of a ultra-fast Viterbi decoder with a circular two-dimensional array of conventional analog signal processing cells.

4 is a development circuit diagram of FIG. 3.

5 is a structural diagram of a high efficiency Viterbi decoder using a two-dimensional array and a multiplexer of an analog signal processing cell of the present invention.

<Description of the symbols for the main parts of the drawings>

110: analog signal processing cell 120: input signal storage position indicator

130: status indicator 140: reference signal input terminal

150: capacitor section 160: first switch section

170: second switch unit 180: analog output circuit

190: third switch unit 200: signal change detection circuit

210: pulse generator circuit 220: output stage

230: output bit determination circuit 240: decoding stage

250: multiplexer

The present invention relates to a structure of a high efficiency Viterbi decoder and a Viterbi decoding method by a two-dimensional array and multiplexer of an analog signal processing cell. More specifically, a trellis diagram of a certain length is implemented by an analog circuit, and the input signals are sequentially stored in a cyclically arranged capacitor, and the multiplexers are used to determine the angle of the analog circuit in the order of the old input signals. A high efficiency Viterbi decoder structure and decoding method using a two-dimensional array and a multiplexer of an analog signal processing cell having a structure applied to a stage.

In the present invention, the "analog signal processing cell" means a signal processing unit that implements the function of each node on the trellis diagram of the Viterbi decoder by the analog circuit.

When the signal of the data communication or the magnetic disk reader is extremely high speed, the distortion of the signal is increased, so correction of the distortion signal is very important. The Viterbi decoder has excellent signal correction efficiency because it decodes a convolutional code using an optimization technique as a technique for this distortion signal correction communication.

This decoder is a simple model of dynamic programming that is effective in finding the optimal path. It is a principle that corrects errors by determining the optimal path from the accumulated result value after several steps of calculation. FIG. 1 is an exemplary view showing an example of trellis diagram (when having 4 state values) in a general Viterbi decoder.

The Viterbi decoder uses an error value between a unique code assigned to each branch of a trellis diagram as shown in FIG. 1 and an actually input code symbol as an error. This method finds the optimal path that minimizes the cumulative error value and decodes using the code corresponding to the branch that the path passes. For example, in FIG. 1, the optimal path is decoded to 0 if it passes a branch corresponding to the solid line of the trellis diagram and to 1 if it passes a dotted line. The received signals may be different from the actual transmission signal, but since the path that has the minimum accumulated error value is found, the corrected signal may be corrected even if the information is added with noise.

The core technology of Viterbi decoder's operation is simple dynamic programming. The dynamic programming method is a method of calculating the shortest distance to the destination by installing a calculation unit that performs the following operation in each node as shown in <Equation 1>.

Where D _{k , l} is the shortest distance from cell (k, l) to the destination and d _{ij , kl} is the partial distance between cell (i, j) to cell (k, l), the branch of the trellis diagram This is given by the difference between the code symbol given to the branch and the code symbol entered. S is a set of cells around cell (i, j), and minimum (min) is a function that outputs the minimum of the listed items.

For this decoding, each node of the trellis diagram regards the difference between the unique code symbol assigned to each branch and the input code symbol (hereinafter, referred to as an error) as the distance value. As described above, a minimum value (min) operation for selecting a path having the minimum value among the accumulated symbol error values is performed.

On the other hand, the existing Viterbi decoder chips do not implement all nodes on the trellis diagram in hardware, and install only nodes corresponding to one column among them, and perform each step during the repetitive processing. We store the result of processing in path memory and use it to find the optimal path.

2A and 2B are schematic structural diagrams of a conventional digital Viterbi decoder and an analog Viterbi decoder.

Conventional digital Viterbi decoder as shown in Figure 2a has to perform the analog / digital conversion for the received analog signal, the high-speed A / D converter consumes a lot of power and can be processed by the digital circuit for the calculation of each cell There is a problem with a limited communication speed.

As a supplement to this, a method of processing using an analog circuit as shown in FIG. 2B without converting an analog input signal into digital has been disclosed. This method eliminates the power consumption by the A / D converter and improves the processing speed at each node because the analog circuit is used. However, as the digital Viterbi decoder stores the processing result in the digital memory, a digital memory for storing paths is required. In addition, since a back-tracking process is required for calculating an optimal path in memory, there is a problem in that the decoding time is not improved.

In addition, a trellis diagram of a certain length is implemented by an analog circuit as shown in FIG. 4, and the last stage of the implemented circuit is cyclically connected to the first stage as shown in FIG. An ultrafast Viterbi decoder has also been disclosed, which is a circular two-dimensional array of conventional analog signal processing cells that performs optimization processing required in a Viterbi decoder by a two-dimensional analog parallel processing scheme. This method requires a lot of auxiliary circuits because the decoding stage moves with each bit of decoding, which complicates the circuit implementation and adds noise to the signal, causing a decoding error.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a two-dimensional trellis without decoding while circulating a circuit by a cyclic connection of an analog signal processing cell, as in the conventional invention. The analog circuit is implemented by analog circuits to a certain size to have a decoding stage at a fixed position and an output stage at a fixed position, and the input signals cyclically stored in the capacitor are aligned in the order of input using a multiplexer. The present invention provides a structure of a high efficiency Viterbi decoder and a Viterbi decoding method using a two-dimensional array and a multiplexer of an analog signal processing cell.

In order to achieve the object of the present invention, the present invention configures an analog signal processing cell circuit at each node position on the trellis diagram of the Viterbi decoder to make one or two stages longer than the length of the constraining field, and circulates in the capacitor. By using the multiplexer, the stored input signals may be arranged in an input order and applied to a two-dimensional array of analog signal processing cells.

An embodiment of the present invention will be described below with reference to the drawings.

5 is a structural diagram of a high efficiency Viterbi decoder using a two-dimensional array and a multiplexer of an analog signal processing cell of the present invention.

1. Embodiment decoding method of the present invention

According to an embodiment of the present invention, a method for performing Viterbi decoding by a high efficiency Viterbi decoder using a two-dimensional array and a multiplexer of an analog signal processing cell

Receiving a plurality of code symbols corresponding to each data bit and storing the plurality of code symbols in a capacitor set at a location indicated by a storage location indicator;

Arranging capacitors in order of the oldest input signal using a multiplexer, and then applying all the capacitors to each stage at a time;

Compute the error between the unique code symbol corresponding to each branch of the trellis diagram and the code symbols stored in each stage capacitor, and at each stage the reference signal value is reduced by the code symbol error value. To propagate;

The process of blocking the flow of signal through these branches by applying a cutoff signal to all branches corresponding to logic value 1 or all branches corresponding to logic value 0 among the branches located in the decoding stage. ;

Determining a decoding result value of 1 or 0 based on whether a change occurs in an output of an output stage as a result of signal flow blocking of the decoding stage;

When the decoding of the current decoding stage is completed, moving the storage position indicator by one bit includes determining a next capacitor position to store the input signal.

2. Detailed processing in the decoding process

The process of determining a decoding result value of 1 or 0 based on whether the influence of the signal flow is blocked on the output of the output stage as a result of the signal flow cutoff of the decoding stage may include applying an electrical signal for signal blocking to the decoding stage. Comparison of decoding before and after the output signal change or skip the reference signal propagation process before applying the electrical signal for signal blocking, and replace with a predetermined threshold, and after the application of the electrical signal for signal blocking takes only the output signal and compares the threshold with the value To decode by using any one of the method of decoding by selecting a method.

In addition, the final output value of the output terminal is to select one of the method of using the maximum value of the output of all cells located in the output terminal or the method of using the average value of all the cells of the output terminal as the output value It is characterized by.

3. Analog Signal Processing Cell

The analog signal processing cell defined in the present invention means a signal processing unit that implements the function of each node on the trellis diagram of the Viterbi decoder by the analog circuit.

In order to achieve the above object, the present invention is implemented using a modified dynamic programming obtained by modifying Equation 1. That is, I _ref is a reference signal value of a large magnitude, and d _{ij, kl} is an error value between a code symbol given to a branch between cells (i, j) and (k, l) and an input code symbol, and D is _{k, l} is the error value of the accumulated code symbol from the decoding cell to the current cell position (k, l), and y _{k, l} is the error value between I _ref and D _{k, l} as shown in Equation 2 If you define it as

It can be expressed as If Equation 2 is expressed with respect to D _{k, l,} Equation 3 is obtained.

Substituting this D _{k, l} into <Equation 1> is shown in <Equation 4> below.

In addition, when Equation 2 is expressed as D _{i, j} and substituted into Equation 4, Equation 5 is shown below.

As described above, the right side of Equation 5 is expressed by the maximum value calculation and subtraction, unlike Equation 1. If an analog signal processing cell is used to calculate the right side of Equation 5, D _{i, j} can be calculated by substituting the output y _{i, j} of each cell into Equation 3. However, since D _{i, j} from the cell of the decoding position to its position should be 0, the cell output y _{i, j} value of the decoding position becomes I _ref from <Equation 5>. The output of the cell at the decoding position and the output value of the normal cell are summarized as in Equation 6.

However, assuming that the maximum value that can be obtained from the circuit is applied to the cell input I _ref of the decoding position, the cell that performs the max operation as shown in Equation (7) without distinction to the cell of the decoding position or the general cell. Can be.

Where u _{i, j} is Equation 8 below.

The analog signal processing cell is composed of electronic circuits that perform the calculations of Equations 7 and 8 analogously. Therefore, if the arithmetic cells located at each node of the trellis diagram perform the operations of Equations 7 and 8, and apply a large reference signal value I _ref to the input of the cell at the decoding position, The applied reference signal value decreases by d _{ij, kl} each time the branches pass to implement an array of analog signal processing cells that propagate to the surroundings.

The analog arithmetic cells that perform Equations 7 and 8 perform basic arithmetic operations to calculate the optimal path of dynamic programming. Combining these cells can implement a Viterbi decoder.

4. Structure of Biderby Decoder of the Present Invention

The structure of the bidderby decoder of the present invention is shown in FIG. In FIG. 5, the high-efficiency Viterbi decoder 300 by a two-dimensional array and multiplexer of analog signal processing cells includes a plurality of stages including an analog signal processing cell 110 and a reference signal input terminal 140. A two-dimensional array of analog processing cells, an input signal storage position indicator 120, a capacitor unit 150, a first switch unit 160, an analog output circuit 180, and an output terminal 220 And an output bit determination circuit 230 and a multiplexer 250. The present invention having this structure has a structure in which the decoding end 240 and the output end 220 are fixed as shown in FIG. 5 without using a method of circulating the decoding end and the output end as in the conventional invention as shown in FIG. 3. The decoding stage 240 is composed of the first branches (branches) and the node connected thereto.

The analog signal processing cell 110 is located at each node of the trellis diagram to perform operations of dynamic programming such as <Equation 7> and <Equation 8>, and the reference signal input terminal 140 A very large reference signal is applied to provide the first signal that propagates each stage when the reference signal decreases from the reference signal by the error value of each branch.

The input signal storage position indicator 120 is configured with a shift register to indicate a capacitor position for storing a newly input signal by the set bit position. In addition, the status indicator 130 indicates the current state by the position of the set bit, the capacitor unit 150 stores the number of code symbols in each stage in order to store a plurality of analog code input symbols corresponding to each data bit. It is composed of a set of capacitors installed, the capacitors are arranged cyclically and stored whenever the input signal is applied to the stored capacitor position is stored cyclically.

The first switch unit 160 is a switch for transferring and storing the input code symbols to a specific capacitor set of the capacitor set of the capacitor unit 150, the analog output circuit 180 of the cells belonging to each decoding stage It is a circuit to take the maximum value or average value among the output values and output them.

In addition, the output bit determination circuit 230 is a circuit for determining a digital bit of 0 or 1 using the output value at the output stage 220, and the multiplexer 250 aligns the capacitors in the order of the received signal is old. It is a circuit for temporarily applying the input signals stored in the capacitor to the decoding circuit.

5. Action of the configuration in the decoding process according to the present invention

The decoding of the high efficiency Viterbi decoder by the two-dimensional array and multiplexer of the analog signal processing cell according to the present invention having the above-described circuit structure proceeds in two stages of reference signal propagation and decoding.

1) Propagation step of reference signal

By applying the large reference signal I _ref to all the cells of the reference signal input terminal 140, while allowing the reference signal I _ref to propagate to all the stages by Equation 7, When a plurality of code symbols corresponding to data bits are received, the first switch unit 160 is switched under the control of the input signal storage position indicator 120 to store the input code symbols in a specific capacitor set of the capacitor unit 150. do. The input signal storage position indicator 120 is moved by one position by the clock every time the bit is decoded, so that the next input signal storage position is sequentially selected, so that the input code symbols are assigned to the capacitor set of each stage in the capacitor section. It is stored in cycles sequentially.

If the information is continuously input, the storage location of the input information is cyclically returned to the original storage location. Each time a signal is input, the multiplexer 250 aligns the capacitors according to the order in which the received signals are old and applies the input signals stored in the capacitors to the two-dimensional array of the analog signal processing cells at once.

In each stage of the two-dimensional array of analog signal processing cells, error information between the applied input signal and the codes assigned to each branch is calculated, and the error information starts from the reference signal propagated from each stage. After subtracting, the subtracted reference signal is propagated to the next stage.

After the propagation of the reference signal, the output terminal takes the maximum value or the average value among the cells belonging to the output terminal by using the analog output circuit 180 and outputs it.

2) decoding step

The decoding electrically cuts all outputs of even-numbered (odd-numbered) cells of the decoding stage, and determines whether the optimal path has passed a branch corresponding to zero or a branch corresponding to one. Decode to 0 or 1 by checking. That is, since each cell performs an operation that takes the maximum value among the input values, the cell receiving the input from the branches to which the negative signal is added is cut off to be naturally excluded from the optimum path, and thus the cell to which the electric signal for signal blocking is applied. If the optimal path has passed, the final output value will suddenly decrease due to the signal blocking electrical signal. This decoding can be used in one of two ways depending on the type of signal used to detect the change in output value.

Iii) Method 1 for detecting change in output signal is a method of comparing output signal changes before and after applying an electrical signal for blocking signal for decoding.

Ii) The output signal change detection method 2 omits the reference signal propagation process before applying the decoding signal cutoff electrical signal in the output signal change detection method 1 to replace the preset threshold value, and outputs the signal after applying the signal cutoff electrical signal. It is a method of comparing the threshold and the value by taking only one.

The detection of such a signal change is performed by the output bit determination circuit 230, and the result is output as 0 (or 1).

When the above decoding is completed, the input signal storage position indicator 120 moves the m th input signal storage position to the m + 1 th capacitor to prepare for decoding the next code symbol.

As described above, according to the present invention, signal processing is performed by an analog circuit, parallel processing is performed using a two-dimensional cell array, and hardware decoding is performed by using an electrical signal. High speed decoding is possible. In particular, the present invention has a structure in which the decoding stage 240 and the output stage 220 are fixed as shown in FIG. 5 without using a method of circulating the decoding stage and the output stage as in the conventional invention as shown in FIG. 3. In the existing structure as shown in FIG. 3, the analog output 180 circuit and the third switch unit 190, which are the maximum value circuits, are installed at every stage, and the position of the decoding stage and the position of the output stage are fast at every decoding bit. The hardware implementation was difficult because it had to be changed and connected to the output. On the other hand, using the structure of the present invention [Fig. 5], since the decoding stage 240 is always fixed to the first stage and the output stage 220 is the last stage, the analog output circuit 180 is necessary only at the output stage, The third switch section 190 is also unnecessary, and the structure is simple. However, in the present invention, since the multiplexer 250 is additionally used, hardware complexity increases and there is a fear of increasing the switching noise of the multiplexer. However, the multiplexer is a kind of switch box, which can be easily configured by a high-speed electronic switch, and decoding. After the switching of the multiplexer is completed, the switching noise disappears later in each bit interval, so that the switching noise of the multiplexer can be avoided. Accordingly, the present invention is a very useful invention that can be effectively used as a decoding circuit for distortion signal correction in an ultra high speed data communication network or a satellite communication network requiring a high speed data transmission, an ultra high speed magnetic disk driver, and other high speed error transmission and reception.

Claims (5)

In the structure of the Viterbi decoder, each node on the trellis diagram is configured by an analog electronic circuit longer by one or two stages than the length of the constraint field based on an analog signal processing cell implemented by the analog circuit. A two-dimensional array of implemented analog signal processing cells; A capacitor unit provided as many as the number of stages of a two-dimensional array of the analog signal processing cells for storing an input signal; High efficiency by the two-dimensional array and multiplexer of the analog signal processing cell comprising a multiplexer for connecting the capacitors in the two-dimensional array of the analog signal processing cells arranged in accordance with the input order of the information stored in the capacitors The structure of the Viterbi decoder. The method of claim 1, wherein the same reference signal having a large value is simultaneously applied to all cells of a reference signal input terminal in a two-dimensional array of analog signal processing cells, and the value is propagated while decreasing by an error value at each stage. High efficiency Viterbi by the multiplexer and multiplexer of the analog signal processing cell, characterized in that the decoding of the input signal information stored in the branches of the decoding stage using the output values of each cell obtained at the output stage The structure of the decoder. In the Viterbi decoding method using the structure of the Viterbi decoder of claim 1, a plurality of code symbols corresponding to each data bit are received and indicated by the input signal storage position indicator 120 of the capacitor sets of the capacitor unit 150. Transferring to and storing the capacitor set at the location; Arranging all signals stored in the capacitor by the multiplexer in the received order and applying them to each stage of the two-dimensional array of analog signal processing cells at a time; Computing an error between the unique code symbol corresponding to each branch of the trellis diagram at each stage and the code symbols stored in each stage capacitor, the reference signal value is reduced by the code symbol error value to propagate. Process of doing; The process of cutting off the flow of signal through these branches by applying an electrical signal to all branches corresponding to logic value 1 or all branches corresponding to logic value 0 among the branches located in the decoding stage. ; Determining a decoding result value of 1 or 0 based on whether a change occurs in an output of an output stage as a result of signal flow blocking of the decoding stage; And when the decoding of the current decoding stage is completed, moving the input signal storage position indicator by one bit to determine a next input signal storage position. 4. The method of claim 3, wherein the determining of the decoding result value of 1 or 0 based on whether the influence as a result of the signal flow blocking of the decoding stage is a change in the output of the output stage is a signal blocking at the decoding stage. By comparing the output signal change before and after applying the electric signal, or decode the reference signal propagation process before applying the electric signal for signal blocking, it replaces with the preset threshold and takes the output signal after applying the electric signal for signal blocking. Viterbi decoding method characterized in that the output stage signal change is checked using any one of the method of decoding by comparing the threshold and the value. 5. The method of claim 4, wherein the output value used for the output stage signal change test is selected from one of a maximum value of the outputs of all cells located at the output stage or an average value of all the cells of the output stage. Viterbi decoding method.

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