KR100868677B1 - Data process device, data process system, method of connecting coprocessor, and coprocessor interface method - Google Patents

Abstract

A data processing unit, a data processing system, a co-processor connecting method, and a co-processor interfacing method are provided to improve the process speed and supporting a connection of multiple co-processor using small number of signal lines. A main processor(411) transmits a first coprocessor interface signal combination, transmits a coprocessor command by receiving a second coprocessor interface signal, and continues the pipeline without waiting the result of coprocessor command. A plurality of coprocessors(412,413) are operated by the coprocessor command. A data processing unit includes a coprocessor bus(420) connecting main processors, and coprocessors for inputting the first coprocessor interface signal group, or the second coprocessor interface signal group to each coprocessors through the same signal line by the interface signals.

Description

Data processing unit, data processing system, coprocessor connection method, and coprocessor interface method {DATA PROCESS DEVICE, DATA PROCESS SYSTEM, METHOD OF CONNECTING COPROCESSOR, AND COPROCESSOR INTERFACE METHOD}

1 is a block diagram illustrating a data processing system according to an exemplary embodiment of the present invention.

2 is a block diagram showing a data processing apparatus according to a first embodiment of the present invention.

3 is a block diagram showing a data processing apparatus according to a second embodiment of the present invention.

4 is a diagram illustrating signals of the data processing apparatus of FIG. 3 when a coprocessor data processing command is transmitted.

FIG. 5 is a diagram illustrating signals of the data processing apparatus of FIG. 3 when two coprocessor data processing instructions are delivered.

FIG. 6 is a diagram illustrating signals of the data processing apparatus of FIG. 3 when a main processor receives a coprocessor data transfer command for writing data to the coprocessor.

FIG. 7 is a diagram illustrating signals of the data processing apparatus of FIG. 3 when a main processor receives a coprocessor data transfer command for reading data from a coprocessor.

8 is a diagram of the data processing apparatus of FIG. 3 when a coprocessor data transfer instruction in which the main processor writes data to the coprocessor after a coprocessor data transfer instruction in which the main processor reads data from the coprocessor is delivered. A diagram illustrating signals.

<Explanation of symbols for the main parts of the drawings>

111, 211, 411 main processor

112, 113, 212, 213, 412, 413: Coprocessor

121, 220, 420: Coprocessor Bus

221, 222, 421, 422, 423, 424

The present invention relates to an interface method between processors, and more particularly, to a data processing device, a data processing system, and a coprocessor connection employing a pipeline non-interlocking interface method between a main processor and a coprocessor. A method, and a coprocessor interface method.

In order to improve the processing speed of the system, coprocessors that complement the functions of the main processor are employed. Coprocessors that operate in response to the instructions of the main processor are typically dedicated processors that perform only specific functions. Examples of such coprocessors are floating-point processing units (FPUs), multiplier-accumulators, modulators / demodulators, digital signal processors, Viterbi operators, cryptographic processors, image processors, vector processors, and the like. .

In general, a pipeline interface method is used for communication between the main processor and the coprocessor. The pipelined interface method between the main processor and the coprocessor includes a pipeline interlocking interface method in which the main processor sends instructions to the coprocessor, and then waits for data processing on the coprocessor, and after the main processor sends instructions to the coprocessor. There is a pipeline non-interlocking interface that processes the next command without waiting for the coprocessor to process the data.

In a system using a pipeline interlocking interface scheme, the main processor decodes the instructions and passes the instructions to the coprocessor if the instructions are instructions executed by the coprocessor. The coprocessor operates in response to the command. At this time, the main processor transfers an instruction to the coprocessor and then waits until the coprocessor completes processing of the instruction. Thus, even if several tens of cycles have elapsed before the coprocessor completes processing of the instruction, the main processor is in a waiting state without processing the next instruction, so that the instruction processing is inefficient and the processing speed of the system may be slowed down.

In a system using the pipelined non-interlocking interface method, the main processor processes the next instruction without waiting for the coprocessor's instruction processing result, except in an exceptional situation such as the main processor receiving data from the coprocessor. Accordingly, the instruction processing speed may be improved in a system using the pipelined non-interlocking interface scheme.

However, in the system using the conventional pipeline non-interlocking interface method, different signal lines are used for all signals between the main processor and the coprocessor. Accordingly, the conventional interface method between the main processor and the coprocessor increases the manufacturing cost by using a plurality of signal lines, and there is a problem of providing a complicated interface. In addition, the system using the conventional pipeline non-interlocking interface method can use only a limited number of coprocessors because a number of signal lines must be used every time a coprocessor is added, and typically only one coprocessor is used. Could. That is, the conventional interface method between the main processor and the coprocessor does not support a connection with a plurality of coprocessors.

Accordingly, there is a need for an interface method between a main processor and a coprocessor that improves data processing speed of a system, uses a small number of signal lines, and supports a connection with a plurality of coprocessors.

An object of the present invention is to provide a data processing apparatus supporting connection with a plurality of coprocessors using a small number of signal lines and improving data processing speed.

Another object of the present invention is to provide a data processing system including the data processing apparatus.

Furthermore, the present invention provides a coprocessor connection method and a coprocessor interface method that support a connection with a plurality of coprocessors using a small number of signal lines and improve data processing speed.

In order to achieve the above object, a data processing apparatus according to an embodiment of the present invention includes a main processor, a plurality of coprocessors, and a coprocessor bus.

The main processor transmits a first coprocessor interface signal set and receives a second coprocessor interface signal set to deliver a coprocessor command, and after passing the coprocessor command, does not wait for a processing result of the coprocessor command. Continue the pipeline. The coprocessors operate in response to the coprocessor command received by receiving the first coprocessor interface signal set and transmitting the second coprocessor interface signal set. The coprocessor bus may include the first coprocessor interface signal set and the coprocessor interface signals through the same signal line for each coprocessor interface signal included in the first coprocessor interface signal set or the second coprocessor interface signal set. Connect the main processor and the coprocessors to be input to the second coprocessor interface signal set and output from each of the coprocessors.

The main processor and the coprocessors can proceed pipeline independently of each other.

The coprocessor instruction may be a coprocessor data processing instruction that is a command that is received by a selected one of the coprocessors and is executed independently by the selected one of the coprocessors. The first coprocessor interface signal set is a coprocessor command request signal requesting the selected one coprocessor to receive the coprocessor data processing instruction, and a coprocessor command index signal representing an index of the selected one coprocessor. It may include. The first coprocessor interface signal set may further include a coprocessor command data signal indicating a content of the coprocessor data processing instruction transferred from the main processor to the selected one coprocessor. The second coprocessor interface signal set may include a coprocessor command enable signal indicating whether the selected one coprocessor can receive the coprocessor data processing instruction.

The coprocessor instruction may be a coprocessor data transfer instruction that is a command for receiving a coprocessor selected from among the coprocessors and transmitting coprocessor data between the main processor and the selected coprocessor. The first coprocessor interface signal set is used to convey a coprocessor command request signal, the coprocessor data transfer command, to request the selected one coprocessor to receive the coprocessor data transfer command, and the selected one A coprocessor instruction index signal indicative of an index of a coprocessor, a coprocessor transfer request signal requesting that the coprocessor data be transmitted in accordance with the coprocessor data transfer command, and the coprocessor data being used to be transmitted, the selected one It may include a coprocessor forward index signal representing the index of the coprocessor of. The first coprocessor interface signal set includes: a coprocessor instruction data signal representing a content of the coprocessor data transfer instruction transmitted from the main processor to the selected one of the coprocessors; A coprocessor delivery selection signal for indicating whether to write the coprocessor data to the selected one coprocessor or to read the coprocessor data from the selected one coprocessor, and the coprocessor data transfer command. The apparatus may further include a coprocessor transfer write signal representing the coprocessor data transmitted from the main processor to the selected coprocessor. The second set of coprocessor interface signals includes a coprocessor command enabled signal indicating whether the selected one coprocessor can receive the coprocessor data transfer command, and the selected one coprocessor transfers the coprocessor data. It may include a coprocessor deliverable signal indicating whether the coprocessor data can be transmitted or received according to the command. The second coprocessor interface signal set may further include a coprocessor transfer read signal representing the coprocessor data transmitted from the selected one coprocessor to the main processor according to the coprocessor data transfer instruction.

The second coprocessor interface signal set is configured in the coprocessors to cause the main processor to execute an interrupt service routine when the coprocessor encounters an exception. It may include a coprocessor exception occurrence signal indicating that an exception has occurred.

The data processing apparatus mux selecting interface signals included in the second coprocessor interface signal set such that the main processor receives the second coprocessor interface signal set from a selected one of the coprocessors. ) May further include. The data processing apparatus may further include a decoder configured to receive a signal including an index of the selected one coprocessor from the main processor and output a signal input as a selection signal of the mux.

A data processing system according to an embodiment of the present invention includes a main processor, a plurality of coprocessors, a coprocessor bus, an external bus, a cache memory, and an internal bus.

The main processor delivers coprocessor instructions through coprocessor interface signals and continues the pipeline without waiting for processing results for the coprocessor instructions after delivering the coprocessor instructions. The coprocessors operate in response to the coprocessor command received via the coprocessor interface signals. The coprocessor bus connects the main processor and the coprocessors such that the coprocessor interface signals are output from or input to each of the coprocessors through the same signal line for each of the coprocessor interface signals. The external bus is connected to an external memory. The cache memory is connected to the external bus and stores data and commands from the external memory. The internal bus connects the cache memory with the main processor.

The main processor and the coprocessors can proceed pipeline independently of each other.

The cache memory may include a data cache memory for receiving and storing the data from the external memory, and a command cache memory for receiving and storing the command from the external memory. The internal bus may include an internal data bus connecting the data cache memory and the main processor, and an internal command bus connecting the command cache memory and the main processor.

The data processing system converts the data and instructions input from the external memory into the cache memory through the external bus between the external bus and the cache memory into cache data and cache commands that the cache memory can recognize. The apparatus may further include a bus interface device.

In the coprocessor connection method according to an embodiment of the present invention, the coprocessor from the main processor to continue the pipeline without waiting for the processing result of the coprocessor instruction after passing the coprocessor instruction to the coprocessors The main processor and the coprocessors so that the first coprocessor interface signal set is input to each of the coprocessors through the same signal line for each coprocessor interface signal included in the first coprocessor interface signal set transmitted to the coprocessor. Connect. The second coprocessor interface signal set is output from each of the coprocessors through the same signal line for each coprocessor interface signal included in the second coprocessor interface signal set transmitted from the coprocessors to the main processor. Connect the main processor and the coprocessors. The main processor and the coprocessors can proceed pipeline independently of each other.

In the coprocessor interface method according to an embodiment of the present invention, each of the coprocessor interface signals is transmitted between the main processor and the coprocessors through the same signal line to transfer coprocessor instructions from the main processor to the coprocessors. After the main processor delivers the coprocessor instruction, the main processor continues the pipeline without waiting for the processing result of the coprocessor instruction. The main processor and the coprocessors can proceed pipeline independently of each other.

Accordingly, the data processing apparatus according to an embodiment of the present invention may improve data processing speed and support connection with a plurality of coprocessors using a small number of signal lines.

With respect to the embodiments of the present invention disclosed herein, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms It should not be construed as limited to the embodiments set forth herein.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

1 is a block diagram illustrating a data processing system according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a data processing system includes a main processor 111, coprocessors 112 and 113, a coprocessor bus 121, an internal data bus 122, an internal command bus 123, and an external bus 124. ), Data cache memory 131, instruction cache memory 132, and bus interface device 133.

According to an embodiment, the bus interface device 133 may be omitted, the data cache memory 131 and the instruction cache memory 132 may be implemented as one cache memory, and also the coprocessor bus 121 and the internal The data bus 122 may be implemented as one internal bus.

The external bus 124 is connected with an external device such as an external memory. Data is input from the external memory to the data cache memory 131 through the external bus 124 and an instruction is input to the command cache memory 132. According to an embodiment, the instruction and data of the external bus 124 between the external bus 124 and the cache memories 131 and 132 may be converted into the instructions and data of the cache memories 131 and 132 or the cache memories ( A bus interface device 133 may be further included to convert the commands and data of the 131 and 132 into the commands and data of the external bus 124. The data cache memory 131 stores the input data, and the instruction cache memory 132 stores the input command. The main processor 111 fetches the input data from the data cache memory 131 through the internal data bus 122 as needed in the course of the pipeline, and through the internal command bus 123. The input command is fetched from the instruction cache memory 131. The main processor 111 decodes the fetched data or the fetched instruction to analyze and execute the fetched data or the fetched instruction. Here, when the decoded data or the decoded instruction is data or instruction for the coprocessors 112 and 113, the main processor 111 may convert the decoded data through the coprocessor data transfer instruction. 113 to the coprocessors 112 and 113, or via a coprocessor data processing instruction. Coprocessor instructions, such as the coprocessor data transfer instruction and the coprocessor data processing instruction, are transmitted through coprocessor interface signals, and the coprocessor interface signals are transmitted through coprocessor interface signals through the same signal line for each of the coprocessor interface signals. 112, 113, or input to each of the coprocessors 112, 113. Signal lines through which the coprocessor interface signals are transmitted are included in the coprocessor bus 121 connecting the main processor 111 and the coprocessors 112 and 113. After the main processor 111 transmits the coprocessor command, the main processor 111 continues the pipeline without waiting for the processing result of the coprocessor command. That is, the main processor 111 and the coprocessors 112 and 113 proceed with the pipeline independently of each other. That is, the main processor 111 and the coprocessors 112 and 113 respectively perform data processing regardless of whether or not each other's data processing is completed in performing pipeline data processing. Therefore, a data processing system employing a pipeline non-interlocking interface method can efficiently process data and employ a coprocessor bus that uses the same signal line for each of the coprocessor interface signals. It can support connections with multiple coprocessors and can be implemented using fewer signal lines.

2 is a block diagram showing a data processing apparatus according to a first embodiment of the present invention.

2, a data processing apparatus includes a main processor 211, coprocessors 212 and 213, and a coprocessor bus 220.

The main processor 211 transmits a first coprocessor interface signal set to the coprocessors 212 and 213 and receives a second coprocessor interface signal set from the coprocessors 212 and 213 to deliver coprocessor instructions. . According to an embodiment, the coprocessor command may be transmitted by the main processor 211 and the coprocessors 212 and 213 receiving the same clock signal. The main processor 211 which has delivered the coprocessor instruction continues the pipeline without waiting for the processing result of the coprocessor instruction. That is, the main processor 211 and the coprocessors 212 and 213 go through pipelines independently of each other. Therefore, the data processing apparatus according to the embodiment of the present invention processes the data efficiently.

In FIG. 2, the coprocessor instruction is a coprocessor data processing instruction that is a command that is received by a selected coprocessor of the coprocessors 212, 213 and executed independently by the selected coprocessor. The first coprocessor interface signal set is a coprocessor command request signal (CPI_REQ) requesting the selected one coprocessor to receive the coprocessor data processing command, a coprocessor command index indicating an index of the selected one coprocessor. Signal CPI_NUM, and a coprocessor command data signal CPI_INSTR indicating the contents of the coprocessor data processing instruction. The number of bits of the coprocessor command index signal CPI_NUM may vary depending on the number of coprocessors included in the data processing device. For example, when two coprocessors are included in the data processing apparatus, the coprocessor command index signal CPI_NUM may be a 1-bit signal, and when 16 coprocessors are included, a 4-bit signal may be included. The number of bits of the coprocessor command data signal CPI_INSTR may also vary according to embodiments. For example, if the coprocessor data processing instruction transmitted between the main processor 211 and the coprocessors 212 and 213 is defined as 4 bytes, the coprocessor instruction data signal CPI_INSTR is processed for the coprocessor data during one clock. It can be implemented as a 32-bit signal so that the command is passed.

The second coprocessor interface signal set includes a coprocessor command enable signal (CPI_READY) indicating whether the selected one coprocessor can receive the coprocessor data processing instruction. The coprocessor command enable signal CPI_READY output from each of the coprocessors 212 and 213 is a coprocessor command index signal CPI_NUM by the first mux 221 which receives the coprocessor command index signal CPI_NUM as a select signal. ) Is selected by the coprocessor command enable signal (CPI_READY) output from the coprocessor indicated by the index. Accordingly, the main processor 211 receives the coprocessor command enable signal CPI_READY transmitted by the selected coprocessor according to the coprocessor command index signal CPI_NUM. According to an embodiment, the second coprocessor interface signal set may further include a coprocessor exception occurrence signal CP_EXC indicating that an exception condition has occurred in the coprocessors 212 and 213. The main processor 211 may receive a coprocessor exception occurrence signal CP_EXC and perform processing according to the exception situation.

Coprocessor bus 220 includes coprocessor command request signal (CPI_REQ), coprocessor command index signal (CPI_NUM), coprocessor command data signal (CPI_INSTR), coprocessor command enable signal (CPI_READY), and coprocessor exception occurrence signal ( Signal lines transmitting the CP_EXC, a first mux 221, and a second mux 222. Here, the coprocessor command request signal (CPI_REQ), the coprocessor command index signal (CPI_NUM), the coprocessor command data signal (CPI_INSTR), the coprocessor command enable signal (CPI_READY), and the coprocessor exception occurrence signal (CP_EXC) are each Each signal is transmitted by the same signal line. Therefore, even if a coprocessor is added to the data processing apparatus, the data processing apparatus may be implemented using a small number of signal lines without additionally using signal lines.

Referring to the operation of the data processing apparatus, the main processor 211 is a coprocessor command request signal (CPI_REQ) and the coprocessor data processing command to inform the coprocessors (212, 213) to transfer the coprocessor data processing instruction A coprocessor command index signal (CPI_NUM) is transmitted indicating which of the coprocessors 212, 213 is the command passed to the coprocessor. The coprocessors 212 and 213 receive the coprocessor command request signal CPI_REQ and the coprocessor command index signal CPI_NUM, and the main processor 211 indicates the index included in the coprocessor command index signal CPI_NUM. Receives a coprocessor command enable signal (CPI_READY) sent by a coprocessor. If the coprocessor command enable signal CPI_READY received by the main processor 211 is logic “high,” the main processor 211 transmits a coprocessor command data signal CPI_INSTR indicating the contents of the coprocessor data processing instruction. The coprocessor indicated by the index receives the coprocessor command data signal CPI_INSTR, receives the coprocessor data processing command, and performs data processing according to the coprocessor data processing command. At this time, the main processor 211 which has delivered the coprocessor data processing instruction continues the pipeline of the main processor 211 without waiting for the processing result of the coprocessor data processing instruction.

In the data processing apparatus, the main processor 211 performs processing according to the exception situation when an exception situation occurs in the coprocessors 212 and 213. The main processor 211 receives a coprocessor exception occurrence signal CP_EXC indicating that an exception has occurred from the coprocessors 212 and 213. The coprocessor exception occurrence signal CP_EXC received by the main processor 211 is a coprocessor exception occurrence signal CP_EXC output from the coprocessor where an exception occurs among the coprocessors 212 and 213 by the mux 222. Can be selected. According to an embodiment, a decoder for providing a selection signal of the mux 221 may be further included. The main processor 211 that receives the coprocessor exception generation signal CP_EXC may execute an interrupt service routine to process the exception.

3 is a block diagram showing a data processing apparatus according to a second embodiment of the present invention.

Referring to FIG. 3, a data processing apparatus includes a main processor 411, coprocessors 412 and 413, and a coprocessor bus 420.

In FIG. 3, main processor 411 transmits a first coprocessor interface signal set to coprocessors 412 and 413 and receives a second coprocessor interface signal set from coprocessors 412 and 413. Pass the command. The coprocessor instruction is a coprocessor data processing instruction which is received by a selected coprocessor of the coprocessors 412 and 413 and is independently executed by the selected coprocessor, or the main processor and the selected processor. It may be a coprocessor data transfer command which is a command for transmitting coprocessor data between one coprocessor. In addition, the main processor 411 may receive a coprocessor exception occurrence signal CP_EXC from the coprocessors 412 and 413 to perform processing according to the exception situation.

The first coprocessor interface signal set includes: a coprocessor instruction request signal (CPI_REQ), the coprocessor data processing instruction, or requesting the selected one of the coprocessors to receive the coprocessor data processing instruction or the coprocessor data transfer instruction. A coprocessor command index signal (CPI_NUM) which is used to convey the coprocessor data transfer command and indicates an index of the selected one coprocessor, and which requests the coprocessor data to be transmitted according to the coprocessor data transfer command A transfer request signal (CPD_REQ), a coprocessor transfer index signal (CPD_NUM) used to transmit the coprocessor data and indicating an index of the selected one coprocessor, and transferred from the main processor to the selected one coprocessor Is a coprocessor instruction data signal (CPI_INSTR) indicating the contents of the coprocessor data processing instruction or the coprocessor data transfer instruction, and the coprocessor data transfer instruction writes data to the selected coprocessor by the main processor 411. A coprocessor transfer selection signal (CPD_RW) indicating whether the command is a command to read or read data from the selected one of the coprocessors, and the coprocessor data transfer command from the main processor to the selected one of the coprocessors. A coprocessor transfer write signal (CPD_WDATA) indicating the data to be written. Like the coprocessor command index signal CPI_NUM described above, the coprocessor transfer index signal CPD_NUM may have a different number of bits depending on the number of coprocessors included in the data processing apparatus. The coprocessor transfer write signal CPD_WDATA may also vary in number of bits in some embodiments. For example, in the case of a data processing device operating through a 32-bit operating system, the coprocessor transfer write signal CPD_WDATA may be implemented as a 32-bit signal.

The second coprocessor interface signal set is a coprocessor command enable signal (CPI_READY) indicating whether the selected one coprocessor can receive the coprocessor data processing instruction or the coprocessor data transfer instruction, the selected one A coprocessor deliverable signal (CPD_READY) indicating whether a coprocessor can transmit or receive the coprocessor data in accordance with the coprocessor data transfer instruction, and from the selected coprocessor in accordance with the coprocessor data transfer instruction And a coprocessor transfer read signal CPD_RDATA representing the coprocessor data transmitted to the main processor 411. The coprocessor delivery possible signal CPD_READY output from each of the coprocessors 412 and 413 is a coprocessor delivery index signal CPD_NUM by a third mux 423 that receives the coprocessor delivery index signal CPD_NUM as a selection signal. ) Is selected by the coprocessor forwardable signal (CPD_READY) output from the coprocessor indicated by the index. Accordingly, the main processor 411 receives the coprocessor deliverable signal CPD_READY transmitted by the selected coprocessor according to the coprocessor forward index signal CPD_NUM. The coprocessor delivery read signal CPD_RDATA may also be selected as the signal output from the selected coprocessor by the fourth mux 424 which receives the coprocessor delivery index signal CPD_NUM as the selection signal. According to an embodiment, the second coprocessor interface signal set may further include a coprocessor exception occurrence signal CP_EXC indicating that an exception condition has occurred in the coprocessors 412 and 413. The main processor 411 may receive a coprocessor exception generation signal CP_EXC and perform processing according to the exception situation.

Coprocessor bus 420 includes coprocessor command request signal (CPI_REQ), coprocessor command index signal (CPI_NUM), coprocessor command data signal (CPI_INSTR), coprocessor command enable signal (CPI_READY), and coprocessor delivery request signal (CPD_REQ). ), Coprocessor forward index signal (CPD_NUM), coprocessor forward select signal (CPD_RW), coprocessor forward write signal (CPD_WDATA), coprocessor forward ready signal (CPD_READY), coprocessor forward read signal (CPD_RDATA), and coprocessor Signal lines transmitting the exception occurrence signal CP_EXC include a first mux 421, a second mux 422, a third mux 423, and a fourth mux 424. Here, coprocessor command request signal (CPI_REQ), coprocessor command index signal (CPI_NUM), coprocessor command data signal (CPI_INSTR), coprocessor command enable signal (CPI_READY), coprocessor delivery request signal (CPD_REQ), coprocessor delivery Index signal (CPD_NUM), coprocessor forward select signal (CPD_RW), coprocessor forward write signal (CPD_WDATA), coprocessor forward ready signal (CPD_READY), coprocessor forward read signal (CPD_RDATA), and coprocessor exception occurrence signal (CP_EXC) ) Is transmitted by the same signal line for each signal. Therefore, even if a coprocessor is added to the data processing apparatus, the data processing apparatus may be implemented using a small number of signal lines without additionally using signal lines.

Referring to the operation of the data processing apparatus, the main processor 411 may transmit the coprocessor data processing instruction or the coprocessor data transfer instruction to the coprocessors 212 and 213. When the main processor 411 delivers the coprocessor data processing instruction, the coprocessor instruction request signal (CPI_REQ), the coprocessor instruction index signal (CPI_NUM), the coprocessor instruction data signal (CPI_INSTR), and the coprocessor instruction enable signal. Only (CPI_READY) is used. The coprocessor data processing instruction is transmitted in the same manner as that of the coprocessor data processing instruction in the data processing apparatus of FIG. 2. Therefore, the description of the operation related to conveying the coprocessor data processing instruction is omitted.

Referring to the operation of the data processing device when the coprocessor data transfer command is delivered, the main processor 411 delivers the coprocessor data transfer command to one of the coprocessors 412 and 413. After the coprocessor data transfer command is delivered, coprocessor data according to the coprocessor data transfer command is transferred between the main processor 411 and the selected one of the coprocessors. That is, the delivery of the coprocessor data transfer instruction involves the delivery of the coprocessor data. The main processor 411 receives the coprocessor command transfer signal CPI_REQ, the coprocessor command index signal CPI_NUM, the coprocessor command data signal CPI_INSTR, and the coprocessor command enable signal CPI_READY. To the selected one coprocessor. The coprocessor data transfer instruction is delivered in the same manner as the coprocessor data processing instruction is delivered in the data processing apparatus of FIG. 2. Hereinafter, a process of transmitting the coprocessor data according to the coprocessor data transfer command will be described.

The main processor 411, which has delivered the coprocessor data transfer command, transmits the coprocessor transfer request signal CPD_REQ to the coprocessors 412 and 413 so that the coprocessor data is transmitted. A coprocessor delivery index signal (CPD_NUM) indicating which coprocessor is the data being delivered to or from which coprocessor, and a coprocessor delivery selection signal indicating whether the coprocessor data transfer command is a write command or a read command. Send (CPD_RW). The main processor 411 which has transmitted the coprocessor delivery request signal CPD_REQ receives the coprocessor delivery possible signal CPD_READY transmitted by the coprocessor indicated by the index included in the coprocessor delivery index signal CPD_NUM. If the coprocessor deliverable signal CPD_READY received by the main processor 411 is logic "high" and the coprocessor delivery select signal CPD_RW is a logic "high", then the main processor 311 receives the coprocessor transfer write signal CPD_WDATA. Transmit the coprocessor data to the selected coprocessor, and the coprocessor forward enable signal CPD_READY received by the main processor 411 is logic “high” and the coprocessor forward select signal CPD_RW is If the logic is low, the main processor 411 receives the coprocessor transfer read signal CPD_RDATA and receives the coprocessor data.

In some embodiments, the main processor 411 may not transmit the coprocessor transfer selection signal CPD_RW. When the main processor 411 does not transmit the coprocessor transfer selection signal CPD_RW, the main processor 411 determines whether the coprocessor data transfer command is a write command or a read command when the coprocessor data transfer command is transmitted. Pass information about Further, even if information about whether the coprocessor data transfer command is a write command or a read command is passed when the coprocessor data transfer command is delivered, the main processor when the coprocessor data is delivered to simplify the configuration of the coprocessor. 411 may send a coprocessor delivery selection signal CPD_RW. Also, according to an embodiment, the main processor 411 may further transmit a coprocessor transfer register signal indicating to which selected coprocessor data the coprocessor data is to which coprocessor data. The selected coprocessor transmits the coprocessor transfer register signal to determine which register among the selected coprocessors receives the coprocessor data or from which register to output the coprocessor data. You can decide.

The main processor 411 not only delivers and executes coprocessor data processing instructions and coprocessor data transfer instructions, but also handles exception processing in the case where an exception occurs in the coprocessors 412 and 413. The main processor 411 receives from the coprocessors 412 and 413 a coprocessor exception occurrence signal CP_EXC indicating that an exception has occurred. The coprocessor exception occurrence signal CP_EXC received by the main processor 411 is a coprocessor exception occurrence signal CP_EXC output from the coprocessor in which an exception occurs among the coprocessors 412 and 413 by the first mux 421. ) May be selected. According to an embodiment, a decoder for providing a selection signal of the first mux 421 may be further included. The main processor 411 receiving the coprocessor exception occurrence signal CP_EXC may execute an interrupt service routine to process the exception.

Hereinafter, operations of the main processor and the coprocessor when the coprocessor command is transmitted in the data processing device of FIG. 3 will be described with reference to FIGS. 4 to 8. The hatched portions in FIGS. 4 to 8 describe operations of the main processor and the coprocessor when the main processor and the coprocessor operate, or when coprocessor instructions are transmitted, regardless of the waveform of the signals of the portion. That's unnecessary.

4 is a diagram illustrating signals of the data processing apparatus of FIG. 3 when a coprocessor data processing command is transmitted.

In FIG. 4, no coprocessor data processing instruction is transmitted since the coprocessor instruction request signal CPI_REQ is a logic “low” on the first rising edge of the clock signal CLK. On the second rising edge of the clock signal CLK, the coprocessor command request signal CPI_REQ is a logic "high", so there is a coprocessor data processing instruction that the main processor is trying to pass, and the coprocessor command enable signal (CPI_READY) is a logic " High ”so that the coprocessor can process the coprocessor data processing instruction. Accordingly, the coprocessor data processing command is transmitted to the coprocessor indicated by the index included in the coprocessor command index signal CPI_NUM through the coprocessor command data signal CPI_INSTR. The coprocessor receiving the coprocessor command data signal CPI_INSTR performs data processing according to the coprocessor data processing command.

FIG. 5 is a diagram illustrating signals of the data processing apparatus of FIG. 3 when two coprocessor data processing instructions are delivered.

In FIG. 5, the operations at the first rising edge and the second rising edge of the clock signal CLK of the clock signal CLK are the same as those in FIG. 4. In the example of FIG. 5, it is assumed that the pipeline of the coprocessor stalls for one cycle after the first coprocessor data processing instruction is delivered on the second rising edge of the clock signal CLK. The coprocessor with the pipeline stalled for one cycle after the second rising edge of the clock signal CLK sends a logic “low” coprocessor command enable signal CPI_READY. On the third rising edge of the clock signal CLK, the coprocessor command request signal CPI_REQ is a logic “high”, so there is a second coprocessor data processing instruction that the main processor is trying to pass, but the coprocessor command enable signal CPI_READY Since the logic is low, the second coprocessor data processing instruction is not passed. Included in the coprocessor command index signal (CPI_NUM) because the coprocessor command request signal (CPI_REQ) is logic "high" and the coprocessor command enable signal (CPI_READY) is logic "high" on the fourth rising edge of the clock signal (CLK). The second coprocessor data processing instruction is delivered via a coprocessor instruction data signal CPI_INSTR to the coprocessor indicated by the index. The coprocessor receiving the coprocessor command data signal CPI_INSTR performs data processing according to the second coprocessor data processing command.

FIG. 6 is a diagram illustrating signals of the data processing apparatus of FIG. 3 when a main processor receives a coprocessor data transfer command for writing data to the coprocessor.

In FIG. 6, the operations at the first rising edge and the second rising edge of the clock signal CLK of the clock signal CLK are similar to those in FIG. 4 or 5. However, the coprocessor data processing instruction is transmitted on the first rising edge and the second rising edge of the clock signal CLK of FIG. 4 or 5, but the first rising edge and the second rising edge of the clock signal CLK of FIG. At the edge, a coprocessor data transfer instruction is sent. On the third rising edge of the clock signal CLK, the coprocessor forward request signal CPD_REQ is a logic “high”, so there is coprocessor data that the main processor wants to pass or receive, and the coprocessor forward signal CPD_READY is a logic “ High ”so that the coprocessor can either transmit or receive the coprocessor data. In this case, since the coprocessor delivery selection signal CPD_RW is logic “high,” the main processor includes the coprocessor included in the coprocessor delivery write signal CPD_WDATA to the coprocessor indicated by the index included in the coprocessor delivery index signal CPD_NUM. Write the processor data.

FIG. 7 is a diagram illustrating signals of the data processing apparatus of FIG. 3 when a main processor receives a coprocessor data transfer command for reading data from a coprocessor.

In FIG. 7, the operations at the first rising edge of the clock signal CLK and the second rising edge of the clock signal CLK are the same as those in FIG. 6. On the third rising edge of the clock signal CLK, the coprocessor forward request signal CPD_REQ is a logic “high”, so there is coprocessor data that the main processor wants to pass or receive, and the coprocessor forward signal CPD_READY is a logic “ High ”so that the coprocessor can either transmit or receive the coprocessor data. At this time, since the coprocessor delivery selection signal CPD_RW is a logic “low”, the main processor receives data contained in the coprocessor delivery read signal CPD_RDATA from the coprocessor indicated by the index included in the coprocessor delivery index signal CPD_NUM. Read out. The coprocessor that receives the coprocessor delivery request signal CPD_REQ on the third rising edge of the clock signal CLK transmits the coprocessor delivery read signal CPD_RDATA on the fourth rising edge of the clock signal CLK to transmit the coprocessor. The data is passed.

8 is a data processing apparatus of FIG. 3 when a coprocessor data transfer instruction in which the main processor writes data to the coprocessor after a coprocessor data transfer instruction in which the main processor reads data from the coprocessor is passed; Figures showing signals of.

In FIG. 8, the operations at the first rising edge of the clock signal CLK and the second rising edge of the clock signal CLK are the same as those in FIG. 6 or FIG. 7. The first coprocessor data transfer command is delivered on the second rising edge of the clock signal CLK. On the third rising edge of the clock signal CLK, the coprocessor forward request signal CPD_REQ is logic "high", the coprocessor forward enable signal CPD_READY is logic "high", and the forward select signal CPD_RW is a logic " Low ”, the main processor requests the coprocessor indicated by the index included in the coprocessor transfer index signal CPD_NUM to read the first coprocessor data from the coprocessor. In addition, since the coprocessor command request signal CPI_REQ is a logic “high” on the third rising edge of the clock signal CLK, there is a second coprocessor data transfer command that the main processor attempts to deliver, but the coprocessor command enable signal CPI_READY. ) Is a logic "low" so that the second coprocessor data transfer instruction is not delivered. On the fourth rising edge of the clock signal CLK, the second coprocessor data transfer command is sent because the coprocessor command request signal CPI_REQ is logic “high” and the coprocessor command enable signal CPI_READY is logic “high”. do. In addition, the first coprocessor data is read at the fourth rising edge of the clock signal CLK. On the fifth rising edge of the clock signal CLK, the coprocessor forward request signal CPD_REQ is logic "high", the coprocessor forward signal (CPD_READY) is logic "high", and the forward select signal CPD_RW is a logic " High ”, so that the main processor executes a second coprocessor data transfer instruction, which is an instruction to write data to the coprocessor indicated by the index included in the coprocessor transfer index signal CPD_NUM, to the second coprocessor data. Enter.

Meanwhile, in the above-described embodiments, the case where the number of coprocessors included in the data processing device and the data processing system is two is taken as an example, but the data processing device and the data processing system according to the present invention include three or more coprocessors. can do.

The data processing apparatus, the data processing system, the coprocessor connection method, and the coprocessor interface method according to the embodiment of the present invention as described above can improve the data processing speed and can support the connection with a plurality of coprocessors. .

In addition, the data processing apparatus, the data processing system, the coprocessor connection method, and the coprocessor interface method according to the embodiment of the present invention can support the connection with a plurality of coprocessors using a small number of signal lines.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (23)

Send a first coprocessor interface signal set and receive a second coprocessor interface signal set to deliver a coprocessor instruction, and after passing the coprocessor instruction, continue the pipeline without waiting for the processing result of the coprocessor instruction. Proceeding to the main processor; A plurality of coprocessors operable in response to said coprocessor command receiving said first coprocessor interface signal set and transmitting said second coprocessor interface signal set; And The first coprocessor interface signal set is input to each of the coprocessors through the same signal line for each coprocessor interface signal included in the first coprocessor interface signal set or the second coprocessor interface signal set. And a coprocessor bus connecting the main processor and the coprocessors such that a coprocessor interface signal set is output from each of the coprocessors. The method of claim 1, And the main processor and the coprocessors run the pipeline independently of each other. The method of claim 1, wherein the coprocessor instruction is: And a coprocessor data processing instruction, the coprocessor data processing instruction being one of the coprocessors that is received and executed independently by the selected one of the coprocessors. The method of claim 3, wherein the first coprocessor interface signal set, A coprocessor instruction request signal requesting the selected one of the coprocessors to receive the coprocessor data processing instruction; And And a coprocessor command index signal representing an index of the selected one coprocessor. The method of claim 4, wherein the first coprocessor interface signal set, And a coprocessor command data signal indicating a content of the coprocessor data processing instruction transmitted from the main processor to the selected coprocessor. The method of claim 3, wherein the second coprocessor interface signal set, And a coprocessor command enabled signal indicating whether the selected one coprocessor can receive the coprocessor data processing command. The method of claim 1, wherein the coprocessor instruction is: And a coprocessor data transfer instruction, the coprocessor data transfer instruction being a coprocessor data transfer command between the main processor and the selected one coprocessor. The method of claim 7, wherein the first coprocessor interface signal set, A coprocessor command request signal for requesting the selected one of the coprocessors to receive the coprocessor data transfer command; A coprocessor command index signal used to convey the coprocessor data transfer command and indicating an index of the selected one coprocessor; A coprocessor delivery request signal for requesting the coprocessor data to be transmitted in accordance with the coprocessor data transfer command; And And a coprocessor forward index signal representing the index of the selected one coprocessor, wherein the coprocessor data is used for transmission. The method of claim 8, wherein the first coprocessor interface signal set, A coprocessor instruction data signal representing the content of the coprocessor data transfer instruction transferred from the main processor to the selected one coprocessor; A coprocessor delivery informing that the coprocessor data delivery instruction is whether the main processor writes the coprocessor data to the selected one coprocessor or reads the coprocessor data from the selected one coprocessor. Selection signal; And And a coprocessor transfer write signal representing the coprocessor data transmitted from the main processor to the selected one of the coprocessors according to the coprocessor data transfer instruction. The method of claim 7, wherein the second coprocessor interface signal set, A coprocessor command enabled signal indicating whether the selected one coprocessor can receive the coprocessor data transfer command; And And a coprocessor deliverable signal indicating whether the selected one of the coprocessors can transmit or receive the coprocessor data in accordance with the coprocessor data transfer command. The method of claim 10, wherein the second coprocessor interface signal set, And a coprocessor transfer read signal indicative of the coprocessor data transmitted from the selected one coprocessor to the main processor in accordance with the coprocessor data transfer instruction. The method of claim 1, wherein the second coprocessor interface signal set, A coprocessor exception is generated informing the coprocessors that the exception has occurred so that the main processor executes an interrupt service routine to process according to the exception when an exception occurs in the coprocessors. A data processing apparatus comprising a signal. The method of claim 1, Further comprising mux for selecting interface signals included in the second coprocessor interface signal set such that the main processor receives the second coprocessor interface signal set from a selected one of the coprocessors. A data processing device, characterized in that. The method of claim 13, And a decoder configured to receive a signal including an index of the selected one coprocessor from the main processor and output a signal input as the selection signal of the mux. A main processor for delivering a coprocessor instruction through coprocessor interface signals, and continuing the pipeline without waiting for a processing result of the coprocessor instruction after delivering the coprocessor instruction; A plurality of coprocessors operative in response to the coprocessor command received via the coprocessor interface signals; A coprocessor bus connecting the main processor and the coprocessors such that the coprocessor interface signals are output from each of the coprocessors or input to each of the coprocessors through the same signal line for each of the coprocessor interface signals; An external bus connected to the external memory; A cache memory connected to the external bus and storing data and commands from the external memory; And And an internal bus connecting the cache memory and the main processor. The method of claim 15, And said main processor and said coprocessors proceed pipeline independently of each other. The method of claim 15, wherein the cache memory, A data cache memory configured to receive and store the data from the external memory; And And a command cache memory configured to receive and store the command from the external memory. The method of claim 17, wherein the internal bus, An internal data bus connecting the data cache memory and the main processor; And And an internal command bus connecting the instruction cache memory and the main processor. The method of claim 15, A bus interface device between the external bus and the cache memory for converting the data and the command inputted from the external memory into the cache memory through the external bus into cache data and cache commands recognizable by the cache memory; The data processing system further comprises. Each included in the first coprocessor interface signal set transmitted from the main processor to the coprocessors after passing the coprocessor instruction to the coprocessors and continuing the pipeline without waiting for the processing result of the coprocessor instruction. Coupling the main processor and the coprocessors so that the first coprocessor interface signal set is input to each of the coprocessors through the same signal line for each coprocessor interface signal of the coprocessor interface signal; And The second coprocessor interface signal set is output from each of the coprocessors through the same signal line for each coprocessor interface signal included in the second coprocessor interface signal set transmitted from the coprocessors to the main processor. Coupling a coprocessor to a main processor. The method of claim 20, And said main processor and said coprocessors proceed pipeline independently of each other. Each of the coprocessor interface signals is transmitted between the main processor and the coprocessors through the same signal line to deliver coprocessor instructions from the main processor to the coprocessors; And And after the main processor delivers the coprocessor instruction, continuing the pipeline without waiting for the processing result of the coprocessor instruction. The method of claim 22, And said main processor and said coprocessors proceed pipeline independently of each other.

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