KR100865046B1 - Methods and apparatuses for providing stacked-die devices - Google Patents

Abstract

Methods and apparatuses for providing a stacked die device composed of stacked subpackages are disclosed. In one embodiment of the invention, each subpackage has interconnections formed on a die-side of the substrate for interconnecting with other subpackages. The dies and connecting wires are protected by an encapsulant while exposing the top of each interconnect. In one embodiment of the invention the encapsulant is a stencil printable encapsulant and the top of the interconnect is exposed by using a patterned stencil during application of the encapsulant.

Stacked Die Devices, Subpackages, Interconnects, Encapsulants, Thermosets

Description

METHODS AND APPARATUSES FOR PROVIDING STACKED-DIE DEVICES

 Embodiments of the present invention generally relate to the field of integrated circuit devices and more particularly to methods and apparatuses for stacking dies to create a stacked-die device.

If the chips can be more densely packaged on the surface of the silicon circuit board, the size and cost of the module can be reduced and the system performance can be improved. One possible method of maximizing packaging densities involves placing chips on top of each other to form three-dimensional stacks called stacked-chip devices or stacked-die devices. In the past years, there has been some interest in stacking chips where possible. Such chip-lamination techniques include stacking multiple chips of reduced size or stacking multiple chips of the same size using spacers, or beveling to facilitate wire-bonds. Employing technology or using “T-cut” dies for the upper die. Problems arise as the trend moves toward stacking more die, ranging from two to four stacked dies of today's typical devices, to six to eight stacked dies in the near future, and more dies do.

For example, in a reduced size die technique, eventually the size of the upper die reaches one point that is ineffective. In the beveled or T-cut die technique, there is a limit of the size difference between the lower and upper dies of the stack (ie, excessive overhang is more difficult to handle and makes stacked die devices less stable). do.

In addition, each of these techniques raises the problem of increasing yield losses. As the number of stacked dies increases, yield loss increases. Stacked die devices are not fully inspected until completion. Although temperature and other error tolerance checks can be completed on individual dies at the die level before lamination, such testing does not represent the overall functionality for stacked die devices. In particular, if one of the stacked dies implements a logic processor device, the speed check is unreliable before all electrical connections of the entire completed device.

To address the issues of stacking limitations and yield loss, the concept of sub-packaging of stacked dies has been introduced. In such a technique, a number of subpackages, each containing a stacked die device, are produced and inspected. Upon successful inspection, two or more subpackages are stacked and electrically connected to form a stacked die device.

1 illustrates a stacked die device composed of stacked subpackages according to the prior art. The stacked die device 100 shown in FIG. 1 includes three subpackages 105a, 105b and 105c, which may be stacked die packages such as packages 105b and 105c. The package 105a includes a substrate 110a having conductive balls 120 formed on the bottom surface 111 of the substrate 110a (eg, a ball grid array (BGA)). The conductive balls 120 are for electrically connecting the substrate 110a to a motherboard (not shown). Die 130a is disposed over top surface 112 of substrate 110a.

Package 105b includes a stacked die device having stacked die 130c over die 130b. Package 105c includes a stacked die device in which one die has stacked dies 130d-130f over another die. All of the dies 130a, 130b and 130c, and 130d-130f are electrically connected to each substrate 110a-110c or to each other with wire bonds 140. Wire bonds 140 for each subpackage are typically covered with a molding compound 145 for protection prior to stacking the subpackages. The subpackages are electrically connected to each other with interconnects 150, which may be copper junctions between the subpackages.

Stacked die device 100 addresses certain disadvantages of stacking limitations and yield loss, but also has disadvantages. For example, copper implants that form connecting junctions between subpackages may require additional space. That is, the interconnects 150 between the subpackages need to be removed from the wire bonds 140 to some extent so that they are not covered by the molding compound 145. This increases the size of the stacked die device. In addition, forming copper implants requires additional processes (eg, drilling), increasing costs. The configuration of each package is practically limited to standard shapes and sizes. 1A is a top view of a subpackage for the stacked die device 100 described above with respect to FIG. 1. As shown in FIG. 1A, the copper implants 150 used to connect the subpackages have a carrier 155. The carrier is beyond the area on the substrate 110a where the wire bonds 140 can be placed. For a given size, die 130a, substrate 110a and thus subpackage 105a need to be large enough to accommodate carrier 155.

The present invention will be best understood by reference to the accompanying drawings and the following description used to illustrate embodiments of the invention.

1 illustrates a stacked die device composed of stacked subpackages, according to the prior art.

1A is a top view of a subpackage for stacked die devices according to the prior art.

2 illustrates a top view and a side view of a subpackage substrate according to an embodiment of the present invention.

3A-3D illustrate a process for producing a subpackage according to one embodiment of the invention.

4 illustrates a process for encapsulating dies of a subpackage while exposing the top of the subpackage interconnects in accordance with an embodiment of the present invention.

5 illustrates a stacked die device composed of stacked subpackages in accordance with an embodiment of the present invention.

In the following description, numerous specific details are set forth. However, it should be understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. In addition, certain features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Moreover, aspects of the invention are less than all of the features of the single disclosed embodiment. Thus, the following claims are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

2 illustrates a top view and a side view of a subpackage substrate according to an embodiment of the present invention. Substrate 210 has interconnects 240 and subpackage interconnects 250, an example that can be used to electrically connect one subpackage to another subpackage thereon in a stacked subpackage configuration. For example, it may be conductive metal balls. Subpackage interconnects 250 may be similar to BGAs typically employed on the bottom of a die for surface mount packaging. According to one embodiment of the invention, the subpackage interconnects are formed on the top side (die side) of the substrate. The subpackage interconnects 250 are separated so that wire bonding can be achieved near and between the subpackage interconnects 250. In one embodiment, prior to forming the subpackage interconnects 250 that will provide interconnection between the subpackages, various wire bonds may be formed to the location where the subpackage interconnects will be placed. The subpackage interconnects are electrically connected to die 230 via interconnects 240. The bottom surface of the substrate may have metal lands or conventional BGA for electrically connecting to the subpackage below.

3A-3D illustrate a process for producing a subpackage according to one embodiment of the invention. As shown in FIG. 3A, the substrate 310 is a conventional substrate having features for die attach and wire bond, or flip chip attach. The bottom surface 311 of the substrate 310 has conductive metal balls 320 as described above with respect to FIG. 1. Substrate 310 has subpackage interconnects 350 formed on top surface 312. Subpackage interconnects 350 are attached to metal pads (not shown) formed near the substrate 310. Subpackage interconnects 350, which may be conductive metal balls, may be formed of solder, which may be a lead / tin alloy. In alternative embodiments, subpackage interconnects 350 may be made of copper or other suitable conductive metals. In such embodiments, subpackage interconnects 350 may be attached using a process similar to the conventional BGA ball attach method.

In one embodiment of the invention, after forming the subpackage interconnects 350 on the top surface 312 of the substrate 310, integrated circuit chips (dies) are attached to the substrate 310. According to one embodiment of the invention, the dies may implement various types of memory devices or logic processor devices. Dies, which may be one or multiple dies in a stacked die configuration, are attached to the substrate 310 and to each other using conventional die attach methods and materials. As shown in FIG. 3B, die 330a is attached to top surface 312 of substrate 310 and die 330b is stacked over die 330a and attached to die 330a. Each die may be electrically connected to the substrate and to each other using conventional methods (eg, wire bonding or flip chip attachment). Subpackage interconnects 350 extend above top 312 and above the die stack.

As shown in FIG. 3C, although the top portion 351 of the subpackage interconnects 350 is exposed, the attached die or die stack, if any, is encapsulated to allow dies and connection wires (eg, For example, wire-bonds are protected. The encapsulant extends above the top surface 312 higher than the die stack, but not as high as the subpackage interconnects 350. In one embodiment of the invention, encapsulant 345 comprises silica or other inorganic particles, which may be of varying amounts (e.g., 0-80% by weight), including CTE, modulus, or viscosity ( It is a thermosetting material such as epoxy or polymer resin that alters viscosty. In one embodiment of the invention, such a thermoset material may include flux to provide fluxing capabilities during subsequent reflow processes. In one embodiment of the present invention, as shown in FIG. 3C, encapsulation of the die stack is performed through a stencil printing process, described in greater detail below.

As shown in FIG. 3D, encapsulant 345 may encapsulate all of subpackage interconnects 350. Subpackage interconnects 350 may remain encapsulated if the subpackage is the top subpackage of the stacked subpackage device. In a stacked subpackage configuration, when subpackage interconnects are used to electrically connect the subpackage to other subpackages thereon, the upper portion of the subpackage interconnects 350 may be ground by grinding or laser drilling. Can be exposed through known methods.

Subpackages to be stacked over other subpackages may not include conductive metal balls, such as BGAs, but may include land pads 321 corresponding to the subpackage interconnects of the subpackage they are stacked on.

Encapsulation

In one embodiment of the present invention, encapsulation of the dies of the subpackage is performed using a stencil printing process. The height coverage of the encapsulant is controlled by material selection and stencil-printing process optimization for improved processability, encapsulation performance, and thermomechanical properties. 4 illustrates a process of encapsulating dies of a subpackage while exposing the top of the subpackage interconnects in accordance with an embodiment of the present invention. Process 400, shown in FIG. 4, begins with operation 405 in which a stencil is provided and placed over the substrate. The stencil, which may be a thin nickel plate, is patterned to cover a predetermined top portion of each subpackage interconnect.

In operation 410, a stencil-printable encapsulant is provided. Typical encapsulants are not stencil printable, but can be made stencil printable by reducing their viscosity, for example, by adding solvents to the encapsulation material.

In operation 415, a stencil printable encapsulant is applied to encapsulate the dies. The amount of encapsulant is controlled such that the top of each subpackage interconnect is exposed while the dies (eg, die-stack) and connecting wires are fully encapsulated. The bottom portion of the subpackage interconnects is also encapsulated. In practice, some encapsulant may remain on top of the subpackage interconnects but the amount of such encapsulant is reduced because of the low viscosity of the encapsulant.

In operation 420, to remove the solvent (ie, to evaporate any or all of the solvent added in operation 410). The temperature of the substrate is raised. In one embodiment of the invention, the substrate is placed at a temperature of about 100 ° C. for about 2 hours. The temperature and time for such evaporation process may vary depending on the amount of solvent to be evaporated. Solvents helpful in the stencil printing process are removed as much as possible prior to reflow to reduce voids that may form during curing / reflow if the solvent is not removed. Removal of the solvent increases the viscosity of the applied encapsulant. In one embodiment of the invention, after baking, the encapsulant is cured (cross linked) during the subsequent reflow process, which will be described in more detail below. In one embodiment of the present invention, such curing is performed with solder reflow. In one embodiment of the present invention, the cure kinetics of the encapsulant is specifically tailored to reduce interference in junction formation.

<Reflow>

Two or more subpackages are interconnected to form a stacked subpackage device according to one embodiment of the invention. Subpackages are stacked on top of other subpackages such that conductive metal balls or land pads on the bottom of the top subpackage correspond to exposed subpackage interconnects of the next subpackage in the stack. A reflow process, or other conventional surface mount process, is then performed to create the interconnect between the subpackages. During reflow, the viscosity of the encapsulant decreases due to the increasing temperature. There is a wetting force between the land pads of the upper subpackage and the subpackage interconnects of the lower subpackage such that any residual encapsulant material on the surface of the subpackage interconnects is pushed out and the subpackages Interconnections therebetween are appropriately formed.

5 illustrates a stacked die device made of stacked subpackages in accordance with an embodiment of the present invention. Stacked die device 500 shown in FIG. 5 includes three subpackages 505a, 505b, and 505c, which may be stacked die subpackages generated in accordance with one embodiment of the present invention. Subpackage 505a includes substrate 510a with conductive balls 520. Subpackage 505a has dies 530a and 530b encapsulated with encapsulant 545a. Top portion 551a of subpackage interconnects 550a is exposed and forms an interconnect with land pads 521b formed on the bottom surface of subpackage 505b. Subpackage 505b has dies 530c and 530d attached to substrate 510b, encapsulated with encapsulant 545b. Top portion 551b of subpackage interconnects 550b is exposed and forms an interconnect with land pads 521c formed on the bottom surface of subpackage 505c. Subpackage 505c has dies 530e and 530f attached to substrate 510c, encapsulated with encapsulant 545c. The entire subpackage interconnects 550c are also encapsulated. Stacked die device 500 is also exemplary, as each of the stacked subpackages of stacked die device 500 is exemplary. Stacked die devices may have any reasonable number of stacked subpackages and each subpackage may have one or any number of stacked die packages.

General Problems

Embodiments of the present invention provide methods and apparatuses for producing a stacked die device having a stacked subpackage configuration. Various embodiments of the invention have been described including specific features or processes. In alternative embodiments of the invention, the features or processes may be changed. For example, although generally described as conductive metal balls, the subpackage interconnects can be any suitable material or form in accordance with alternative embodiments of the present invention.

Embodiments of the present invention have been described as a process having various operations. Such tasks may be described in an illustrative and most basic form, but in accordance with various embodiments it is possible for the tasks to be added to, deleted from, or altered in the process without departing from the basic scope of the invention. For example, in the process 400 described above with respect to FIG. 4, the task of covering the subpackage interconnects can be omitted. For such a process, to expose the subpackage interconnects, the top portion of the subpackage interconnects can be exposed by dragging a squeegee across the surface of the applied encapsulant. In such an embodiment, the limited encapsulant material remaining on the surface of the subpackage interconnects is due to the increased viscosity of the encapsulant and the wetting between the corresponding land pads and the subpackage interconnects of the connection subpackage. It will flow off the surface during reflow. Thus, any residual encapsulant does not affect proper interconnect formation.

According to one embodiment of the invention, a non-flow underfill material may be applied prior to reflow for better connection formation and thermal energy dissipation. In an alternative embodiment of the invention, the underfill material may be applied after the subpackages are connected.

Although the present invention has been described in terms of some embodiments, those skilled in the art will recognize that the present invention is not limited to the described embodiments but may be practiced with modifications and adaptations within the spirit and scope of the appended claims. Will recognize that. Thus, the specification is to be regarded as illustrative rather than restrictive.

Claims (29)

An apparatus for providing a stacked die device, A first substrate having a top surface and a bottom surface; A set of one or more dies attached to the top surface of the first substrate and extending a first distance over the top surface; One or more interconnections formed on the top surface of the first substrate and extending a second distance over the top surface; A planar encapsulant disposed over the top surface of the first substrate and extending a third distance over the top surface, the third distance being longer than the first distance and shorter than the second distance such that the one or more dies and one The bottom of the at least one interconnect is encapsulated and the top of the at least one interconnect is exposed; And A second substrate over the first substrate, the second substrate having a bottom surface and at least one conductive pad formed on the bottom surface of the second substrate, each conductive pad being downward from the bottom surface of the second substrate; Does not extend to the third distance but extends to the second distance − Device comprising a. The method of claim 1, Wherein the one or more dies are attached to each other in a stacked die configuration and a top portion of the top die extends above the top surface by the first distance. The method of claim 1, Said at least one die having connecting wires, said connecting wires extending a fourth distance over said top surface, said fourth distance being shorter than said first distance such that said connecting wires are encapsulated. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, Wherein said encapsulant is a thermoset material. The method of claim 1, The second substrate further has a top surface and a second set of one or more dies attached to the top surface of the second substrate, each conductive pad corresponding to one of the one or more interconnections formed on the top surface of the first substrate. Device electrically connected with the interconnect. Claim 6 was abandoned when the registration fee was paid. The method of claim 4, wherein The thermosetting material is an epoxy. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 3, One or more connecting wires of the die comprise wire-bonds. The method of claim 1, At least one die having a logic processor device implemented thereon. A system for providing a stacked die device, First sub-package; And A second subpackage stacked on and electrically connected to the first subpackage Including, Each of the first subpackage and the second subpackage comprises a substrate, the substrate having one or more dies attached to an upper surface of the substrate and one or more interconnects formed over the upper surface of the substrate, the first subpackage Each of the package and the second subpackage further includes an encapsulant disposed on the top surface of the substrate, such that the one or more dies and the bottom of the one or more interconnects are encapsulated and the top of each of the one or more interconnects. Is exposed, the encapsulant of the first subpackage has a top surface of a plane, wherein an upper portion of each of the one or more interconnections of the first subpackage extends above a top surface of the plane and the second sub- The substrate of the package has one or more conductive pads formed on the bottom surface, each conductive pad having the second standing It extends downward from the bottom surface of the substrate of the package that is not to extend to the upper surface of the flat contact the corresponding interconnection of the first sub-package, system. The method of claim 9, Each conductive pad is electrically connected to a corresponding one of the one or more interconnections formed on the top surface of the substrate of the first subpackage. The method of claim 10, One or more additional subpackages sequentially stacked over the second subpackage, each additional subpackage comprising a substrate, the substrate formed on the top surface of the substrate and one or more dies attached to the top surface of the substrate; Having at least one interconnect, each additional subpackage further comprises an encapsulant disposed over the top surface of the substrate, such that the at least one die and the bottom of the at least one interconnect are encapsulated and the at least one interconnect Each top is exposed, each additional subpackage comprising one or more conductive regions formed on a bottom surface, each conductive region corresponding to one or more of the one or more interconnections formed on the top surface of the substrate of the immediately preceding subpackage. A system, electrically connected to the interconnect. The method of claim 9, The one or more dies are attached to each other in a stacked die configuration. The method of claim 9, Said at least one die having connecting wires, said connecting wires being fully encapsulated by said encapsulant. Claim 14 was abandoned when the registration fee was paid. The method of claim 13, And the connecting wires of one or more of the dies include wire bonds. Claim 15 was abandoned upon payment of a registration fee. The method of claim 9, The encapsulant is a thermoset material. Claim 16 was abandoned upon payment of a setup registration fee. The method of claim 15, The thermosetting material is an epoxy. The method of claim 9, One or more dies of the dies implement a logic processor device. A method for providing a stacked-die device, Forming at least one interconnection on said top surface of said substrate extending a first distance above said top surface; Attaching a set of one or more dies to the top surface of the substrate extending a second distance above the top surface; Positioning a stencil over the substrate, the stencil having a pattern corresponding to one or more interconnections formed on the top surface, wherein the stencil measures the amount of encapsulant formed on any of the one or more interconnections. Decrease-; And Applying an encapsulant on the top surface of the substrate while the stencil is over the substrate such that the encapsulant extends over the top surface by a third distance shorter than the first distance and longer than the second distance. Including, Wherein the at least one die and a bottom of the at least one interconnect are encapsulated, and a top of the at least one interconnect is exposed. delete The method of claim 18, The encapsulant is a thermoset material. The method of claim 20, Said thermosetting material is an epoxy. The method of claim 21, Reducing the viscosity of the thermal epoxy prior to applying a thermal epoxy to the top surface of the substrate. The method of claim 22, Reducing the viscosity of the thermal epoxy comprises adding a solvent to the thermal epoxy. The method of claim 18, Stacking a second substrate having a top surface and a bottom surface over the substrate, the second substrate having a second set of one or more dies attached to the top surface of the second substrate, and And one or more conductive regions formed on the bottom surface, each conductive region corresponding to an interconnection of one of the one or more interconnections formed on the top surface of the substrate. The method of claim 24, Performing a reflow process to form an electrical connection between each interconnect formed on said top surface of said substrate and each corresponding conductive region formed on said bottom surface of said second substrate. The method of claim 18, Applying a squeegee over the encapsulant to reduce the amount of encapsulant formed on any of the one or more interconnects extending over the top surface of the substrate by a distance greater than the second distance. The method further comprises a step. The method of claim 18, Said at least one die having connecting wires, said connecting wires being fully encapsulated by said encapsulant. Claim 28 was abandoned upon payment of a registration fee. The method of claim 27, Wherein the connecting wires of one or more of the dies comprise wire bonds. Claim 29 was abandoned upon payment of a set-up fee. The method of claim 18, At least one of the dies implements a logic processor device.

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