KR100863373B1 - Memory system and memory card - Google Patents

Abstract

The memory system includes a plurality of nonvolatile memory chips CHP1 and CHP2 each having a plurality of memory banks BNK1 and BNK2 independently capable of memory operation, and a memory controller 5 that can individually access and control the nonvolatile memory chips. ). The memory controller may selectively instruct simultaneous write operations or interleaved write operations for a plurality of memory banks of the nonvolatile memory chip. Therefore, in the simultaneous recording operation, a significantly long write operation with respect to the write setup time can be completely parallelized. In the interleaved write operation, the write operation following the write setup can be partially superimposed on the write operation of another memory bank, and as a result, In addition, the number of nonvolatile memory chips can be relatively small in a memory system having a fast write process.

Description

Memory system and memory card {MEMORY SYSTEM AND MEMORY CARD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system or a memory card using a plurality of chips of nonvolatile memory such as a flash memory having a multi-bank. The present invention relates to a useful technique applied to a memory card such as a multimedia card.

The flash memory can store information by increasing its threshold voltage by injection or withdrawal of electrons into a floating gate or the like of a memory cell transistor. In this specification, a state where the threshold voltage of the memory cell transistor is low is referred to as an erase state and a high state is referred to as a write state. When information storage is performed in accordance with the write data, a high voltage is applied to the memory cell transistor in the erased state according to the logic value of the write data. It takes a relatively long processing time to obtain the desired threshold voltage for the memory cell transistor.

In a flash memory card equipped with a conventional flash memory chip and a memory controller, an interleaved recording operation is employed to speed up the recording operation in appearance. For example, a plurality of flash memory chips are mounted on a card substrate, one flash memory chip is instructed to start a write operation, and then another flash memory is instructed to start a write operation. By this operation, a large number of flash memory chips must be mounted in order for the write operation time not to be visible. In other words, when a write setup time for supplying a write address or write data to one flash memory chip to instruct a write operation and a write operation write time for write data in the memory address indicated by the write setup are compared, The recording operation time is much longer. As this write operation time is filled, if write setups for other flash memories are performed sequentially, the write operations for the majority of flash memory chips can be partially parallelized, and the write operation times of many flash memory chips are invisible.

However, in the conventional method of performing interleaved recording in units of flash memory, since a large number of flash memory chips must be mounted in order for the write operation time to be invisible, the size of the memory card is increased and the cost is increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory system and a memory card capable of speeding up the recording speed without mounting many flash memory chips so as to increase the size of the memory card or increase the cost.

The above and other objects and novel features of the present invention will be apparent from the description of the specification and the accompanying drawings.

(Initiation of invention)

[1] The memory system according to the present invention includes a plurality of nonvolatile memory chips each having a plurality of memory banks capable of independently memory operation, and a memory controller capable of individually controlling access to the nonvolatile memory chips. The memory controller can selectively instruct simultaneous write operations or interleaved write operations for a plurality of memory banks of the nonvolatile memory chip.

According to the above means, simultaneous write operation or interleaved write operation for a plurality of memory banks is possible in units of chips having a multibank. In the simultaneous write operation, a significantly long write operation can be completely parallelized to the write setup time. In an interleaved write operation, the write operation following the write setup of one memory bank is shifted sequentially, and the data is partially overlapped with the write operation of another memory bank. do. This makes it possible to relatively reduce the number of nonvolatile memory chips in forming a memory system with a fast write process.

The simultaneous write operation is a write operation that starts at the same timing for the plurality of memory banks, for example, after a plurality of serial instructions of the write operation in which the memory banks are designated. The interleaved write operation is, for example, a write operation that starts a new write operation in response to a write instruction specifying another memory bank during the already started write operation.

In one preferred aspect of the present invention, the memory controller distinguishes between the instruction of the simultaneous write operation and the instruction of the interleaved write operation by a type of command code for instructing a write operation accompanying the write address information and the write data information. Good to do. It is also possible to indicate by register setting, but in comparison with this, a special control type can be omitted. The write command may be supplied in addition to the write address information and the write data information.

In a preferred embodiment of the present invention, when each of the nonvolatile memory chips has a chip select terminal and a plurality of other access terminals, a connection form that allows the memory controller to individually access control the plurality of nonvolatile memory chips. In order to easily obtain the?, The memory controller includes a chip select signal output terminal individually connected to the chip select terminal of each nonvolatile memory chip, and a plurality of access information commonly connected to the access terminal of each nonvolatile memory chip. You just need to have a terminal.

[2] A memory system according to another aspect of the present invention is capable of individually controlling access to a plurality of nonvolatile memory chips having a plurality of memory banks each independently capable of memory operation, and to the plurality of nonvolatile memory chips. It includes a memory controller. The memory controller is capable of instructing interleaved writing of memory banks in the nonvolatile memory chip sequentially for each of the nonvolatile memory chips.

The interleaved write instruction is, for example, a write operation instruction for starting a new write operation in response to a write instruction that designates another memory bank during the already started write operation.

According to the above means, an interleaved write operation for a plurality of memory banks is possible in units of chips having a multibank. In the interleaved write operation, the write operation subsequent to the write setup of one memory bank is shifted sequentially and partially overlapped with the write operation of another memory bank to be parallelized. This makes it possible to comparatively reduce the number of nonvolatile memory chips to form a memory system with a fast writing process.

[3] A memory system according to another aspect of the present invention includes a plurality of nonvolatile memory chips each having a plurality of memory banks independently operable to memory, and a memory controller capable of individually controlling access to the nonvolatile memory chips. It includes. The memory controller can instruct simultaneous writing for each of the nonvolatile memory chips sequentially between memory banks in the nonvolatile memory chip.

The simultaneous write instruction is, for example, a write operation instruction for starting a write operation for a plurality of memory banks at the same timing after a plurality of serial instructions of a write operation in which a memory bank is designated.

According to the above means, simultaneous write operation for a plurality of memory banks is possible in units of chips having a multibank. In the simultaneous recording operation, a significantly long recording operation with respect to the recording setup time can be fully parallelized. This makes it possible to comparatively reduce the number of nonvolatile memory chips to form a memory system with a fast writing process.

[4] A memory system according to another aspect of the present invention includes a plurality of flash memory chips each having a plurality of memory banks capable of independently operating memory, and a memory controller capable of individually accessing and controlling the plurality of flash memory chips. And an SRAM connected to the memory controller. The SRAM can temporarily store write data for a flash memory chip. The memory controller selects to instruct interleaved writes for the memory banks in the flash memory chips sequentially for each of the flash memory chips, and to instruct simultaneous writes for the memory banks in the flash memory chips sequentially for each of the flash memory chips. It is possible.

When the transfer speed of the write data transferred from the host system is faster than the write operation speed on the data to the flash memory chip by interleaved write or simultaneous write, the SRAM is used as the write data buffer. If the write speed is faster than the data transfer speed, it is not necessary to use the SRAM as a write data buffer.

[5] A memory system according to another aspect of the present invention includes a plurality of flash memory chips each having a plurality of memory banks capable of independently memory operation, and a memory controller for access control of the flash memory chips using an access command. It includes. The memory controller outputs a first command code, address information of a memory bank subsequent to the first command code, and a second command code subsequent to address information of the memory bank, and, for the memory bank specified by the address information, The memory operation is started for each input of the second command code. Further, the first command code, the address information of the memory bank following the first command code, the third command code following the address information of the memory bank, the address address information of the memory bank subsequent to the third command code, and the memory bank A second command for outputting a second command code subsequent to the address information, and for a plurality of memory banks specified by a plurality of address information divided by the third command between the first command code and the second command code; In response to the code input, memory operation is started simultaneously. The former is the interleaved recording operation, and the latter is the simultaneous recording operation.

The first command code is a command code for supplying a type of a recording operation, the second command code is a command code for instructing the start of a recording operation, and the third command code is a command code indicating that address information follows.

[6] A memory card according to the present invention includes an external connection terminal connected to a card substrate, an external interface circuit connected to the external connection terminal, a memory controller connected to the external interface circuit, and separately accessed by the memory controller. It has a plurality of flash memory chips under control. The flash memory chips each have a plurality of memory banks each capable of independently memory operation. The memory controller may selectively instruct simultaneous write operations or interleaved write operations for a plurality of memory banks of the flash memory chip.

SRAM may be mounted as a write data buffer. When applied to a multimedia card or the like, the external connection terminal includes a 1-bit data input / output terminal, a 1-bit command terminal, a power supply voltage terminal, a ground voltage terminal of a circuit, and a clock terminal.

Also in this memory card, similarly to the above, in the simultaneous recording operation, a significantly long recording operation can be completely parallelized to the recording setup time, and in the interleaved recording operation, the recording operation following the recording setup of one memory bank is shifted sequentially and the other Since the memory bank can be partially overlapped and parallelized, the number of nonvolatile memory chips can be relatively small to form a memory card with a fast recording process, and the cost of the memory card can be suppressed to increase the speed of the recording operation. It can be realized.

[7] A nonvolatile semiconductor memory device according to the present invention includes a memory controller and at least one nonvolatile memory. The memory controller issues a write instruction command containing address information indicating an address to which information is to be written, for the one or more nonvolatile memories. Among the nonvolatile memories, the first nonvolatile memory has a plurality of storage regions separated by addresses, and each of the storage regions can perform a memory access operation in parallel with other storage regions. The conventional memory controller issues a first write instruction command for instructing the writing of information to an address included in the first storage region of the first nonvolatile memory, and then in the first storage region. Before the write operation is completed, it is possible to issue a second write instruction command for instructing the writing of information to an address included in the second storage area of the first nonvolatile memory.

The nonvolatile memory has, for example, a plurality of memory elements, and in the writing operation of the nonvolatile memory, each memory element selected by selecting a group of memory elements in accordance with an address indicated by the write instruction command is selected. It is to change the threshold voltage according to the information to be recorded in.

The write operation of the nonvolatile memory may include, for example, a first operation for changing a threshold voltage of a memory cell, and whether the threshold voltage of each memory cell has changed to a threshold voltage corresponding to the information to be written. And a second operation for confirming that if the threshold voltage of at least one memory cell does not change to a threshold voltage corresponding to information to be written after the second operation. Do it.

The plurality of memory devices may be, for example, threshold voltages included in threshold voltage distributions corresponding to information to be written among three or more threshold voltage distributions.

[8] A nonvolatile memory device according to the present invention instructs a first terminal used for inputting / outputting data, a second terminal used for inputting an operation instruction command, and timings of inputting / outputting of data and input of an operation instruction command. It has a third terminal used for the input of the clock. A control unit for controlling the operation according to the operation instruction command input from the second terminal, and one or more nonvolatile memories for storing or reading data under the control of the control unit. The nonvolatile memory has a plurality of memory elements corresponding to an address, and the plurality of memory elements are classified into a plurality of groups, and the data storage operation in another group can be started during the data storage operation of the first group. Done.

The controller, for example, divides data input from the first terminal into predetermined bytes, stores first data in the first group of a first nonvolatile memory, and stores second data in the first group. Instructs storage to a second group of nonvolatile memories.

In the above, the control unit issues, for example, a storage instruction command for instructing a storage operation to the nonvolatile memory. The storage instruction command includes a first command indicating that the command is a storage instruction command, address information indicating a memory element to store data, data to be stored, and a second command instructing to start a storage operation. do.

In the above description, the control unit may include, for example, the first command, a first address indicating the memory element of the first group of the first nonvolatile memory, the first data, and the second command. After issuing, a second address indicating the first command, the memory device of the second group of the first nonvolatile memory, the second data, and the second command are issued.

In the above, the control unit is further configured to issue the first command, a first address indicating the memory element of the first group of the first nonvolatile memory, and the first data after issuing the first data. A first command, a second address indicating the memory element of the second group of the first nonvolatile memory, the second data, and the second command are issued.

In addition, by changing the viewpoint, the controller divides, for example, data input from the first terminal into predetermined bytes, instructs storage of first data in the first group of the first nonvolatile memory, and stores the second data. The storage instruction is given to the first group of the second nonvolatile memory.

In the above description, the control unit may include, for example, the first command, a first address indicating the memory element of the first group of the first nonvolatile memory, the first data, and the second command. After issuing, issuing the first command, a second address indicating the memory element of the first group of the second nonvolatile memory, the second data, and the second command.

In the above description, the control unit is configured to issue the first command, a first address indicating the memory device of the first group of the first nonvolatile memory, and the first data after issuing the first data. A first command, a second address indicating the memory element of the first group of the second nonvolatile memory, the second data, and the second command are issued.

1 is a block diagram illustrating a memory card as an example of the memory system according to the present invention.

2 is an exemplary timing chart of a setup operation (write setup operation) and a memory operation (write operation) for writing.

3 is an exemplary timing chart of one bank operation for operating memory banks one by one in an operation selected flash memory chip.

4 is an exemplary timing chart of two bank simultaneous recording.

5 is an exemplary timing chart of an interleaved recording operation.

6 is an explanatory diagram illustrating the recording operation timing and the recording speed for each recording operation state.

Fig. 7 is an explanatory diagram illustrating a relationship between the number of memory banks and the writing speed in each of interleaved recording and simultaneous writing when N = 2K bytes, Tsetup = 100 mu sec, and Tprog = 1000 mu sec.

Fig. 8 is an explanatory diagram illustrating the write operation timing and the write operation speed when U 1 bank flash memory chips are used.

Fig. 9 is an explanatory diagram illustrating the simultaneous write operation timing and write operation speed when U S bank flash memory chips are used.                 

Fig. 10 is an explanatory diagram illustrating an interleaved write operation timing and write operation speed when U S bank flash memory chips are used.

FIG. 11 is an explanatory diagram illustrating a relationship between the number of chips and the number of memory banks at which the writing speed is maximum in each of the write operations of FIGS.

12 is a block diagram of a multimedia card to which the present invention is applied.

Fig. 13 is an explanatory diagram illustrating a recording operation mode and an operation timing of a one bank, one chip use mode.

Fig. 14 is an explanatory diagram illustrating a recording operation mode and an operation timing of the one bank two chip usage mode.

Fig. 15 is an explanatory diagram illustrating a recording operation form and an operation timing of a 2-bank simultaneous write 1 chip usage form.

Fig. 16 is an explanatory diagram illustrating a recording operation type and an operation timing of a two bank simultaneous recording two chip usage type.

Fig. 17 is an explanatory diagram illustrating a recording operation form and an operation timing of a 2-bank interleaved write 1 chip use form.

18 is an explanatory diagram illustrating a recording operation form and an operation timing of a 2-bank interleaved recording 2-chip usage form.

19 is a block diagram showing an example of a flash memory chip as a whole.

20 is a block diagram illustrating an example of a memory bank.

21 is an explanatory diagram illustrating a cross-sectional structure of a nonvolatile memory cell.                 

Fig. 22 is a circuit diagram illustrating a portion of an AND-type memory cell array.

Fig. 23 is an explanatory diagram illustrating a voltage application state of erase and write to a memory cell.

24 is an explanatory diagram illustrating a command of a flash memory.

Best Mode for Carrying Out the Invention

<< Memory System >>

Fig. 1 shows a memory card as an example of the memory system according to the present invention. The memory card 1 shown in the figure has a plurality of nonvolatile memory chips, for example, having a plurality of memory banks BNK1 and BNK2 each capable of independently memory operation on the card substrate 2, for example, two. Flash memory chips CHP1 and CHP2, a memory controller 5 that can be individually accessed and controlled for the flash memory chips CHP1 and CHP2, and an SRAM 6 connected to the memory controller 5. The SRAM 6 can be used as a data buffer for temporarily storing write data for the flash memory chips CHP1 and CHP2. The memory controller 5 can selectively instruct simultaneous or interleaved write operations for the memory banks BNK1 and BNK2 of the flash memory chips CHP1 and CHP2.

Details of the flash memory chips CHP1 and CHP2 will be described later. Here, a function for responding to the instruction of the simultaneous write operation or the interleaved write operation will be described in advance. Each of the flash memory chips CHP1 and CHP2 has a chip select terminal (/ CE), a reset terminal (/ RES), a write enable terminal (/ WER), an output enable terminal (/ OE), and command data enable. It has a terminal (/ CDE), a serial clock terminal (SC), an input / output terminal (I / O [0: 7]) and a ready / busy terminal (R / B). The input / output terminals I / O [0: 7] are used for data input / output, address input, and command input. Command input from the input / output terminals I / O [0: 7] is synchronized with the change of the command enable signal / CDE. The data input / output is synchronized with the serial clock SC. The input of the address information is synchronized with the change of the write enable signal / WE.

The operation selection for the flash memory chip CHP1 is indicated by a chip select signal / CEO at the memory controller 5, and the operation selection for the flash memory chip CHP2 is a chip select signal at the memory controller 5. It is indicated by (/ CE1). The other interface terminals of the flash memory chips CHP1 and CHP2 are commonly connected to the corresponding terminals of the memory controller 5 in common with the corresponding ones.

The memory operation contents for the flash chips CHP1 and CHP2 selected by the chip enable signals / CEO and / CE1 are command and address information supplied through the input / output terminals I / O [0: 7], and If necessary, it is indicated by recording data. The address information includes designation information of the memory banks BNK1 and BNK2, access address information in the designated memory bank, and the like. An operation for instructing the contents of this memory operation is called a setup operation. Since the setup operation requires an interface with the outside, it must be performed serially in each memory bank. Operation The selected flash chips CHP1 and CHP2 perform memory operations such as writing, erasing or reading of the flash memory cells in accordance with the contents instructed in the setup operation. The memory operation can be performed independently for each bank according to the access control information supplied in the setup operation. Thus, memory operations can be parallelized between memory banks.

As an example, timing charts of a setup operation (write setup operation) and a memory operation (write operation) for recording are illustrated as an example. "10H" input in the write setup operation is a write command, "SA (1), SA (2)" is a sector address, "A (1), CA (2)" is a column address, and "Din1-DinN" is a write. Data "40H" is a write start command.

In Fig. 2, the recording operation time (recording operation time Tprog) is significantly longer than the recording setup time (recording setup time Tsetup). The data amount of the recording data Din1 to DinN is generally large, and the recording setup time Tsetup is proportional to the amount of recording data input to the SC synchronization.

3 illustrates a timing chart of one bank operation in which memory banks are operated one by one in an operation-selected flash memory chip. The recording data is Din1 to DinN. The write operation is performed serially for each of the memory banks BNK1 and BNK2.

4 shows a timing chart of two bank simultaneous recording. The input of a command or the like takes about twice as much as Tsetup, but the operation time of the two memory banks BNK1 and BNK2 ends in a parallel operation and therefore the time Tprog.

5 is a timing chart of an interleaved recording operation. The two bank simultaneous write operation causes both memory banks to be simultaneously written in parallel when there is an instruction of a write operation specifying another memory bank continuously before the start of the memory operation in response to the instruction of the write operation specifying one memory bank. will be. On the other hand, the interleaved write operation means an operation that enables the memory operation in response to an instruction of a write operation in which another memory bank is designated among memory operations in response to an instruction of a write operation in which one memory bank is designated. The time Tx is the time from the issuance of the command code "40H" for instructing the start of the write operation to the issuance of the sector address in the next write operation, and the time can be substantially close to zero.

The command codes of the write access command in the write setup operation of Fig. 4 are " 10H ", " 41H " and " 40H ", and the command codes of the write access command in the write setup operation of Fig. 5 are " 10H " "," 40H ". If the time Tx of Fig. 5 is substantially zero, the write setup operation time for the two-bank parallel recording of Fig. 4 and the write setup operation time for the interleaved write operation of Fig. 5 become substantially the same. In short, the two-bank parallel simultaneous write operation time in FIG. 4 and the interleaved write operation time in FIG. 5 become 2Tsetup + Tprog in the shortest time. On the other hand, in the one bank operation of Fig. 3, the shortest time for writing to two memory banks BNK1 and BNK2 becomes 2Tsetup + 2Tprog.

As described above, the flash memory chips CHP1 and CHP2 are distinguished and instructed from parallel simultaneous write operations for the plurality of memory banks and interleaved write operations by command codes supplied in the setup operation. In addition, since the write or interleave write operation can be performed in parallel in the plurality of memory banks 3 and 4, it is possible to shorten the busy period by the write operation. In short, it is possible to speed up the processing for the instruction of the write operation from the memory controller 5.                 

After it is understood that the write processing can be speeded up by writing or interleaving write operations in parallel in the flash memory chips, the relationship between the number of memory banks and the write speed in one flash memory chip is summarized for each write operation state.

In Fig. 6, the recording operation timing and the recording speed are illustrated for each recording operation state. In Fig. 6, the recording unit of the recording operation is N bytes. The writing speed of one flash memory chip in the memory bank is N / (Tsetup + Tprog) [Bytes / sec].

In the case of simultaneously writing S memory banks in a flash memory chip having S memory banks, the writing speed is S · N / (S · TSetup + Tprog) [Bytes / sec].

The recording speed in the case of performing interleaved writing for S memory banks in a flash memory chip having S memory banks is divided by the magnitude relationship between (S-1) Tsetup and Tprog. In other words, when the setup operation is completed up to the memory banks BNK1 to BNKS, the case is divided in terms of whether or not the write operation of the memory bank BNK1 has already been completed. When (S-1) · Tsetup≥Tprog, the recording speed is N / Tsetup [Bytes / sec]. When (S-1) · Tsetup <Tprog, the recording speed is S · N / (Tsetup + Tprog) [Bytes / sec].

Fig. 7 illustrates the relationship between the number of memory banks of one flash memory in interleaved write and simultaneous write and the write speed described in Fig. 6 when N = 2K bytes, Tsetup = 100 mu sec, and Tprog = 1000 mu sec. In the case of interleaved writing, if the number of memory banks is increased to a certain value, the write operation speed does not change even if it is increased further. In the case of simultaneous recording, as the number of banks increases, the rate of increase of the recording operation speed gradually decreases. Where the number of banks is relatively small, the recording operation speeds of the interleaved recording and the simultaneous recording are almost the same.

Next, the relationship between the number of memory banks and the write speed in the plurality of flash memory chips is summarized for each write operation state.

Fig. 8 illustrates the write operation timing and write operation speed when U banks of 1 bank flash memory are used. This operation state is equivalent to the interleaved write operation state for one flash memory chip having U memory banks, and corresponds to the S bank interleaved write operation in FIG. When (U-1) Tsetup≥Tprog, the recording speed is N / Tsetup [Bytes / sec]. When (U-1) · Tsetup <Tprog, the recording speed is U · N / (Tsetup + Tprog) [Bytes / sec].

9 shows the simultaneous write operation timing and write operation speed when U S bank flash memory chips are used. This operation state corresponds to the processing of U times the S bank simultaneous recording operation in FIG. The recording speed at this time is divided by the magnitude relationship between S (U-1) Tsetup and Tprog. That is, when the setup operation is completed for the memory banks of all the chips CHP1 to CHPU, there are cases where the interleaving recording of all the memory banks BNK1 to BNKS on one chip CHIP1 has already been completed. Divided. When S (U-1) Tsetup≥Tprog, the recording speed is N / Tsetup [Bytes / sec]. When S (U-1) · Tsetup <Tprog, the recording speed is S · U · N / (S · Tsetup + Tprog) [Bytes / sec].

Fig. 10 illustrates the interleaved write operation timing and write operation speed when U S bank flash memory chips are used. This operation state is equivalent to the interleaved write operation state for one flash memory chip having S · U memory banks, and corresponds to the processing of U times the S bank interleaved write operation in FIG. The recording speed at this time is divided by the magnitude relationship between (S · U-1) · Tsetup and Tprog. That is, when the setup operation is performed for the memory banks of all the chips CHP1 to CHPU, the case is divided in terms of whether or not the interleaving recording of one memory bank BNK1 on one chip CHP1 has already been completed. Lose. When (SU-1) · Tsetup≥Tprog, the recording speed is N / Tsetup [Bytes / sec]. When (SU-1) · Tsetup <Tprog, the recording speed is S · U · N / (Tsetup + Tprog) [Bytes / sec].

8 to 10, in the case where the writing speed is N / Tsetup [Bytes / sec], i.e., the writing speed does not increase even if the number of chips is increased, the flash memory chip from the memory controller 5 is used. This means that setup data and recording data can be sent all the time. If the number of chips is increased, the number of chips at the boundary point that the recording speed does not increase is supplied, the minimum value of the area of the system where the recording speed is maximized in each recording operation state, that is, the minimum value of the number of flash memory chips. Fig. 11 illustrates the relationship between the number of chips and the number of memory banks at which the writing speed is maximum in each of the write operation states shown in Figs. In the figure, Tsetup = 100 µsec and Tprog = 1000 µsec. According to Fig. 11, when simultaneous recording in a memory chip or interleaving in a memory chip is performed by using a flash memory chip having a plurality of banks having a plurality of memory banks capable of independently operating memory, a flash required for constructing a memory system having a high writing speed can be obtained. It becomes clear that the number of memory chips can be reduced.

As described above, the selectable simultaneous write operation can completely parallelize a write operation that is significantly longer with respect to the write setup time for the multibank of the multichip, and in the selectable interleaved write operation, one memory bank is provided for the multibank of the multichip. The write operation subsequent to the write setup of &lt; RTI ID = 0.0 &gt; is &lt; / RTI &gt; This makes it possible to comparatively reduce the number of nonvolatile memory chips to form a memory system with a fast writing process.

The memory controller distinguishes the instruction of the simultaneous write operation from the instruction of the interleaved write operation according to the type of command code for instructing the write operation accompanying the write address information and the write data information. Although it is possible, in comparison with the register setting, a special control type can be omitted. The write command may be supplied in addition to the write address information and the write data information.

<< Application to Multimedia Card >>

12 illustrates a multimedia card to which the present invention is applied. The multimedia card 11 has a card dimension of 24 mm x 32 mm x 1.4 mm according to the specification by the standardization body. As the connection terminal, one connection terminal 13a for inputting the card select signal CS, one connection terminal 13b for inputting the command CMD, and a clock signal CLK are input to the card board 12. One connecting terminal 13c for inputting, one connecting terminal 13d for inputting and outputting data DAT, one connecting terminal 13e supplied with a power supply voltage Vcc, and two supplied with a ground voltage Vss. Has connection terminals 13f and 13g.

The card substrate 12 includes an interface driver 14, the memory controller 5, an SRAM 6, and flash memory chips CHP1 and CHP2. The memory controller 5 has an interface controller 15 and a memory controller 16. The interface controller 15 has a control logic circuit for host interface control, file control control and data transfer control. The interface control unit 15 receives a command supplied from the host system via the interface driver 14, decrypts it, and instructs the memory control unit 16 to operate. The memory control unit 16 receives the instruction and performs access control of file data for the flash memory chips CHP1 and CHP2. For example, the interface controller 15 temporarily stores write data supplied from the outside into the SRAM, and simultaneously writes the multi-bank of the multi-chip described above or writes the multi-bank of the multi-chip to the memory controller 16. Interleave recording is indicated. The memory control unit 16 supplies command codes and write data to the flash memory chips CHP1 and CHP2 in accordance with the instructions, and simultaneously records the multibanks of the multichips or interleaves the multibanks of the multichips. To control.

Here, the recording speed in various recording operation states in the multimedia card 11 will be described. The characteristics of the flash memory chips CHP1 and CHP2 are set to Tsetup = 100 mu sec, Tprog = 2000 mu sec, and 1 sector, which is a recording unit corresponding to N described above, is 2 k bytes. At this time, since data is serially input from the host system to the data terminal DAT at a period of 50 nsec, 2k bytes of write data are input to the data terminal DAT, which takes 2048 x 8 x 50 x 0.82 msec. .

In Fig. 13, the write operation timing of the operation mode (using one bank and one chip) using only one memory bank of one flash memory chip is illustrated. In this case, the data transfer rate from the host system to the memory card is 0.67 Mbytes / sec.

In Fig. 14, the write operation timing of an operation mode (one bank and two chip usage forms) using one memory bank for each of two flash memory chips is illustrated. In this case, the data transfer rate from the host system to the memory card is 1.34 Mbytes / sec.

Fig. 15 illustrates a write operation timing of an operation mode (two bank simultaneous write one chip usage mode) for simultaneously writing two memory banks for one flash memory chip. In this case, the data transfer rate from the host system to the memory card is 1.04 Mbyte / sec.

Fig. 16 illustrates a write operation timing of an operation mode (two bank simultaneous write two chip use mode) for simultaneously writing two memory banks to two flash memory chips. In this case, the data transfer rate from the host system to the memory card is 2.08 Mbytes / sec.

In Fig. 17, the write operation timing of the operation mode for interleaving two memory banks for one flash memory chip (using the two bank interleaved write one chip) is exemplified. In this case, the data transfer rate from the host system to the memory card is 1.24 Mbytes / sec.

Fig. 18 illustrates a write operation timing of an operation type (two bank interleaved write two chip usage type) in which two memory banks are interleaved written for each of two flash memory chips. In this case, the data transfer rate from the host system to the memory card is 2.38 Mbytes / sec.

In the operation speed results for each of the operation modes shown in FIGS. 13 to 18, two operation modes of the operation mode using the two bank simultaneous recording two chips shown in FIG. 16 and the operation mode using the two bank interleaved recording two chips shown in FIG. In this case, the data transfer rate from the host system side can be made relatively high. The operation mode of two-bank simultaneous recording using two chips shown in FIG. 16 is one form of S-bank simultaneous recording for a plurality of chips of FIG. 9, and the operation mode of using two-bank interleaved recording two chips shown in FIG. One form of S-bank interleaved recording. Therefore, by adopting the simultaneous write operation or the interleaved write operation for the multi-bank of the multichip, it becomes more apparent that a memory system having a faster write process can be constituted.

Whether simultaneous recording or interleaved recording is adopted is arbitrary depending on the host system's response. In the case of Fig. 18, the processing speed is the highest, but the host system must continuously send write commands and write data. In the case of Fig. 16, a busy state occurs slightly on the memory card side and the processing speed decreases slightly. However, in the busy state, the host system has the freedom to perform other processing.

<< Overall Configuration of Flash Memory >>

19 shows an example of the flash memory chip CHP1 as a whole.                 

The flash memory chip CHP1 includes a plurality of memory banks BNK1 and BNK2, each of which can be independently operated on a single semiconductor substrate (semiconductor chip) 22 such as single crystal silicon, for example. A controller 25 for controlling memory operations for the memory banks BNK1 and BNK2, status registers 26 and 27 provided for each of the memory banks BNK1 and BNK2, an interface controller 28 to the outside, and a memory There are relief circuits 29 and 30, an address buffer 31, an address counter 32, and an internal power supply circuit 33 allocated to each of the banks BNK1 and BNK2. The control unit 25 includes a command decoder 40, a CPU (central processing unit), and a processor (hereinafter, simply referred to as a CPU) 41 having a working program memory (PGM) thereof, and a data input / output control circuit 42. Have

The input / output terminals I / O [7: 0] of the flash memory chip CHP1 are used for address input, data input / output, and command input. The X address signal input from the input / output terminals I / O [7: 0] is supplied to the X address buffer 31 through the interface control unit 28, and the input Y address signal is Y through the interface control unit 28. It is preset to the address counter 32. The command input from the input / output terminals I / O [7: 0] is supplied to the command decoder 40 through the interface control unit 28. The write data to be supplied to the memory banks BNK1 and BNK2 from the input / output terminals I / O [7: 0] are supplied to the data input / output control circuit 42 through the interface control unit 28. Read data from the memory banks BNK1 and BNK2 is supplied from the data input / output control circuit 42 to the input / output terminals I / O [7: 0] through the interface control unit 28. In addition, the signal input / output from the input / output terminal I / O [7: 0] is also called signal I / O [7: 0] for convenience.                 

The interface control unit 28 is an access control signal, and the chip enable signal / CE, the output enable signal / OE, the write enable signal / WE, the serial clock signal SC, and the reset signal are described above. Input (/ RES) and command enable signal (/ CDE). The symbol / immediately preceding the signal name means that the signal is low-enabled. The interface control unit 28 controls the signal interface function and the like with the outside in accordance with the state of those signals.

Each of the memory banks BNK1 and BNK2 has a plurality of nonvolatile memory cells capable of rewriting storage information. Some of the nonvolatile memory cells become relief (redundant) memory cells for replacing defective memory cells. The relief circuits 29 and 30 determine whether an address of a defective memory cell to be replaced by a relief memory cell is programmed with a programmable circuit (not shown) and whether the programmed address to be saved is designated as an access address. It has an address comparator (not shown). An X address signal for selecting nonvolatile memory cells from the memory banks BNK1 and BNK2 is output from an address buffer 31 and a Y address signal for selecting nonvolatile memory cells from the memory banks BNK1 and BNK2. Is output from the address counter 32. The X address signal and the Y address signal are supplied to the rescue circuits 29 and 30. When the address is to be saved, the address is replaced, and when the address is not to be saved, through the memory banks BNK1 and BNK2. Is supplied.

Although each of the memory banks BNK1 and BNK2 is not particularly limited, as illustrated in FIG. 20, the memory cell array 50, the X address decoder 51, the Y address decoder 52, and the Y switch circuit ( 53, the sense latch circuit 54, the data latch circuit 55, and the like. The memory cell array 50 has a plurality of nonvolatile memory cells that can be electrically erased and written. For example, as illustrated in FIG. 21, the nonvolatile memory cell MC is formed by floating a source S and a drain D formed in a semiconductor substrate or a memory well SUB and an oxide film in a channel region. The gate FG and the floating gate FG have a control gate CG superimposed through an interlayer insulating film. In the case of the AND-type array illustrated in FIG. 22, the memory cell array 50 includes the selected MOS transistor M1 on the main bit line MBL. The drain of the nonvolatile memory cell MC is coupled to the negative bit line SBL. The source of the nonvolatile memory cell MC sharing the sub bit line SBL is commonly connected to the source line SL through the second selection MOS transistor M2. The first select MOS transistor M1 is switched controlled by the bit line control line SDi in the row direction unit, and the second select MOS transistor M2 is controlled by the source line control line SSi in the row direction unit.

The X address decoder 51 of FIG. 20 decodes an X address signal and selects a word line WL, a bit line control line SDi, and a source line control line SSi in accordance with a specified memory operation. . The Y address decoder 52 decodes the Y address signal output from the address counter 32 and generates a switching control signal of the Y switch circuit 53 for bit line selection. The data latch circuit 55 has a function as a data buffer for temporarily holding write data input in units of bytes from the outside. The sense latch circuit 54 senses and holds the memory information read from the nonvolatile memory cell, and also holds the write control data for the write operation supplied from the data latch circuit 55.

As shown in Fig. 23, erasing of the memory cell is performed in batch erase in word line units (also in one sector unit), -17 V is applied to the selected word line, and 0 V is applied to the unselected word line, and the source line is erased. Becomes 0V.

As shown in Fig. 23, 17V is written to the write select word line, 0V is applied to the write select bit line, and 6V is applied to the write non-select bit line as shown in FIG. As the write high voltage application time increases, the threshold voltage of the memory cell increases. Whether 0V or 6V is applied to the bit line is determined by the logic value of the write control information latched in the sense latch circuit.

The read operation to the memory cell is not particularly limited, but the read select word line is set to 3.2V, the source line is connected to the ground voltage of the circuit, 1.0V is supplied to the bit line through the sense latch circuit, and the memory The storage information is read in accordance with the change in the bit line potential with or without the current flowing from the bit line to the source line according to the threshold voltage of the cell.

The bit line selected by the Y address decoder 52 is conducted to the data input / output control circuit 42. The connection between the data input / output control circuit 42 and the input / output terminals I / O [7: 0] is controlled by the interface control unit 28.

The internal power supply circuit 33 shown in Fig. 19 generates and supplies various operating power sources for writing, erasing, verifying, reading, and the like to the memory banks BNK1 and BNK2.

The command decoder 40 and the CPU 41 simultaneously record the multi-bank using the above-described multichip and use the multichip in accordance with an access command (simply referred to as a command) supplied from the interface control unit 28 or the like. Overall control of memory operations such as interleaved writing for multibanks.

The command is not particularly limited, but includes single or plural command codes and address information and data information necessary for executing the command along a predetermined format. Data information such as write data included in the command is supplied to the data input / output control circuit 42. The address information included in the command is supplied to the address buffer 31 and the address counter 32 if necessary. The memory banks BNK1 and BNK2 are mapped to different memory addresses, respectively, and the X address signal supplied to the address buffer 31 is positioned as a sector address that designates one sector area in units of 2048 bits, for example. In particular, part of the information of the X address signal, for example, the most significant address bit Am, is regarded as memory bank designation information indicating a target memory bank of the memory operation and is supplied to the command decoder 40. The command decoder 40 instructs the CPU 41 to target the memory bank specified in the memory bank designation information as the memory operation. The Y address signal supplied to the address counter 32 specifies the position in units of 8 bits with respect to 2048 bits of data of the sector address specified in the X address signal. In the initial state of the memory operation, the address counter 32 is reset to the initial value "0". When a Y address signal is supplied to this, the value becomes a preset value of the address counter 32. The Y address counter 32 uses an initial value or a preset value as a starting address, and outputs sequentially incremented Y address signals to the memory banks BNK1 and BNK2.

The command decoder 40 of FIG. 19 decodes the command code included in the command, determines the memory bank to be operated by the memory bank designation information Am, and supplies the decryption result and the determination result to the CPU 41. FIG. . The CPU 41 controls the operation of the memory banks BNK1 and BNK2 by supplying the access control signals CNT1 and CNT2 to the memory banks BNK1 and BNK2 to be operated on the basis thereof. When the memory operation is erased or written, the application of the high voltage is progressed step by step, and the BarriPy operation is performed at each step, and the BarriPy result information VFY1 and VFY2 are returned to the CPU 41. The CPU 41 applies the high voltage of the next step by the access control signals CNT1 and CNT2 when the barrifi result information VFY1 and VFY2 means not reaching the required threshold voltage state. To indicate. Even when the time-out occurs, the CPU 41 fails due to fail pass information FP1 and FP2 when the result of the baripai result information VFY1 and VFY2 indicates that the threshold voltage state is not reached. Is supplied to the status registers 26 and 27. The command decoder 40 outputs the operation mode information MD1 and MD2 to the status registers 26 and 27 based on the operation indicated by the command supplied at that time. The status registers 26 and 27 determine the fail path factors notified by the fail path information FP1 and FP2 as the operation mode information MD1 and MD2, and set the fail or path state to the corresponding register bits. do. The command decoder 40 inputs the status information ST1 and ST2 held by the status registers 26 and 27, and determines whether or not to accept a new input command with reference thereto. For example, when the memory bank BNK1 is a write fail, reception of an access command specifying the memory bank is made possible only for a predetermined command such as a write retry.

The status registers 26 and 27 hold information representing the state of the memory operation for each memory bank. The contents of the two status registers 26 and 27 can be read from the input / output terminal I / O [7: 0] by asserting the output enable signal / OE.

An access command of the flash memory chip CHP1 is illustrated in FIG. The access command is roughly divided into a read operation system command A, an erase operation system command B, a write operation system command C, and a status register clear system command D. In the figure, basic forms of command names, meanings, and command formats are illustrated.

The first serial read command (Serial Read (1)) is a read command for the data area of the sector. The second serial read command (Serial Read (2)) is a read command for the management area of the sector. ID Read Commands (Read ldentifier Codes) are commands for reading a silicon signature such as a storage capacity of a flash memory chip or a manufacturing number. The first data recovery read command (Data Recovery Read (1)) instructs to externally output the write data held by the memory bank which has become the write fail during the write operation to one memory bank. The second data recovery read command (Data Recovery Read (2)) instructs to externally output the write data held by one memory bank BNK1 which has become a write fail during a write operation to the two memory banks. The third data recovery read command (Data Recovery Read (3)) instructs to externally output the write data held by the other memory bank BNK2 that has become a write fail in the write operation to the two memory banks. do. These data recovery commands are used to output the write data held in the flash memory to the outside when the write fail occurs, so that the host device can write to the other flash memory.

A sector erase command (Sector Erase) instructs the sector-by-sector erase operation.

The first write command Program (1) instructs a write operation of sector erase sequence insertion. The second write command Program (2) instructs a write operation to the data area of the sector. The third write command (Program (3)) instructs recording of the management area of the sector. The fourth write command Program (4) instructs additional recording. The additional recording is a recording operation for a part of the storage area of the management area or the like. The program retry command gives an instruction to retry the write operation to other sectors of the same memory bank when the write failure occurs.

At the head of the various access commands, a command code such as "00H" shown in hexadecimal notation is arranged. Some commands, such as ID read commands (Read Identifier Codes), consist only of command codes. In the access command requiring the address information, the sector address information SA1 and SA2 are disposed after the command code. The sector address information SA1 and SA2 are all 16 bits, and constitute one sector address (X address information) with 16 bits. In the case where a part of one sector is used in the read or write operation, and the read or write is to be performed from the middle of the sector, the Y address information may be added after the sector address information. If the recording data is required as in the recording operation, the recording data is then continued.

The command code "BOH" in the sector erase command indicates the start of the erase operation. The command for instructing sector erase for one memory bank may be added with the command code "BOH" after the erase target sector addresses SA1 and SA2. In order to instruct sector erasure in parallel to the two memory banks, the second sector address information SA1 * 1 and SA2 * 1 are placed next to the first sector address information SA1 and SA2, and finally, The command code "BOH" may be added. The memory bank designated by the second sector address information SA1 * 1 and SA2 * 1 needs to be different from the memory bank designated by the first sector address information SA1, SA2. No distinction code is required between the first sector address information SA1 and SA2 and the second sector address information SA1 * 1 and SA2 * 1. This is because sector erase does not require Y address information or data information.

In the first to fourth write access commands and the program retry command, the command code "40H" is a command code for instructing the start of the write operation. When writing is performed in parallel to two memory banks, the command code "41H" is interposed between the addresses of the memory banks BNK1 and BNK2 and the indication information such as the write data. In the write operation, since the designation of the Y address (preset address to address counter) is arbitrary, a division code is required. This division code "41H" may be positioned as a command code for instructing a parallel recording operation. In the write operation, the memory bank designated by the second sector address information SA1 * 2 and SA2 * 2 needs to be different from the memory bank designated by the first sector address information SA1, SA2. This two bank parallel write command is not an object of the interleaving operation. In the program retry command, the sector addresses SA1 * 3 and SAI2 * 3 need to select a bank whose recording has failed. The state of fulfillment of these constraints is determined by the command decoder 40.

As mentioned above, although the invention made by this inventor was concretely demonstrated based on embodiment, it is needless to say that this invention is not limited to that and can be variously changed in the range which does not deviate from the summary.

For example, the nonvolatile memory chip is not limited to a flash memory cell, but may be an MNOS, a high dielectric memory cell, or the like. The storage information of the memory cell is not limited to two values per one memory cell, but may be multiple values such as four values. In the case of a memory cell capable of multi-value memory, multi-value memory may be performed due to a difference in threshold voltage, or multi-value memory may be performed by locally accumulating electric charges in the memory gate. In addition, the configuration of the memory cell array in the flash memory is not limited to the AND type, and can be appropriately changed such as the NOR type or the NAND type. In addition, the threshold voltage definitions for erasing and writing may be defined contrary to the present specification.

The type of command, the method of specifying the sector address, the method of inputting the recording data, and the like may be different from the above. For example, data, address. The input terminal of the command does not have to be dedicated. The number of memory banks is not limited to two, but may be greater.

The format of the memory card is not limited to the multimedia card, and needless to say, applicable to memory cards conforming to other standards. For example, a memory card has a plurality of terminals for inputting and outputting data, and the input and output of data are performed in parallel. The memory system is not limited to the memory card, but may be configured by mounting a flash memory chip and a control chip as part of a data processing system configured by mounting a microprocessor, a memory, and the like on a circuit board.

The effect obtained by the typical thing of the invention disclosed in this application is briefly described as follows.

That is, since the simultaneous write operation or the interleaved write operation to the plurality of memory banks of the plurality of nonvolatile memory chips can be selected, the write operation time can be completely parallelized in the parallel write operation, and the interleaved recording can be completely parallelized. In the operation, the write operation following the write setup can be partially superimposed on the write operation of another memory bank, and as a result, the number of nonvolatile memory chips can be made relatively small to form a memory system with fast write processing. In short, it is possible to provide a memory system or a memory card capable of speeding up the recording speed by not mounting a lot of flash memory chips so as to increase the size of the memory card or increase the cost.

INDUSTRIAL APPLICABILITY The present invention can be widely applied to a processor board having a memory card, a flash memory, and a microprocessor, such as a multimedia card.

Claims (32)

A memory system comprising a plurality of nonvolatile memory chips each having a plurality of memory banks that are independently memory-operable, and a memory controller capable of individually controlling access to the nonvolatile memory chip. The memory controller performs a write instruction indicating an address to the nonvolatile memory chip, and then selectively indicates a simultaneous write operation or an interleaved write operation when a write instruction is issued by indicating a different address to the nonvolatile memory chip. Is possible, After a write instruction instructing the other address for one nonvolatile memory chip of the plurality of nonvolatile memory chips, another address is indicated for another nonvolatile memory chip in the plurality of nonvolatile memory chips for a write instruction. A memory system which can be carried out. The method of claim 1, The simultaneous write operation is a write operation that starts at the same timing for the plurality of memory banks after a plurality of serial instructions of a write operation for designating a memory bank, Wherein said interleaved write operation is a write operation that starts a new write operation in response to a write instruction specifying a different memory bank during the already started write operation. The method of claim 2, And the memory controller distinguishes between the instruction of the simultaneous write operation and the instruction of the interleaved write operation by a kind of command code for instructing a write operation accompanied with write address information and write data information. The method of claim 1, Each nonvolatile memory chip has a chip select terminal and a plurality of other access terminals, The memory controller has a chip select signal output terminal individually connected to the chip select terminal of each nonvolatile memory chip, and a plurality of access information terminals commonly connected to the access terminal of each nonvolatile memory chip. Memory system. A memory system comprising: a plurality of nonvolatile memory chips each having a plurality of memory banks independently operable to memory; and a memory controller capable of individually accessing and controlling the plurality of nonvolatile memory chips. The memory controller is capable of selectively instructing interleaved write or simultaneous write with respect to the memory banks in the nonvolatile memory chip sequentially for each of the nonvolatile memory chips. The method of claim 5, wherein And the interleaved write instruction is a write operation instruction for starting a new write operation in response to a write instruction specifying a different memory bank during the already started write operation. A memory system comprising a plurality of nonvolatile memory chips each having a plurality of memory banks that are independently memory-operable, and a memory controller capable of individually controlling access to the nonvolatile memory chip. And the memory controller is capable of instructing simultaneous writes to memory banks in the nonvolatile memory chip sequentially for each of the nonvolatile memory chips. The method of claim 7, wherein And the simultaneous write instruction is a write operation instruction that starts a write operation for a plurality of memory banks at the same timing after a plurality of serial instructions of a write operation for which a memory bank is designated. A memory system comprising: a plurality of flash memory chips each having a plurality of memory banks independently operable to memory; a memory controller individually accessible and controllable to the plurality of flash memory chips; and an SRAM connected to the memory controller. The SRAM may temporarily store write data for a flash memory chip, The memory controller is selectable for instructing interleaved writing for a memory bank in a flash memory chip and instructing simultaneous writing for a memory bank in a flash memory chip sequentially for each of the flash memory chips. . The method of claim 9, The interleaved write instruction is a write operation instruction for starting a new write operation in response to a write instruction specifying another memory bank during a write operation that has already been started, And the simultaneous write instruction is a write operation instruction for starting a write operation for a plurality of memory banks at the same timing after a plurality of serial instructions of a write operation specifying a memory bank. A memory system comprising a plurality of nonvolatile memory chips each having a plurality of memory banks independently operable to memory, and a memory controller configured to access and control the flash memory chip using an access command. The memory controller outputs a first command code, address information of a memory bank subsequent to the first command code, and a second command code following the address information of the memory bank, and the memory in the flash memory chip designated by the address information. A first control or first command code for starting a memory operation for each input of the second command code, the address information of the memory bank in the flash memory chip following the first command code, and the address information of the memory bank with respect to the bank. Outputting the third command code, the address information of the memory bank in the flash memory chip following the third command code, and the second command code following the address information of the memory bank, and between the first command code and the second command code. Specified by the plurality of address information partitioned by the third command in Memory for a plurality of memory banks, wherein one of the second controls for simultaneously starting the memory operation in response to the input of the second command code is selected, and the memory can be operated in series with the plurality of flash memory chips. system. The method of claim 11, The first command code is a command code for supplying a type of a recording operation, the second command code is a command code for instructing the start of a recording operation, and the third command code is a command code indicating that address information follows. Memory system. The card substrate has an external connection terminal, an external interface circuit connected to the external connection terminal, a memory controller connected to the external interface circuit, and a plurality of flash memory chips individually controlled to be accessed by the memory controller. As a memory card, The flash memory chip has a plurality of memory banks, each of which can be memory operated independently, When the memory controller issues a write instruction indicating an address to a flash memory chip and then performs a write instruction by pointing a different address to the flash memory chip, the memory controller selectively instructs simultaneous write operation or interleaved write operation. Is possible, After a write instruction instructing the different address with respect to one flash memory chip among the plurality of flash memory chips, a write instruction can be performed by instructing another address among the other flash memory chips in the flash memory chips. Memory card, characterized in that. The method of claim 13, The simultaneous write operation is a write operation that starts at the same timing for a plurality of memory banks after a plurality of serial instructions of a write operation specifying a memory bank, And the interleaved recording operation is a recording operation for starting a new recording operation in response to a recording instruction specifying another memory bank during the already started recording operation. The method of claim 14, And the memory controller distinguishes between the instruction of the simultaneous write operation and the instruction of the interleaved write operation by a type of command code for instructing a write operation accompanying the write address information and the write data information. The method of claim 15, And an SRAM connected to said memory controller, said SRAM being capable of temporarily storing write data for a flash memory chip. The method of claim 13, The external connection terminal includes a 1-bit data input / output terminal, a 1-bit command terminal, a power supply voltage terminal, a ground voltage terminal of a circuit, and a clock terminal. Having a memory controller and a plurality of nonvolatile memories, the memory controller issues a write instruction command containing address information indicating an address at which information is to be written to the plurality of nonvolatile memories, The nonvolatile memory has a plurality of storage areas separated by addresses, and each storage area is capable of a memory access operation in parallel with other storage areas. The memory controller performs serially recording on a plurality of nonvolatile memories in parallel, which simultaneously starts a recording operation at the same timing with respect to the designated plurality of storage areas after serially generating a write instruction command that designates another storage area. Nonvolatile semiconductor memory, characterized in that possible. The method of claim 18, The nonvolatile memory has a plurality of memory elements, The write operation of the nonvolatile memory may include selecting a group of memory elements according to an address indicated by the write instruction command and changing the threshold voltage according to address information to be written to each selected memory element. Nonvolatile Semiconductor Memory. The method of claim 18, The writing operation of the nonvolatile memory may include a first operation for changing a threshold voltage of a memory cell, and checking whether the threshold voltage of each memory cell has changed to a threshold voltage corresponding to the address information to be written. A second operation for And after the second operation, when the threshold voltage of at least one memory cell does not change to a threshold voltage corresponding to address information to be written, the first operation is performed. The method of claim 20, And the plurality of memory elements are threshold voltages included in threshold voltage distributions corresponding to address information to be written among three or more threshold voltage distributions. A first terminal used for inputting / outputting data, a second terminal used for inputting an operation instruction command, and a third terminal used for inputting a clock indicating timing of inputting / outputting of data and input of an operation instruction command, A control unit for controlling the operation according to the operation instruction command input from the second terminal, and a plurality of nonvolatile memories for storing or reading data under the control of the control unit, The nonvolatile memory has a plurality of memory elements corresponding to an address, and the plurality of memory elements are classified into a plurality of groups, and data storage operation is performed for another group of the nonvolatile memory during one group of data storage operations. And storing data for one group and storing data for a group of memory elements in another nonvolatile memory at the same time. The method of claim 22, The control unit divides data input from the first terminal for each predetermined byte, instructs storage of first data in the first group of a first nonvolatile memory, and stores second data in the first nonvolatile memory. And a storage instruction to a second group of devices. The method of claim 23, The control unit issues a storage instruction command for instructing a storage operation to the nonvolatile memory, The storage instruction command includes a first command indicating that the command is a storage instruction command, address information indicating a memory element to store data, data to be stored, and a second command instructing to start a storage operation. Non-volatile memory, characterized in that configured. The method of claim 24, The control unit issuing the first command, a first address indicating the memory device of the first group of the first nonvolatile memory, the first data and the second command, And a second address indicating the first command, the second address indicating the memory element of the second group of the first nonvolatile memory, the second data, and the second command. . The method of claim 24, The controller issuing the first command, a first address indicating the memory element of the first group of the first nonvolatile memory, and the first data, And a second address indicating the first command, the second address indicating the memory element of the second group of the first nonvolatile memory, the second data, and the second command. . The method of claim 22, The control unit divides data input from the first terminal for each predetermined byte, instructs storage of first data in the first group of a first nonvolatile memory, and stores second data of the second nonvolatile memory. And a storage instruction to the first group. delete delete The method of claim 27, The control unit issues a storage instruction command for instructing a storage operation to the nonvolatile memory, The storage instruction command includes a first command indicating that the command is a storage instruction command, address information indicating a memory element to store data, data to be stored, and a second command instructing to start a storage operation. Non-volatile memory, characterized in that configured. The method of claim 30, The control unit issuing the first command, a first address indicating the memory device of the first group of the first nonvolatile memory, the first data and the second command, And a second address indicating the first command, the second address indicating the memory element of the first group of the second nonvolatile memory, the second data, and the second command. . The method of claim 30, The controller, after generating the first command, a first address indicating the memory element of the first group of the first nonvolatile memory, and the first data, The first nonvolatile memory and the second nonvolatile memory after generating the first command, a second address indicating a memory element of the first group of the second nonvolatile memory, and the second data; A nonvolatile memory device characterized by generating the second command in both of the volatile memory.

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