KR100856769B1 - Multi-stage amplifier and method for correctiing dc offsets - Google Patents

Abstract

The method of correcting the DC offset in a multistage amplifier includes determining a DC offset imparted to the input signal by the multistage amplifier. The method includes applying a correction voltage to a plurality of selected stages in a multistage amplifier. The total correction voltage applied virtually negates the DC offset imparted by the multistage amplifier.

Description

MULTI-STAGE AMPLIFIER AND METHOD FOR CORRECTIING DC OFFSETS}

1 illustrates an equalizer capable of compensating for attenuation of a signal received by the equalizer via a communication medium.

2 illustrates one embodiment of a circuit used to apply a first order arithmetic operation to a signal.

3 illustrates one embodiment of a circuit for introducing a delay into a signal.

4 illustrates one embodiment of a variable gain limiting amplifier used to maintain a signal within the dynamic range of an equalizer.

5 illustrates one embodiment of a multi-stage variable gain amplifier with DC offset correction.

6 illustrates one embodiment of a method for setting gains along a signal path of the circuit shown in FIG.

7 illustrates an embodiment of a method for adaptively adjusting gain along a signal path of the circuit shown in FIG.

8 illustrates one embodiment of a method for adaptively controlling a correction voltage with respect to a DC offset of a multistage variable gain amplifier.

9 illustrates one embodiment of a method for adjusting the correction voltage of a multistage variable gain amplifier.

<Explanation of symbols for main parts of the drawings>

100: equalizer

102: adaptive controller

104: output monitor

106: offset controller

108: offset monitor

110: variable gain limiting amplifier

112: arithmetic operators

114: delay generator

116 variable gain amplifier

118: Mixer

120: drive amplifier

210, 308, 410: common mode voltage detector

FIELD OF THE INVENTION The present invention generally relates to signal communication, and more particularly, to a multistage amplifier with DC offset compensation.

When a signal is communicated through a communication medium, the signals may be attenuated by various phenomena such as skin effect and dielectric absorption. The signal receiver may include an equalizer that compensates for this attenuation to improve the accuracy and efficiency of signal communications. The amount of compensation applied by the equalizer is preferably matched as closely as possible to the level of attenuation due to the medium in order to maintain consistent output signal characteristics regardless of the particular communication path used for signal communication.

In one embodiment of the invention, a method for correcting a DC offset in a multistage amplifier includes determining a DC offset imparted to the input signal by the multistage amplifier. The method also includes applying a correction voltage to the selected plurality of stages in the multistage amplifier. The total correction voltage applied substantially nullifies the DC offset imparted by the multistage amplifier.

One technical advantage of a particular embodiment is to equalize the output signals. Certain embodiments compensate for signal attenuation resulting from a communication medium used for signal communication. This allows the output characteristics of the signal to be maintained consistent regardless of the communication path used for signal communication. Advantages associated with consistent output characteristics include improved component response since the signal level can be selected to be within the dynamic range of system components. In addition, the signal can be maintained at a level sufficient to prevent information from being lost.

Other technical advantages of certain embodiments include adaptability to different communication media. Certain embodiments use a variable gain amplifier to adjust the degree of compensation applied to the incoming signal. Such embodiments can adjust the magnitude of the compensation for different media, thus increasing the variety of equalizers embodying such techniques. In addition, such embodiments can adapt to changes in media properties associated with process, voltage, and temperature changes.

Another technical advantage of certain embodiments is to facilitate high speed response. Certain embodiments use a multistage variable gain amplifier for signal amplification with DC offset correction in each stage. Since each amplifier provides only a fraction of the total amount of amplification, the overall response time of the multistage amplifier is reduced. Applying DC offset correction at each stage can increase the flexibility of the multistage amplifier by preventing the signal from moving out of the dynamic range of any special stage of the amplifier.

Another technical advantage of certain embodiments is the scalability of the multistage amplifier. By correcting the DC offset at each stage of the multistage amplifier, additional stages can be added without recalculating the overall DC offset of the multistage amplifier. In addition, the risk of the signal leaving the dynamic range of one of the plurality of amplifier stages is substantially reduced when using a large DC offset to correct the DC offset of the entire multistage amplifier. These and other embodiments can be used for applications such as high speed communication.

Other technical advantages will be apparent to those skilled in the art from the accompanying drawings, the description and the claims. In addition, although specific advantages are listed above, specific embodiments may include all, some, or none of the advantages listed above.

1 illustrates in block diagram an equalizer 100 capable of compensating for attenuation of a signal received by the equalizer 100 via a communication medium. In the illustrated embodiment, equalizer 100 measures the magnitude of the gain applied to each of the three signal paths 101A, 101B, 101C based on the output characteristics of the output signal measured by output monitor 104. It includes an adaptive controller 102 to adjust. Equalizer 100 also offsets the DC offset imparted by the components of equalizer 100 in response to offset monitor 108 having detected an inappropriate DC offset in the output signal of equalizer 100. Controller 106. Other components of equalizer 100 include variable gain limiting amplifier (VGLA) 110, arithmetic operator (S) 112, delay generator 114, variable gain amplifier (VGA) 116, mixer 118. And drive amplifier 120. In general, equalizer 100 is capable of the distortion of input signals due to attenuation within a communication medium and the DC offset of signals potentially caused by manufacturing techniques, such as device geometry mismatches and threshold voltage mismatches. In spite of the variation, the DC offset provides an equalized output signal.

에 비례하는데, 여기에서 a_s는 물질에 대한 표피 효과의 계수이고, x는 물질을 따라 이동한 길이이며, f는 신호의 주파수이다. 유전 흡수에 의한 손실의 크기는 다음의 식 a_d·x·f에 비례하는데, 여기에서 a_d는 물질의 유전 흡수의 계수이다. 효과의 상대적 중요성은 물질 및 신호의 주파수에 따라 크게 변할 수 있다. 따라서, 예를 들면, 케이블은 표피 효과의 계수보다 훨씬 더 작은 유전 흡수의 계수를 가질 수 있고, 따라서 표피 효과에 의한 손실은 고주파수에서는 제외하고 현저하게 된다. 반면에, 백플레인 트레이스(backplane trace)는 더 높은 유전 흡수 계수를 가질 수 있고, 따라서 유전 흡수에 의한 손실은 표피 효과에 의한 손실의 크기와 비슷하거나 더 크다. 또한, 공정, 전압 또는 온도(PVT) 변화와 같은 동작 조건의 변화와 관련된 물질의 특성들은 입력 신호에 대한 등화기(100)의 응답에 영향을 줄 수 있다. In general, signal attenuation in conductive communication media occurs for two important reasons. The first important reason is the skin effect that occurs when signals are conducted along the communication medium. The second important reason is the dielectric absorption of the signal by the communication medium. In general, the magnitude (in decibels) of signal loss due to the skin effect is given by

Where a _s is the coefficient of epidermal effect on the material, x is the length traveled along the material, and f is the frequency of the signal. The magnitude of the loss due to dielectric absorption is proportional to the equation a _d x x f where a _d is the coefficient of dielectric absorption of the material. The relative importance of the effects can vary greatly depending on the frequency of the material and the signal. Thus, for example, a cable may have a coefficient of dielectric absorption that is much smaller than the coefficient of skin effect, so that the loss due to the skin effect becomes significant except at high frequencies. On the other hand, the backplane trace can have a higher dielectric absorption coefficient, so the loss due to dielectric absorption is similar to or greater than the magnitude of the loss due to the skin effect. In addition, the properties of the material associated with changes in operating conditions, such as changes in process, voltage or temperature (PVT), can affect the response of the equalizer 100 to the input signal.

To compensate for these losses, equalizer 100 distributes the signal across three signal paths 101A, 101B, and 101C, and selectively uses portions of the signal on each path using variable gain amplifier 116. Amplify. First path 101A represents an unmodified, i.e., unmodified input signal. The second path 101B applies a first order arithmetic operation based on the frequency of the signal, such as a derivative operation, to the signal. This operation is shown as arithmetic operator (S) 112. Third path 101C applies a second arithmetic operation based on the frequency of the signal, such as the second derivative, to the signal. This operation is illustrated by the application of two arithmetic operators (S) 112. By selectively amplifying the primary and secondary components of the signal, equalizer 100 compensates for loss effects that are proportional to frequency and square root of frequency, respectively. It is appropriate to discuss the components of the equalizer 100 in detail using a general background of the operation of the equalizer 100.

Adaptive controller 102 represents any component or components for analyzing information about the output signal of equalizer 100 and adjusting each gain of each variable gain amplifier 116. Adaptive controller 102 may include analog and / or digital electronic components such as transistors, resistors, amplifiers, constant current sources, or other similar components. Adaptive controller 102 may also include suitable components for converting signals from analog signals to digital signals and vice versa. According to a particular embodiment, adaptive controller 102 includes a digital processor, such as a microprocessor, microcontroller, embedded logic circuit, or other information processing component. Further, according to a particular embodiment, the adaptive controller 102 controls the gain of each variable gain amplifier 116 by adjusting the bias current applied to each variable gain amplifier 116. One advantage of using a bias current to control the variable gain amplifier 116 is to adjust the magnitude of the gain applied by the amplifier without changing the amplifier's bandwidth, so that the amplifier can be used even if the gain increases. Its dynamic range can be maintained.

The output monitor 104 represents any component for detecting the output characteristic of the output signal of the equalizer 100. Output monitor 104 may be any sensor, integrator, amplifier, comparator, or any other suitable for performing signal detection and analysis using any suitable operation, such as signal averaging, filtering, or maximum or minimum level latching. Suitable components may be included. According to a particular embodiment, the output monitor 104 detects the intersymbol interference level for the output signal, the output signals representing the magnitude of signal distortion caused by the skin effect and / or dielectric absorption. In addition, according to certain embodiments, output monitor 104 communicates the output characteristic as an analog signal to adaptive controller 102.

The offset controller 106 represents any component or components for adjusting the magnitude of the DC offset correction applied in one or more stages of the variable gain amplifier 116. The offset controller 106 may analyze any microprocessor, microcontroller, embedded logic circuitry, or other information for adjusting the magnitude of the correction voltage applied to the signal to correct the DC offset and analyze the information received from the offset monitor 108. Suitable components may be included. The DC offset may be imparted to the signal by various components of equalizer 100, in particular by variable gain amplifier 116. In a multistage variable gain amplifier, the DC offset can be cumulative between each stage. The offset controller 106 applies a DC voltage to the signal amplified by the variable gain amplifier 116 to correct the offset. According to a particular embodiment, the offset controller 106 applies a correction voltage stepwise, each step being applied to the variable gain amplifier 116 of the other stage. In such an embodiment, the magnitude of the voltage applied in each step can be determined in any suitable manner. For example, the total correction voltage may be evenly distributed between the steps, or may be distributed in magnitude proportional to the gain of each stage.

The offset monitor 108 represents any suitable component or components for measuring the magnitude of the DC offset in the signal. Offset monitor 108 may include a low pass filter, integrator, amplifier, comparator, or other suitable components for detecting a DC offset. In the illustrated embodiment, offset monitor 108 is coupled to the output of equalizer 100 and the output of each variable gain amplifier 116. Thus, the offset monitor 108 can measure the DC offset imparted by each variable gain amplifier 116 as well as the overall DC offset imparted by the equalizer 100. This allows the offset controller 106 to make appropriate DC offset adjustments for the particular path 101A, 101B, or 101C and the overall output of the equalizer 100.

Variable gain limiting amplifier (VGLA) 110 represents a component or combination of components for adjusting the input signals received by equalizer 100. The adjustment process adjusts the overall level of the input signal so that the signal remains within the dynamic range of the equalizer 100. Thus, VGLA 110 may provide some level of equalization by adjusting the overall signal at that level. In a particular embodiment, the amount of amplification applied by VGLA 110 is controlled by the bias current applied to VGLA 110.

Arithmetic operator (S) 112 represents any component or combination of components that produces an output that is linearly proportional to the frequency of the incoming signal (this is called a "first order operation"). Arithmetic operator (S) 112 may include any suitable electronic component or circuitry for performing certain arithmetic operations. According to a particular embodiment, this operation is a differential operation and multiplies the incoming sinusoidal signal by a multiple of the frequency of the signal. Arithmetic operator (S) 112 is applied multiple times for one signal to generate an output signal that is proportional to the square of the frequency, cube, or other exponential square based on the number of times arithmetic operator (S) 112 is applied. can do.

Delay generator 114 represents any component or combination of components that introduces a time delay in the communication of a signal. Delay generator 114 may include any suitable electronic component or circuit. According to a particular embodiment, the delay introduced into the signal by the delay generator 114 is approximately equal to the amount of time needed for the arithmetic operator (S) 112 to be applied to the signal. Thus, the delay generator 114 can be used to equalize the amount of time required for each portion of the input signal to travel down the corresponding path 101A, 101B or 101C. In this way, the signals of each part can be synchronized as these signals reach mixer 118.

Variable gain amplifier 116 represents any component or components for amplifying a signal. The variable gain amplifier 116 may comprise any suitable electronic component, and in a particular embodiment each variable gain amplifier 116 is controlled by a bias current applied to the special variable gain amplifier 116. In some cases, the response time of the special component performing the amplification is so high that the amplifier cannot effectively amplify a rapidly changing high frequency signal between high and low values. Thus, the variable gain amplifier 116 includes a series of stages, where each stage can perform part of the overall amplification. Since no stage is burdened with performing all amplification, the time required for each stage to apply its respective gain is also reduced. This allows the multistage variable gain amplifier 116 to respond to high frequency signals.

The variable gain amplifier 116 may also provide a DC offset to the signal. In a multistage amplifier, each stage may impart a DC offset. One way to correct the DC offset is to apply a correction voltage to correct the DC offset of the signal. The correction voltage may be applied to the initial signal as a whole before the initial signal is amplified. However, applying the voltage globally at one point may cause the signal to be out of the dynamic range of one or more stages of the amplifier 116. In addition, the applied voltage is recalculated and adjusted each time a new stage is added, and if the gain is variable at each stage, the DC offset may be unevenly distributed at each stage. To address this difficulty, particular embodiments may include applying a correction voltage at multiple stages of the amplifier 116. This allows the DC offset of each stage to be corrected at that stage, thereby reducing the chance that the signal will leave the amplifier's dynamic range and eliminating the need to recalculate the DC offset of the entire array each time a stage is added. Furthermore, applying a correction voltage for each stage facilitates the correction of the DC offset when the gain of each stage changes independently, allowing different stages to have different gains and give different DC offsets.

Mixer 118 represents a component or combination of components for recombining signals on communication paths 101A, 101B, 101C into a single signal. Mixer 118 may include any suitable electronic components. Mixer 118 provides the signal coupled to drive amplifier 120. Drive amplifier 120 represents any component or combination of components for amplifying the combined signal. The drive amplifier 120 performs any suitable amplification on the combined signal to produce an output signal for the equalizer 100, which is high enough to effectively deliver the output signal to another destination. Have a level.

In operation, equalizer 100 receives an input signal attenuated by communication over a communication medium. VGLA 110 adjusts the signal so that the signal level is within the dynamic range of equalizer 100. Equalizer 100 distributes the input signal to three paths 101A, 101B, 101C. The signal of path 101A is delayed twice by delay generator 114. The signal of path 101B passes once through arithmetic operator S 112 and is delayed once by delay generator 114. The signal in path 101C passes through arithmetic operator S 112 twice. Thus, the three paths 101A, 101B, and 101C correspond to input signals on which no arithmetic, first order and second order operations are performed, respectively.

The equalizer 100 then amplifies the signal on each path using each variable gain amplifier 116. The gain of each amplifier 116 is controlled by the adaptive controller 102 and the gain may vary for each path 101A, 101B, 101C. This allows equalizer 100 to provide different degrees of compensation for loss effects having different proportionalities depending on the frequency of the signal. In general, the magnitude of the compensation of a particular effect with respect to the base signal is proportional to the ratio of the amplification of the corresponding path to the amplification of the unmodified signal on path 101A. Thus, path 101A may apply a gainless or slight negative gain (dB) to increase the relative effect of compensation applied to other paths. The offset controller 106 corrects any DC offset provided by the corresponding amplifier 116 for each signal on each path 101A, 101B, 101C.

The amplified signal from each path is combined into a single signal by mixer 118. The drive amplifier 120 amplifies the output signal to enable effective communication of the output signal to other destinations. Output monitor 104 and offset monitor 108 monitor the characteristics of the output signal and provide feedback to adaptive controller 102 and offset controller 106. Adaptive controller 102 uses feedback from output monitor 104 on the level of the output signal to determine whether adaptive controller 102 overcompensates or undercompensates the input signal. Adaptive controller 102 may appropriately adjust the amount of gain applied to one or more paths 101A, 101B, 101C to more effectively compensate based on the determination. The offset controller 106 uses the information about the DC offset of the output signal provided by the offset monitor 108 to adjust the magnitude of the correction voltage applied to each amplifier 116.

One advantage of the aforementioned adaptive control and feedback is that the equalizer 100 can respond to effects that change the response of the equalizer 100 to signals such as process, voltage and temperature (PVT) variations. The adaptive response allows the equalizer 100 to produce consistent output characteristics of the output signal even when there is a change in attenuation. Embodiments that do not include automatic adaptive control may also be manually adjusted in response to the detected change in the changed condition or response.

An advantage of the particular embodiment of the equalizer 100 is that it is adaptable to other communication media. For example, equalizer 100 has a gain setting function coupled to the cable and suitably set to compensate for attenuation due to skin effect and dielectric absorption. If equalizer 100 is coupled to a backplane trace instead of a cable, the gains of paths 101A, 101B, and 101C may be controlled by controller 102 to allow adaptive equalizer 100 to compensate for the different attenuation characteristics of the backplane trace. Can be adjusted using This allows the equalization circuitry to be configured to provide the inverse operation of the transfer function of a particular communication medium, thus providing many advantages over previous compensation methods in which the circuits could not be effectively applied for communication media with different transmission characteristics.

Although specific embodiments of the equalizer 100 have been described in detail, there are many other possible embodiments. Possible variants include, for example, applying other or additional arithmetic operations to paths 101A, 101B, and 101C to compensate for different loss characteristics, increasing the number of paths, and controllers 102 and 106. Using manual control instead of automatic feedback control, using a single stage variable gain amplifier 116, and other variations suggested by the above description. In general, components may be rearranged, modified, or omitted in any suitable manner, and the functions performed by the components may be distributed to other or additional components, or in any suitable method for one component. It can be integrated into. Thus, implementation of equalizer 100 should be understood to include any such variations.

2 shows a particular embodiment of an arithmetic operator (S) 112. In the illustrated embodiment, arithmetic operator (S) 112 applies a derivative operation to an input signal provided as a derivative input A (along with complement A _x ) to arithmetic operator (S) 112. Arithmetic operator (S) 112 includes a resistor 202, a transistor 204, a capacitor 206, and a constant current source 208. Transistor 204 can be any suitable transistor, including, for example, a metal oxide semiconductor field effect transistor (MOSFET) shown in FIG. 2. The component values of the resistor 202, the capacitor 206, and the constant current source 208 may be selected to produce a certain proportional factor between the frequency of the input signal and the level of the output signal.

Arithmetic operator (S) 112 also includes a common mode voltage detector (CMVD) 210 that monitors the common mode voltage of the differential output signal Z (with complement Z _x ). The CMVD 210 is coupled to an amplifier 212, which compares the output of the CMVD 210 with a reference common voltage V _comm 214. The CMVD 210 and the amplifier 212 together maintain the common mode voltage of the differential output signal Z at V _comm 214. This prevents voltage drift of the output signal that occurs in other cases.

In operation, arithmetic operator (S) 112 receives an input signal (A). The response of the arithmetic operator S 112 to the input signal A is frequency dependent because of the frequency dependent responsiveness of the capacitor 206. The resistor 202 and the constant current source 208 regulate the rate at which the capacitor 206 is charged and discharged by the input signal A. Thus, arithmetic operator S 112 provides an output signal Z that is proportional to the frequency of the input signal A. The CMVD 210 monitors the common mode voltage of the output signal Z, and the amplifier 212 corrects the common mode voltage as needed.

The arithmetic operator (S) 112 is only one special example of one special first order arithmetic operation. Other operations may be used in the equalizer 100 and other suitable components may be used to generate the differential operation. Furthermore, other arithmetic operations can produce higher order responses, such as output signals that are proportional to the square of the frequency. Such modifications are to be understood as being included within the scope of the present invention.

3 illustrates one embodiment of a delay generator 114. Delay generator 114 generates a differential output signal Z that is phase delayed behind the differential input signal A. In this embodiment, the delay generator 114 includes a transistor 302, a capacitor 304, a constant current source 306, a CMVD 308, and an amplifier 310. Transistor 302 may be any suitable transistor, such as, for example, a metal oxide semiconductor field effect transistor (MOSFET) shown in FIG. 3. Component values of capacitor 304 and constant current source 306 may be selected to impart a suitable phase delay between input signal A and output signal Z. According to a particular embodiment, the component values of delay generator 114 are selected to match the phase delay of delay generator 114 with the time required for arithmetic operator S 112 to apply its respective arithmetic operation.

In operation, the delay generator 114 generates an output signal Z that is delayed behind the input signal A because of the charging time of the capacitor 304 and the response time of the transistor 302. The CMVD 308 and the amplifier 312 operate together to maintain the common mode voltage of the output signal Z at V _comm 312. This helps to prevent voltage drift of the output signal that occurs in other cases.

The illustrated embodiment of the delay generator 114 is just one example of many possible components that provide a delay for the input signal. In other embodiments, the magnitude of the delay can be adjusted using, for example, variable capacitor 304 or variable constant current source 306. Other components may be used to generate a certain delay, and the various components shown may be rearranged or omitted. Such modifications are to be understood as being included within the scope of the present invention.

4 illustrates one embodiment of a VGLA 110. In the illustrated embodiment, VGLA 110 includes resistor 402, transistor 404, constant current source 406, variable constant current source 408, CMVD 410, and amplifier 412. Transistor 404 can be any suitable transistor, such as, for example, a metal oxide semiconductor field effect transistor (MOSFET) shown in FIG. 4. The component values of resistor 402 and constant current source 406 may be appropriately selected to produce the desired amplification range for VGLA 110. The variable constant current source 408 is adjustable such that the gain of the VGLA 110 is controlled by controlling the amount of current biasing the transistor 404 (as indicated by “k”).

In operation, VGLA 110 provides a gain of an input signal applied to input transistor 404 (denoted as "M1" and "M2"). The magnitude of the gain is controlled by the component values of the variable current source 408 and other components of the VGLA 110. VGLA 110 also limits the maximum level of the signal to prevent the signal from moving beyond the dynamic range of equalizer 100. The CMVD 410 monitors the common mode voltage of the output signal Z and maintains the common mode voltage of the output signal Z at V _comm 414 together with the amplifier 412.

The illustrated embodiment is just one example of many possible embodiments of VGLA 110. Other components may be used to generate some variable gain, limit the maximum level of the output signal, and otherwise adjust the input signal to the equalizer 100. Furthermore, various components shown may be rearranged or omitted. Such modifications are to be understood as being included in the scope of the present invention.

5 illustrates an example of a multistage embodiment of a variable gain amplifier 116. In the illustrated embodiment, the amplifier 116 includes amplifier stages 502A, 502B, ... 502n (collectively referred to as "stage 502"). Each amplifier provides a variable gain g on the signal applied to its corresponding input terminals 504A, 504B, ... 504n (collectively referred to as "input terminal 504"). The gain generated by each stage 502 may be independently variable and, alternatively, may be automatically equalized between all stages. According to a particular embodiment, the gain can be controlled by adjusting the bias currents 506A, 506B, ... 506n (collectively referred to as "bias current 506") applied to the corresponding stage 502. Controlling the stages 502 using the bias current 506 can increase the gain of the stages 502 without significantly reducing the bandwidth of the stages 502.

Each stage 502 may impart a DC offset to the signals applied to each input terminal 504 of the stages. The magnitude of the DC offset thus given may vary depending on the gain of the particular stage 502, and generally other stages 502 may impart a different DC offset 502. The previous methods corrected the DC offset by applying a correction voltage in front of the first stage 502A to be the DC offset provided by the overall multistage amplifier 116. However, this may cause the signal to deviate outside of the dynamic range of one or more stages 502, especially if the magnitude of the given DC offset varies from stage to stage 502. Furthermore, this is more dangerous than the uncorrected DC offset being amplified at each subsequent stage 502 and potentially disturbs the signal.

Thus, in the embodiment shown, (hereinafter voltages _{V sA (508A), V sB} (508B), ... V sn (508n) the whole so) correction voltage (V _s) (508) are each stage 502 Is applied to the input terminal 504 of. This reduces the risk that the uncorrected DC offset at initiation is amplified to the point of severely impaired signal quality, and also reduces the risk that the signal leaves the dynamic range of one of the stages 502. The magnitude of the correction voltage 508 applied to each stage 502 can be adjusted for the special stage 502, thus further reducing the risk of the signal leaving the dynamic range of any stage 502. A new correction voltage 508 can be added for each new stage 502. This prevents the risk of the signal leaving the dynamic range of each stage 502 caused by the addition of each new stage 502, such as when a single DC offset is applied to the first stage 502A.

The magnitude of the correction voltage 508 applied to each stage 502 can be varied in various ways. Correction voltage 508 may be evenly distributed between stages 502 such that the overall correction is equal to the overall DC offset imparted by amplifier 116. Alternatively, the correction voltage 508 can be selectively adjusted at each stage. For example, the magnitude of the correction voltage 508 can be adjusted each time the gain of the stage changes. In such embodiments, it is useful for the offset controller 106 and the adaptive controller 102 to be in communication with each other for quick adjustment. The correction voltage 508 can be adjusted automatically in response to the information received from the offset monitor 108. Alternatively, the correction voltage 508 can be adjusted manually. It is to be understood that these and many other variations, including the addition, omission, or rearrangement of various components, are included within the scope of the present invention. In particular, it should be understood that the techniques described herein may be applied to any multistage variable gain amplifier without being limited to amplifiers used in equalizer 100 or similar devices.

6 is a flowchart 600 illustrating an exemplary method for setting gain levels of paths 101A, 101B, 101C using adaptive controller 102. In step 602, transmission characteristics of the communication medium are measured. This measurement can be used to determine the physical properties of the communication medium, such as skin effect factor, dielectric absorption factor, length, or other properties related to the attenuation of the signal. The effect of the primary frequency dependency of the medium is determined at step 604. This may include any type of attenuation that is linearly proportional to the frequency of the signal carried in the medium. Based on the first order effect, the adaptive controller 102 is set at step 606 to generate a gain on the path 101B which roughly compensates for the first order effect. The effect of the secondary frequency dependency is determined from the measurements performed on the medium at step 608, and the adaptive controller 102 is set to generate a compensation gain on path 101C at step 610.

In order to prove that the relative compensation on the primary path 101B and the secondary path 101C is sufficient with respect to the uncorrected path 101A, the amplification factor between the paths is calculated in step 612. Based on this ratio, it can be determined whether the amount of compensation applied to the paths 101B and 101C is sufficient with respect to the uncorrected signal. If the amount of compensation is not sufficient, a negative dB gain may be applied to the uncorrected path 101A to improve the gain / gain ratio of the paths in step 614. For example, in special cases full compensation for the damping effect may require a gain of 1 on path 101A, a gain of 10 on path 101B, and a gain of 50 on path 101C. If the amplifier 116 on the path 101C has a maximum gain of 40, then a gain of 0.8 is applied to the path 101A, for example, so that the ratio between the paths equals the gains of the paths 101B and 101C to 8 and 40, respectively. Can be maintained by setting. Once all gains have been set, the method ends.

7 is a flowchart 700 illustrating a method for adaptively adjusting the gains of paths 101A, 101B, and 101C. The equalizer 100 starts processing the input signal to generate an output signal, and the adaptive control method starts. The output monitor 104 monitors the intersymbol interference of the output signal at step 702 to determine whether there is an imbalance in the signal indicating that the gains of one or more paths 101A, 101B, 101C require adjustment. If an imbalance is detected at decision step 704, the adaptive controller 102 determines the gain adjustment of each path at step 706 based on the information provided by the output monitor 104. The adaptive controller 102 then appropriately adjusts the gain of each path 101A, 101B, 101C in step 708. The method may be repeated as long as reception of the signal continues as shown by decision step 710.

The method of operation shown in FIGS. 6 and 7 shows examples of a method for setting the appropriate gain of variable gain amplifier 116 in equalizer 100. In other embodiments, the steps described above may be performed in any suitable order, and special steps may be omitted or added. Other gain setting methods may also be used, particularly including any method of operation consistent with any of the many embodiments of equalizer 100 described above.

8 is a flowchart 800 illustrating one embodiment of a method of adaptively controlling a correction voltage provided to correct for a DC offset in a multi-stage amplifier 116. In the method shown, the correction voltage is determined for each stage 502 along all paths 101A, 101B, 101C in step 802. This determination can be made based on any suitable measurement of the DC offset imparted by the special stage 502. The offset controller 106 applies each correction voltage to each stage at step 804.

When equalizer 100 is activated and receiving a signal, offset monitor 108 monitors the DC offset of the entire output signal as well as the DC offset of each path 101A, 101B, 101C in step 806. If an unexpected offset is detected at decision step 808, the offset controller 106 determines the appropriate adjustment of the correction voltage at step 810. The offset controller 106 then applies the adjustment at step 812. Then, as shown in decision step 814, the method may be repeated from step 806 as long as reception of the signal continues.

9 is a flowchart illustrating a method of adjusting the correction voltage in the multistage amplifier 116. The method starts at step 902, for example, setting the correction voltage of each stage 502 by applying steps 802 and 804 of the method shown in FIG. Once the correction voltage is set, the correction voltage can be adjusted based on the change in the multistage amplifier 116. If the gain of one or more stages 502 is adjusted as shown in decision step 904, the offset controller 106 may determine a new correction voltage for each stage 502 in step 906. The offset controller 106 then applies a new correction voltage at step 908.

Offset controller 106 may also be adjusted in response to adding stage 502 to multistage amplifier 116. If it is determined at step 910 that a stage has been added, then at step 912 the correction voltage of the new stage 502 is determined. The offset controller 106 applies a correction voltage to the new stage 502 in step 914. Since the correction voltage is applied to each stage separately, it is not necessary to adjust the correction voltage associated with any other stage 502. The method is terminated after appropriate adjustments are made to the gain change or additional stages.

8 and 9 are just one example of many possible methods for applying a correction voltage to multiple stages of the multi-stage amplifier 116. Other embodiments, for example, other embodiments including applying a correction voltage for each of the other stages 502 without applying a correction voltage for each stage 502, and manually controlling the offset without feedback. Or other similar forms of disease are possible. In particular, it should be understood that any method of operation consistent with any embodiment of variable gain amplifier 116 described above is within the scope of the present invention.

Although the present invention has been described above in connection with some embodiments, those skilled in the art will be able to make various changes, modifications, adaptations, substitutions and modifications to the embodiments. Accordingly, it is intended that the present invention cover such changes, modifications, alterations, substitutions and modifications as fall within the scope of the appended claims.

According to the present invention, equalization of the output signal is made by compensating for signal attenuation resulting from a communication medium used for signal communication. This allows the output characteristics of the signal to be maintained consistent regardless of the communication path used for signal communication. Advantages associated with consistent output characteristics include improved component response since the signal level can be selected to be within the dynamic range of system components. In addition, the signal can be maintained at a level sufficient to prevent information from being lost.

According to the invention, it is adaptable to different communication media. Certain embodiments use a variable gain amplifier to adjust the degree of compensation applied to the incoming signal. Such embodiments can adjust the magnitude of the compensation for different media, thus increasing the variety of equalizers embodying such techniques. In addition, such embodiments can adapt to changes in media properties associated with process, voltage, and temperature changes.

Another technical advantage of the present invention is to promote high speed response. Certain embodiments use a multistage variable gain amplifier for signal amplification with DC offset correction in each stage. Since each amplifier provides only a fraction of the total amount of amplification, the overall response time of the multistage amplifier is reduced. Applying DC offset correction at each stage can increase the flexibility of the multistage amplifier by preventing the signal from moving out of the dynamic range of any special stage of the amplifier.

Another technical advantage of the present invention is the scalability of the multistage amplifier. By correcting the DC offset at each stage of the multistage amplifier, additional stages can be added without recalculating the overall DC offset of the multistage amplifier. In addition, the risk of the signal leaving the dynamic range of one of the plurality of amplifier stages is substantially reduced when using a large DC offset to correct the DC offset of the entire multistage amplifier.

Claims (22)

In the method of correcting the DC offset in a multi-stage amplifier, Determining a DC offset imparted to an input signal by the multistage amplifier, wherein the multistage amplifier has a plurality of stages coupled between the amplifiers; And Applying a correction voltage to a selected one of the plurality of stages of the multistage amplifier, wherein the sum of the applied correction voltages negates the DC offset imposed by the multistage amplifier. Including; The DC offset correction method is performed in an equalizer operable to compensate for attenuation of the input signal, and a correction voltage applied to a selected stage among a plurality of stages of the multistage amplifier further invalidates the DC offset imparted by the equalizer. To; Gain of each of the plurality of stages of the multistage amplifier is controlled by an adaptive controller of the equalizer, DC offset correction method. The method of claim 1, Determining the DC offset comprises determining a DC offset of each stage of the multi-stage amplifier. The method of claim 2, The correction voltage is applied to each stage of the multistage amplifier; And the correction voltage applied to each stage is equal in magnitude to the DC offset imparted by that stage. The method of claim 1, Wherein the total correction voltage is uniformly distributed among the selected stages to which the correction voltage is applied. The method of claim 1, Monitoring the output DC offset of the output signal of the multi-stage amplifier; Detecting a change in the output DC offset; And And adjusting the correction voltage applied to each stage in response to the change of the output DC offset. The method of claim 1, Adding a new stage to the multistage amplifier; Determining a DC offset imparted by the new stage; And And applying a correction voltage equal in magnitude to the DC offset imparted by the new stage. The method of claim 1, Adjusting the gain of one stage of the multistage amplifier; And In response to the adjustment of the gain, adjusting the correction voltage applied to the stage at which the gain is adjusted. The method of claim 1, The multi-stage amplifier includes a multi-stage arrangement of a plurality of amplifiers, wherein stages of the plurality of amplifiers are connected in series, the multi-stage arrangement of the plurality of amplifiers receives an input signal through a respective communication path, and the respective communication Operable to amplify the input signal received via a path; Each input signal is mixed into a combined output signal; The method, Monitoring a change in the DC offset of the combined output signal; And And adjusting a correction voltage in response to detecting a change in the DC offset of the combined output signal. delete The method of claim 9, Detecting an indication from an adaptive controller indicating that the gain of the multistage amplifier has changed; And And adjusting the correction voltage in response to the change. The method of claim 1, And the input signal has a frequency in excess of 1 GH. In a multistage amplifier, A plurality of stages coupled between the amplifiers, each stage operable to apply respective gains to the input signal; And An offset controller operable to apply a correction voltage to a selected one of the plurality of stages, wherein the sum of the correction voltages applied to the selected stages also invalidates the total DC offset imparted by the multi-stage amplifier. Including The multistage amplifier is part of an equalizer operable to compensate for attenuation of an input signal, and a correction voltage applied to a selected stage among the plurality of stages of the multistage amplifier also negates the DC offset imparted by the equalizer; Gain of each of the plurality of stages of the multistage amplifier is controlled by an adaptive controller of the equalizer,  Multi-stage amplifier. The method of claim 12, And said correction voltage is equal in magnitude to the DC offset imparted by a selected one of said plurality of stages. The method of claim 12, Wherein the total correction voltage is evenly distributed among the selected stages to which the correction voltage is applied. The method of claim 12, The multistage amplifier further comprises an offset monitor operable to monitor the output DC offset of the output signal of the multistage amplifier and detect a change in the output DC offset, The offset controller is further operable to adjust a correction voltage applied to each stage in response to a change in the output DC offset. The method of claim 12, The offset controller is further operable to detect an adjustment of the gain of one stage of the multistage amplifier and to adjust the correction voltage applied to the stage whose gain is adjusted in response to the adjustment of the gain. The method of claim 12, The multi-stage amplifier includes a multi-stage arrangement of a plurality of amplifiers, wherein stages of the plurality of amplifiers are connected in series, the multi-stage arrangement of the plurality of amplifiers receives an input signal through a respective communication path, and the respective communication Operable to amplify the input signal received via a path; Each input signal is mixed into a combined output signal; Wherein the multistage amplifier further comprises an offset monitor operable to monitor a change in the DC offset of the combined output signal and adjust a correction voltage in response to detecting a change in the DC offset of the combined output signal. delete The method of claim 12, And wherein the input signal has a frequency in excess of 1 GHz. In a multistage amplifier, Means for determining a DC offset imparted by a multistage amplifier having a plurality of amplifier stages coupled between the amplifiers; Means for applying a correction voltage to a selected one of a plurality of stages in the multistage amplifier, wherein the sum of the applied correction voltages invalidates the DC offset imposed by the multistage amplifier; And Means for controlling the gain of a multistage amplifier Including; The DC offset determining means, the correction voltage applying means and the multistage amplifier gain control means form a part of the equalizer operable to compensate for the attenuation of the input signal to the equalizer, the selected offset being selected from a plurality of stages of the multistage amplifier. The applied correction voltage is also to invalidate the DC offset imparted by the equalizer,  Multi-stage amplifier. The method of claim 20, Means for monitoring an output DC offset of the output signal of the multistage amplifier; Means for detecting a change in output DC offset; And Means for adjusting the correction voltage applied to each stage in response to a change in the output DC offset. The method of claim 20, Means for adjusting the gain of one stage of the multistage amplifier; And Means for adjusting the correction voltage applied to the stage whose gain is adjusted in response to the adjustment of the gain.

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