KR100850777B1 - Method of converting analog to digital with enhanced resolution by oversampling - Google Patents

Abstract

An analog-to-digital conversion method having improved resolution by oversampling is disclosed. Analog-to-digital conversion method according to the present invention comprises the steps of generating an oversampling clock having a frequency of N (N is a natural number of 2 or more) of the reference clock, and in accordance with the oversampling clock, the analog input every cycle of the reference clock Sampling and quantizing M signals, where M is a natural number of two or more, and converting the signals into M digital values, determining weights for each of the M digital values, and based on M digital values and weights. Determining one digital code.

Description

Analog-to-digital conversion method with improved resolution by oversampling {METHOD OF CONVERTING ANALOG TO DIGITAL WITH ENHANCED RESOLUTION BY OVERSAMPLING}

1 is a diagram schematically showing an analog-to-digital conversion method according to an embodiment of the present invention.

2 is a block diagram showing the structure of an analog-to-digital converter for performing an analog-to-digital conversion according to an embodiment of the present invention.

3 is a waveform diagram illustrating an oscillation signal output from each output terminal of a delay stage of a voltage controlled oscillator.

4 is a waveform diagram comparing a reference oscillation signal with a reference clock and an oversampling clock.

5 is a waveform diagram illustrating a detection process of a phase change amount in a first section.

6 is a waveform diagram illustrating a detection process of a phase change amount in a second section.

7 is a flowchart illustrating an analog-digital conversion method according to an embodiment of the present invention.

The present invention relates to an analog-to-digital conversion method, and more particularly, to an analog-to-digital conversion method for improving resolution using an oversampling technique without using a sample-and-hold circuit.

Sample-and-hold circuits commonly used in analog-to-digital converters typically use op-amps to increase power consumption and occupy a large area. However, if the sample-and-hold circuit is removed, the average value of the input during the sampling period will be transformed into a digital value, which will degrade the resolution since the analog input is not linear.

An object of the present invention for solving the above problems is to provide an analog-to-digital conversion method by oversampling to improve the resolution is reduced by eliminating the sample-and-hold circuit in the analog-to-digital converter.

In order to achieve the above object, the analog-to-digital conversion method according to an embodiment of the present invention comprises the steps of generating an oversampling clock having a frequency of N (N is a natural number of 2 or more) of the reference clock, and the oversampling In synchronization with the clock, sampling and quantizing M analog input signals (M is a natural number of 2 or more) every cycle of the reference clock, converting the M digital values into M digital values, and weighting each of the M digital values. Determining, and determining one digital code based on the M digital values and the weight.

The generating of the oversampling clock may include locking the oversampling clock using a delay locked loop.

The converting into M digital values may include sampling M analog signals in synchronization with M consecutive rising edges of an oversampling clock.

The converting into M digital values may include outputting a plurality of oscillation signals having a phase difference from each other to output terminals of a plurality of delay stages included in a voltage controlled oscillator corresponding to the analog input signal, and outputting the plurality of oscillation signals to the oversampling clock. Synchronously, detecting phase shift amounts of the plurality of oscillation signals every M cycles of the reference clock, and determining M digital values based on each of the M phase detected phase shifts. have.

The detecting of the phase change amount M times may be performed based on the plurality of oscillation signals, from the start point of every cycle of the oversampling clock to the rising edge of the first reference oscillation signal during the first cycle of the oversampling clock. Detecting a first phase change amount M times, and every cycle of the oversampling clock from the rising edge of the reference oscillation signal last appearing during each period of the oversampling clock based on the plurality of oscillation signals; Detecting the second phase change amount up to an end point M times; and a third phase change amount from the rising edge of the reference oscillation signal first appearing during every period of the oversampling clock to the last rising edge M; And detecting once.

The determining of the M weights may be performed by comparing the starting point of each cycle of the reference clock with the time of oversampling, and comparing the weight of the oversampled signal with the weight of the overclocked signal at a time closer to the starting point of each cycle of the reference clock. It may be determined that the weight is greater than the weight for the oversampled signal at a point far from the start of the cycle.

The determining of the one digital code may determine one digital code by a weighted sum of the M digital values and each weight.

Hereinafter, with reference to the accompanying drawings will be described in detail the analog-to-digital conversion method according to an embodiment of the present invention.

1 is a diagram schematically showing an analog-to-digital conversion method according to an embodiment of the present invention.

1 illustrates an oversampling clock OVERCLK having a frequency that is an integer multiple of the reference clock REFCLK and the frequency of the reference clock. In one embodiment of the present invention, the oversampling method using a voltage controlled oscillator is analog to digital conversion during one period of the same sampling, unlike the conventional oversampling used in a delta-sigma analog-to-digital converter (Delta-Sigma ADC). Will be done many times. An embodiment of the present invention shows a process of using an oversampling clock having four times the frequency. In order to sample the analog input signal (ANALOG SIGNAL) at the R1 point of the reference clock (REFCLK), the analog input signal is sampled at the L1, L2, L3, L4, and L5 points of the oversampling clock (OVERCLK) and weighted to the sampled value. The weighted sum of determines the digital value at time R1. In order to determine the digital value at the time point R1 of the reference clock REFCLK, an analog signal is sampled at the time points L1, L2, L3, L4, and L5 in synchronization with the oversampling clock and converted into a digital value, respectively. When c, d, and e, the weighted sum a * 1 + b * 3 + c * 5 + d * 3 + e * 1 can be defined as the final digital value. In this case, it is effective to improve the resolution by making the weight of the value sampled at the point L3 close to the reference clock R1 larger than the weight of the value sampled at the points L1 and L5 farther than the point R1. Can be.

In an embodiment of the present invention, an oversampling clock (OVERCLK) having a frequency four times the frequency of the reference clock (REFCLK) is used and sampled at five times as many times as the sampling time of the reference clock. You can.

2 is a block diagram showing the structure of an analog-to-digital converter for performing an analog-to-digital conversion according to an embodiment of the present invention.

Referring to FIG. 2, the analog-digital converter detects a phase change amount of an oscillation signal output by a voltage controlled oscillator 210 and a voltage controlled oscillator 210 that generate an oscillation signal in proportion to an input voltage, and corresponds to a digital change corresponding to a phase change amount. And a phase change detector 220 for outputting a code.

Analog-to-digital conversion method according to an embodiment of the present invention uses a voltage controlled oscillator 210 to quantize the analog value. The size of the quantized unit may be determined according to the number of delay stages included in the voltage controlled oscillator 210. The voltage controlled oscillator 210 includes four delay stages, and each delay stage may be implemented as a fully differential ring oscillator for inverting and outputting an input signal. Therefore, all four output stages have eight output stages, and each of the eight oscillation signals outputted from each output stage has a phase difference as much as propagation delay of the delay stage. Depending on the embodiment, the type of voltage controlled oscillator or the number of delay stages may vary. Since the voltage controlled oscillator 210 outputs an oscillation signal having a frequency proportional to an input voltage, analog-to-digital conversion is possible by detecting a frequency of the oscillation signal through the phase change amount detector 220. Since the frequency is proportional to the phase change amount for a predetermined time, the same function can be performed even by detecting the phase change amount instead of the frequency. Hereinafter, the term "phase change amount" instead of the term "frequency" will be described.

The phase change amount detector 220 detects a phase change amount of the oscillation signal output from the voltage controlled oscillator 210 and outputs a digital code corresponding to the phase change amount. In an embodiment of the present invention, the oscillation signal is detected at each output terminal of the voltage controlled oscillator 210 in order to obtain high resolution.

The phase change detector 220 may include a first detector 221, a second detector 222, a third detector 223, and a phase information synthesizer 224. The first detector 221, the second detector 222, and the third detector 223 partially detect a phase change amount of the oscillation signal output from the voltage controlled oscillator 210 and convert the phase information into a phase information synthesizer 224. The phase information synthesizing unit 224 generates the final digital code by synthesizing the phase information of the first detecting unit 221, the second detecting unit 222, and the third detecting unit 223.

3 is a waveform diagram illustrating an oscillation signal output from each output terminal of a delay stage of a voltage controlled oscillator.

Referring to FIG. 3, each output stage of the plurality of delay stages included in the voltage controlled oscillator outputs a plurality of oscillation signals OSC1 to OSC8 having a phase difference from each other by a unit delay time TD. When one of the plurality of oscillation signals OSC1 to OSC8 is selected as the reference oscillation signal OSC1, the remaining oscillation signals OSC2 to OSC8 have a phase difference of a unit delay time TD compared to the previous oscillation signal, respectively.

4 is a waveform diagram comparing a reference oscillation signal OSC1 with a reference clock REFCLK and an oversampling clock OVERCLK.

The oversampling clock OVERCLK has an integer multiple of the frequency of the reference clock REFCLK. Referring to FIG. 4, the method according to an embodiment of the present invention uses an oversampling clock OVERCLK having a frequency of four times. . The reference clock REFCLK may be an actual physical clock for generating an oversampling clock OVERCLK through a frequency multiplier, or may be a virtual meaning indicating a time ratio at which a digital code value is output. In order to generate the oversampling clock (OVERCLK), a circuit capable of delaying the signals at equal intervals is required. It is effective to generate an oversampling clock using a delay locked loop having a good jitter characteristic. Can be.

Unlike the general method of sampling one analog data in every cycle of the reference clock REFCLK in synchronization with the reference clock REFCLK, an integer multiple of the analog data in every cycle of the reference clock REFCLK in synchronization with the oversampling clock OVERCLK. After sampling, one output value is determined from the plurality of sampling values.

In FIG. 4, four periods of the oversampling clock OVERCLK are repeated during each period of the reference clock REFCLK. Since the frequency ratio of the reference clock and the oversampling clock and the number of times of detecting the analog signal per cycle of the reference clock are not necessarily the same, an embodiment of the present invention will be described in the case where the amount of phase change is detected five times. In order to sample in synchronization with the oversampling clock OVERCLK, a phase change amount of the oscillation signal is detected during each period (PD1 to PD5) of the oversampling clock OVERCLK. Therefore, the phase change amount of the oscillation signal corresponding to each period PD1 to PD5 of the oversampling clock OVERCLK is detected five times during one period of the reference clock REFCLK.

Hereinafter, an example of a process of detecting a phase change amount in the third period PD3 of the five periods PD1 to PD5 of the oversampling clock CLK will be described. The amount of phase change of the remaining periods (PD1, PD2, PD4, PD5) can also be detected by the same method.

Since the rising edge of the reference oscillation signal OSC1 is present in the third period PD3, the first edge of the interval between the start point of every cycle of the oversampling clock OVERCLK and the first rising edge of the reference oscillation signal OSC1. 1 section PH1, the first rising edge of the second section PH2, the reference oscillation signal OSC1, which is a section between the last rising edge of the reference oscillation signal OSC1 and the end point of every cycle of the oversampling clock OVERCLK. And a third section (PH3) section which is a section between the last rising edge. Therefore, when the first period PH1, the second period PH2, and the third period PH3 are added together, one period PD3 of the oversampling clock OVERCLK is obtained. In the first detection unit 221, the second detection unit 222, and the third detection unit 223 in FIG. 2, the first detection unit 221, the second detection unit 223, and the third detection unit 223 respectively, respectively. When the phase change amount of the reference oscillation signal OSC1 is detected and the phase change amount of the first period PH1, the second period PH2, and the third period PH3 is summed in the phase information synthesizing unit 224 of FIG. 2. The amount of phase change of the reference oscillation signal during one period PD3 of the oversampling clock OVERCLK is detected. The phase change amount of the third section PH3 may be detected by counting the rising edge of the reference oscillation signal during one period PD3 of the oversampling clock OVERCLK using the counter included in the third detector 223. . If K rising edges of the reference oscillation signal OSC1 are detected during the phase detection unit section PD3, the amount of phase change is 360 degrees (K-1). For the sake of convenience, the phase change amount of 360 Hz may be represented by a numerical value of 8 × (K-1).

5 is a waveform diagram illustrating a detection process of a phase change amount in a first section.

5 shows waveforms of the oscillation signals OSC2 to OSC8 having a phase difference by the unit delay time TD together with the reference oscillation signal OSC1. The reference oscillation signal OSC1 may divide one period into eight equally spaced periods D1 to D8, where one interval corresponds to a unit delay time TD. In order to detect the amount of phase change in the first section PH1, all output values of the oscillation signals OSC1 to OSC8 are checked. In an exemplary embodiment, when an oscillation signal whose logic value is changed from 1 to 0 is searched among the oscillation signals, the amount of phase change of the first section PH1 may be approximately detected.

Referring to FIG. 5, when the rising edge of the oversampling clock appears, the oscillation signals OSC1 to OSC3 have a logic value of 0, the oscillation signals OSC4 to OSC7 have a logic value of 1, and the oscillation signals ( OSC8) has a logical value of zero. That is, since the logic value 1 in the seventh oscillation signal OSC7 is changed to the logic value 0 in the eighth oscillation signal OSC8, the seventh section (D1 to D8) of the equal intervals of the reference oscillation signal OSC1 ( It can be seen that the rising edge of the oversampling clock has occurred in D7). Since the phase change of 360 Hz is expressed as 8 for convenience, the phase change amount of the first section PH1 is 1 Can be detected approximately. In the same principle, if the rising edge of the oversampling clock appears in the third section (D3) of the equal intervals (D1-D8) of the reference oscillation signal, the fourth having the logical value 1 in the third oscillation signal (OSC3) The oscillation signal OSC4 will change to a logic value of zero.

6 is a waveform diagram illustrating a detection process of a phase change amount in a first section.

In FIG. 6, the method for detecting the amount of phase change in the second section PH2 is similar to the description of FIG. 4. In order to detect the amount of phase change in the second section PH2, all output values of the oscillation signals OSC1 to OSC8 are checked. In an exemplary embodiment, when an oscillation signal whose logic value changes from 1 to 0 is searched among the oscillation signals OSC1 to OSC8, an interval of P1 may be approximately detected.

Referring to FIG. 6, when the rising edge of the oversampling clock occurs in the second period D2 of the equal intervals D1 to D8 of the reference oscillation signal, the oscillation signals OSC1 to OSC2 set the logic value 1. In addition, the oscillation signals OSC3 to OSC6 have a logic value of 0, and the oscillation signals OSC7 to OSC8 have a logic value of 1. That is, since the logic value 1 in the second oscillation signal OSC2 is changed to the logic value 0 in the third oscillation signal OSC3, the second section D2 of the equal intervals D1 to D8 of the reference oscillation signal OSC1 is changed. It can be seen that the rising edge of the oversampling clock has occurred, and, for convenience, if the phase change of 360 Hz is expressed as a numerical value 8, the interval of the second period PH2 can be approximately detected as the numerical value 2.

As described with reference to FIGS. 5 and 6, when the oscillation signal of each output stage of the delay stage is used, the amount of phase change can be detected in units of 360 Hz as if only one rising edge of the oscillation signal is counted and converted into a digital code. Compared to the present invention, the amount of phase change can be detected more precisely, thereby improving resolution. Depending on the embodiment, the number of delay stages may be properly adjusted.

7 is a flowchart illustrating an analog-digital conversion method according to an embodiment of the present invention.

1 to 7, the analog-to-digital conversion is comprehensively explained by oversampling.

When the analog-to-digital conversion is started, a reference clock is generated (S100), and oversampling having a frequency of an integer (N) times of the reference clock is generated (S200). In this case, the oversampling clock may be generated using a delay locked loop. The analog signal is sampled in synchronization with the oversampling clock (S300) and then converted into a digital value (S400). This process may be performed by detecting the amount of phase change of the oscillation signal output from the voltage controlled oscillator as described above. This process (S300 ~ S400) is repeated M times to convert the analog signal to M digital values (S500). In order to determine one output value, a weight of each digital value is determined (S600), and a digital code is determined and output by a weighted sum of the digital value and the weight (S700).

When the sampling frequency was 100MHz, the analog-to-digital converter of FIG. 2 was simulated using the spectrum, and the resolution was 5 bits. However, the resolution was increased to 6.5 bits using the oversampling method according to the embodiment of the present invention.

According to an embodiment of the present invention as described above, a voltage controlled oscillator is used to quantize analog signals, and a plurality of analog values are sampled for one period of a reference clock, and the digital codes to be output are given with their respective weights. The decision improves the resolution of the analog-to-digital converter without the sample-and-hold circuit.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (7)

Generating an oversampling clock having a frequency of N (N is a natural number of two or more) times the reference clock; Outputting a plurality of oscillation signals having a phase difference to each output terminal of the plurality of delay stages included in the voltage controlled oscillator corresponding to the analog input signal; In synchronization with the oversampling clock, phase shift amounts of the plurality of oscillation signals are detected M times (M is a natural number of 2 or more) every period of the reference clock, and M digital values are based on the detected phase shift amounts. Determining; Determining a weight for each of the M digital values; And And determining one digital code based on the M digital values and the weights. The method of claim 1, wherein generating the oversampling clock comprises fixing the oversampling clock using a delay locked loop. The method of claim 1, wherein detecting the phase change amounts M times and determining M digital values based on the detected phase change amounts And detecting phase shift amounts of the plurality of oscillation signals in synchronization with M consecutive rising edges of an oversampling clock. delete The method of claim 1, wherein detecting the phase change amounts M times and determining M digital values based on the detected phase change amounts Based on the plurality of oscillation signals, detecting the first phase change amount M times from the start of every cycle of the oversampling clock to the rising edge of the first reference oscillation signal that occurs first during every cycle of the oversampling clock; step; Based on the plurality of oscillation signals, detecting a second phase change amount M times from a rising edge of the reference oscillation signal last appearing during each period of the oversampling clock to the end of every cycle of the oversampling clock; step; And Detecting the third phase change amount M times from the rising edge of the reference oscillation signal first appearing during each period of the oversampling clock, to the last rising edge of the reference oscillation signal. . The method of claim 1, wherein the determining of the M weights comprises comparing weights of signals oversampled at a time closer to the start point of each cycle of the reference clock by comparing the start point of every cycle of the reference clock. Determining a greater than the weight for the oversampled signal at a point far from the start of each period of the reference clock. 2. The method of claim 1, wherein determining the one digital code comprises determining one digital code by weighted sum of the M digital values and respective weights.

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