KR100849531B1 - Method of direct memory access in digital signal processor and digital signal processor by using the same - Google Patents

Abstract

Disclosed are a direct memory access method of a digital signal processing apparatus and a digital signal processing apparatus using the same. According to a preferred embodiment of the present invention, in a direct memory access method of a digital signal processing apparatus of an n-bit processing unit connected to an external memory having an m-bit bandwidth, data written to the external memory is read in m-bit units ( read) and transfer the read data to the internal data memory with the memory width of lxk (l is a natural number of 1 or more, k is the least common multiple of m and n) in units of m bits, but the data stored in the internal data memory is Provided is a direct memory access method of a digital signal processing apparatus, which is read and calculated in units of n bits.

According to the present invention, there is no need for a combination circuit for various data input and output, there is an advantage that does not reduce the processing speed of the DSP.

Digital Signal Processor, DSP, DMA, Direct, Memory, Access, FIFO

Description

Method of direct memory access in digital signal processor and digital signal processor by using the same}

1 illustrates an interface for direct memory access in a conventional DSP.

2 is a diagram illustrating a process of storing data in a data memory by a direct memory access method in a conventional DSP.

3 illustrates an interface for direct memory access in a DSP in accordance with one preferred embodiment of the present invention.

4 is a diagram illustrating a process of storing data in a data memory by a direct memory access method in a DSP according to an exemplary embodiment of the present invention.

5 is a diagram illustrating a process of reading data stored in a data memory in a DSP according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor (DSP), and more particularly, to a direct memory access method of a DSP and a DSP using the same when a bandwidth between the DSP and an external memory is different.

A DSP is a microprocessor of one integrated circuit (IC) chip that processes signals by digital operations.

DSPs are widely used in speech and communication devices, mainly speech synthesis, speech recognition, speech encoding, compression, high speed modems, echo cancellation devices, and the like. In particular, since it shows excellent performance in mathematical operations, DSP is more widely used than a general processor to process speech data having many mathematical operations such as Hoffman decoding and inverse quantization.

DSP has built-in hardware design and built-in floating point operation for mathematical operation or multiply and accumulation (MAC) operation function that can perform multiplication and addition in one cycle. It can also be configured to perform the above instructions and to perform repetitive operations quickly.

Direct memory access (DMA) is a memory access method that improves the input / output speed of data by transferring data directly to a memory device, without executing a separate program.

On the other hand, the DSP is configured to include a program memory and a data memory to be used by the program, and the data memory may be composed of two X memories and two Y memories.

The program is stored in the program memory, and also in the case of digital voice signal data such as MP3, WMA, and ACC for voice data processing.

The program stored in the program memory is fetched, decoded, and executed by a DSP core that actually performs an operation. The DSP core may include components such as a compiler or debugger.

The program memory is composed of 32 bits equal to the bandwidth of the external memory because the program input from the external memory is transmitted and stored.

However, currently widely used DSP has a processing unit of 24 bits, so the data memory in which data calculated in the DSP is stored is composed of a memory having 24-bit bandwidth.

Therefore, since the data memory has a bandwidth of 24 bits, there is a problem that the bandwidth does not match with the external memory when inputting / outputting data from the data memory to the external memory.

A DSP configuration has been proposed to solve this problem, but a problem has arisen in such a case. This will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, a configuration and data input / output of a conventional DSP for solving a problem in which bandwidths do not coincide with each other when data is input / output from the data memory to the external memory are described.

1 is a diagram illustrating an interface for direct memory access in a conventional DSP.

As shown in FIG. 1, a conventional DSP includes a plurality of DSP DMA controllers 100a, 100b, ..., hereinafter referred to collectively as 100, a selector 1 (110), and a selector 2 (120). AHB (Advanced High-performance Bus) master (130), DSP slave (Slave) 140, AHB slave 150, SFR (Special Function Register) (160).

Although not shown in FIG. 1, the DSP further includes a DSP core that reads and executes an instruction, and further includes a program memory and a data memory inside the DSP.

The DSP DMA control unit 100 included in the conventional DSP includes an AHB master 102, a FIFO 104, and a DSP master 106 as a part for controlling direct memory access to data memory and program memory in the DSP.

The FIFO 104 is a first-in, first-out device or circuit that is added in hardware for each channel to solve the problem that the bandwidths of the DSP and data memory do not match each other. FIFO 104 implements a method that adds a time stamp when certain data is imported to replace the first imported data when other data needs to be imported.

The data introduced into the FIFO 104 accesses the data memory through an interface between the DSP DMA controller 100 and the data memory.

Therefore, a combination circuit for a variety of data input and output, such as data input and output between the data memory and the DSP, data input and output between the program memory and the DSP is required, the use of the various combination circuits, there is a problem that reduces the processing speed of the DSP.

In order to reduce the processing speed of the DSP, there is a method of increasing the main clock frequency of the DSP, but in this case, there is a problem in that power consumption is increased.

In addition, the problem of inputting data from the DSP into the data memory will be described with reference to FIG. 2.

2 is a diagram illustrating a process of storing data into a data memory by a direct memory access method in a conventional DSP.

2 illustrates a case in which a DSP having a conventional 24-bit processing unit reads data from a 32-bit external memory 200 and stores data in a 24-bit data memory 210.

As shown in FIG. 2, first, data is sequentially read from the LSB of the external memory 200 having a 32-bit bandwidth in the horizontal direction and sequentially written to the FIFO 104 from below, and the data written to the FIFO 104. Are sequentially recorded in the horizontal direction from the LSB of the data memory 210 having a 24-bit bandwidth.

However, in this case, the bandwidth of the external memory 200 is 32 bits, whereas the bandwidth of the data memory 210 is 24 bits. Therefore, a data loss in which some of the data read from the external memory and written to the FIFO 104 is lost is lost. There is a problem that occurs.

In order to prevent such data loss, a method of reading data from the external memory 200 to the FIFO 104 only once and reading the data recorded in the FIFO 104 twice into the data memory 210 may be applied. In this case, there is a problem in that the remaining storage space of the data memory 210 having a 24-bit bandwidth is filled with so-called 'garbage value' which is meaningless data.

The 'garbage value' recorded in such a data memory is, for example, especially in the case of audio data, there is a problem such that noise is generated if the program creator does not know the program in advance and does not program it to be decoded.

In order to solve the conventional problems as described above, the present invention does not require a combination circuit for various data input and output, such as data input and output between the data memory and the DSP, data input and output between the program memory and the DSP does not reduce the processing speed of the DSP Disclosed are a direct memory access method in a digital processing device and a digital signal processing device using the same.

In addition, the present invention proposes a direct memory access method and a digital signal processing apparatus using the same in a digital processing apparatus that can reduce power consumption by not increasing the main clock frequency of the DSP so as not to reduce the processing speed of the DSP.

The present invention also proposes a direct memory access method and a digital signal processing apparatus using the same in a digital processing apparatus such that the data memory is not filled with a so-called 'garbage value' that is data having no data loss or meaning.

Still other objects of the present invention will be readily understood through the following description of the embodiments.

In order to achieve the above object, according to an aspect of the present invention, a direct memory access method in a digital processing apparatus is provided.

According to a preferred embodiment of the present invention, in a direct memory access method of a digital signal processor (DSP) of an n-bit processing unit connected to an external memory having an m-bit bandwidth, the external memory recorded in the external memory (A) reading data in m-bit units; And transmitting (b) the read data to an internal data memory having a memory width of lxk (l is a natural number of 1 or more, k is a least common multiple of m and n) in units of m bits. Provided is a direct memory access method of a digital signal processing apparatus, wherein the data stored in the data memory is read and calculated in units of n bits.

The data transmission may be performed through an advanced high-performance bus (AHB).

Transmitting the received data to an internal data memory having a memory width of k bits (k is a least common multiple of m and n) in m-bit units from LSB (Least Significant Bit) of the internal data memory to m-bit units. May be performed sequentially.

According to another aspect of the present invention, a digital signal processing apparatus is provided.

According to an embodiment of the present invention, in a digital signal processor (DSP) of an n-bit processing unit connected to an external memory having an m-bit bandwidth, lxk (l is a natural number of 1 or more, k is m An internal data memory having a memory width in units of bits); And a DSP DMA (Direct Memory), in which data read in m-bit units from the external memory is written to the internal data memory in m-bit units, and data written from the internal data memory is read in n-bit units for calculation. Access) There is provided a digital signal processing apparatus comprising a control unit.

The internal data memory may be plural.

The digital signal processing apparatus may include an internal program memory that stores a program, and may include a DSP core that fetches, decodes, and executes a program stored in the program memory according to an input command. .

The digital signal processing apparatus may include a bus for transmitting data and control signals, and the bus may be an advanced high-performance bus (AHB) scheme.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be.

On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention.

Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art.

Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, and the same or corresponding components will be denoted by the same reference numerals regardless of the reference numerals and redundant description thereof will be omitted.

First, a digital signal processor (DSP: Digital Signal Processor (DSP)) according to an exemplary embodiment of the present invention will be described with reference to FIG. 3.

3 is a diagram illustrating an interface for direct memory access in a DSP according to an embodiment of the present invention.

Although not shown in FIG. 3, the DSP according to an exemplary embodiment of the present invention includes a program memory and a data memory to be used by the program. In addition, the data memory may be configured of two X memories and Y memories, but is not limited thereto.

The program is stored in the program memory, and in the case of digital voice signal data such as MP3, WMA, and ACC for voice data processing, the program memory may be stored in the program memory.

Also, the DSP may further include a DSP core that fetches, decodes, and executes a program stored in a program memory according to an input command.

In the following description, a DSP including a DSP core having a 24-bit processing unit and a program memory having a 32-bit bandwidth will be described as an example. However, direct memory access in a digital processing apparatus according to the present invention will be described. It is apparent that the method and the digital signal processing apparatus using the same can be applied to a DSP including a program memory having a different bandwidth and a DSP core.

As shown in FIG. 3, a DSP according to an exemplary embodiment of the present invention includes a plurality of DSP DMA controllers 300a, 300b,..., 300, a selector 1 310, and a selector. 2 (320), Advanced High-performance Bus (AHB) master (330), DSP slave (Slave) (340), AHB slave 350, may include a SFR (Special Function Register) (360). .

The DSP DMA control unit 300 is a part for controlling direct memory access to the data memory and the program memory, and includes only the DSP master 302 as shown in FIG.

Compared with the conventional DSP DMA control unit, the FIFO and AHB masters are not included, and the data to be input / output is directly input / output through the DSP master 302.

The DSP DMA controller 300 may include a DSP master 302 having a 32-bit bandwidth to receive data in 32-bit bandwidth from an external memory having a 32-bit bandwidth. Can pass data

Accordingly, unlike the related art, the DSP DMA controller 300 is configured to interface with an external memory having a 32-bit bandwidth without considering another bandwidth (for example, 24 bits).

The selector 1 310 is a device that selectively transfers data transmitted through the plurality of DSP DMA controllers 300 to the devices (for example, DSP cores, etc.) other than the internal memory of the DSP through the AHB.

The selector 2 320 selectively transfers data transmitted from the plurality of DMA controllers 300 to a program memory or a data memory.

The AHB master 330 and the AHB slave 350 are components for supporting the AHB scheme, which is one of the AMBA bus specifications.

AMBA (Advanced Microcontroller Bus Architecture) is an open standard bus specification developed by ARM, which includes Advanced High-performance Bus (AHB), Advanced System Bus (ASB) and Advanced Peripheral Bus (APB).

AHB is a high clock frequency, high performance bus with a wide bandwidth and supporting a number of master devices, for example, used in memory controllers, interrupt controllers and the like.

The ASB, like the AHB, supports one or more master devices as a high-performance bus or a lower-performance bus than the AHB, while the APB supports a register-mapped slave device as a low-speed, low-power bus that reduces complexity to support peripheral functions. .

In FIG. 3, an AHB master and an AHB slave are used as an example of an AHB widely used in a DSP. However, the bus system for transmitting data and control signals is not limited thereto.

The DSP slave 340 is a device to which a control signal or data input from an external memory is first transmitted.

The AHB slave 350 receives data from the AHB master and transfers the data to a special function register (SFR), and the SFR 360 temporarily stores information on data repeatedly or periodically processed by the DSP as a type of register.

The data temporarily stored in the SFR 360 is selectively transferred to the program memory or the data memory by the selection unit 2 320 according to a control signal from the DSP core (not shown).

On the other hand, the configuration of the DSP DMA control unit 300 does not include the FIFO or the AHB master in the DSP DMA control unit, unlike the prior art, the circuit configuration is simplified in hardware.

In addition, the connection from the external memory to the data memory through the DSP DMA control unit has 32-bit bandwidth.

Therefore, the circuit configuration is simpler than in the related art, and data is transmitted through a bus having a 32-bit bandwidth, which does not reduce the processing speed of the DSP.

The structure of the internal data memory where data is transmitted through the bus with 32-bit bandwidth and the process of storing the data will be described.

Even if the DSP DMA controller 300 is configured without including the FIFO or the AHB master, the processing bandwidth of the DSP and the bandwidth of the external memory are different. Therefore, the configuration of the data memory and the data storage must be handled differently.

Hereinafter, a process of storing data in the data memory will be described with reference to FIG. 4.

First, a width of a data memory included in a DSP according to an exemplary embodiment of the present invention is determined by the processing unit of the DSP and the bandwidth of the external memory 400, and the values of the data memory are determined by the processing unit and the external memory of the DSP. It is determined by the least common multiple of the bandwidth of 400).

For example, if the bandwidth of a 24-bit processing unit and the external memory connected to the DSP is 32 bits, the width of the data memory is 96 bits (that is, the least common multiple of 24 and 32).

Of course, it is obvious that the width of the data memory can be determined by an integer multiple of the least common multiple of the processing unit of the DSP and the bandwidth of the external memory 400.

As illustrated above, if the bandwidth of the 24-bit processing unit and the external memory connected to the DSP is 32 bits, the width of the data memory is not only 96 bits but also 192 bits and 288 bits.

Memory for ASIC (Application Specific Integrated Circuit) operations is created by entering depths and widths into the memory generator.

The data memory inside the DSP according to the preferred embodiment of the present invention is arbitrarily determined as necessary for the system including the DSP, and the memory width is generated as 96 bits having a least common multiple of 24 and 32.

With reference to the creation and configuration of the data memory, the process of storing the data read from the external memory in the data memory included in the DSP will be described.

4 is a diagram illustrating a process of storing data in a data memory by a direct memory access method in a DSP according to an exemplary embodiment of the present invention.

As shown in FIG. 4, when the external memory 400 having a bandwidth of 32 bits has a memory width of 4, data is stored by 8 bits in one cell, which is a space in which data is stored. 32 bits of stored data stored in four cells of 8 bits each is one word.

On the other hand, the data memory 410 inside the DSP is generated with 96 bits, which is the least common multiple of 24 and 32, resulting in a memory having three words.

On the other hand, when storing or reading in the memory in general, since it is stored and read from the LSB (Least Significant Bit), the data transmitted from the external memory 400 may be stored from the LSB in the data memory 410 inside the stored DSP, but It is not limited.

First, when the data of the external memory 400 is stored in the internal data memory 410, the buses between the DSP DMA controller 300, the external memory 400, the DMA controller 300, and the internal data memory 410 are 32 respectively. Since the bit bandwidth is stored in the internal data memory 410 in units of 32 bits.

Therefore, if the method is sequentially performed, all data is stored in the internal data memory 410 without losing data stored in the external memory 400.

On the other hand, a case in which data is read in order to perform the operation of the data stored by such a method in the DSP will be described with reference to FIG. 5.

As shown in FIG. 5, since the processing unit of the DSP is 24 bits, the DSP reads data stored in the internal data memory 410 by three cells, that is, 24 bits, and processes the read data in the DSP core 500. Will be performed. Therefore, by reading the 96-bit data written in three words of 32 bits four times in the internal data memory 410, it is possible to read all the data without losing data.

In addition, the storage space to be filled with so-called 'garbage value' which is meaningless data in the internal data memory 410 does not occur at all.

Therefore, according to the DSP of the present invention, even when the bandwidth between the external memory and the DSP is different, all data stored in the external memory can be stored in the data memory 410 inside the DSP without losing data, and meaningless data is stored in the internal data. The data may be stored in the internal data memory 410 of the DSP without being filled in the storage space of the memory 410 and data may be read for data processing such as an operation.

Preferred embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit and scope of the present invention. Additions should be considered to be within the scope of the following claims.

As described above, the direct memory access method of the digital processing apparatus and the digital signal processing apparatus using the same according to the present invention do not require a combination circuit for various data inputs and outputs and thus do not reduce the processing speed of the DSP.

In addition, there is an advantage in reducing power consumption since the DSP does not increase the processing speed of the DSP, thereby increasing the DSP's main clock frequency.

In addition, there is an advantage that the data memory is not filled with so-called 'garbage value', which is data loss or meaningless data.

Claims (9)

In the direct memory access method of a digital signal processor (DSP) of n-bit processing unit connected to an external memory having an m-bit bandwidth, (A) reading data written in the external memory in units of m bits; And (B) transferring the read data to an internal data memory having a memory width in units of bits of l x k (l is a natural number of 1 or more, k is a least common multiple of m and n) in units of m bits, The data stored in the internal data memory is read and calculated in units of n bits, the direct memory access method of the digital signal processing apparatus. The method of claim 1, Step (a) and step (b), A direct memory access method of a digital signal processing device, characterized in that it is performed through an Advanced High-performance Bus (AHB). The method of claim 1, Step (b) is, Direct memory access method of a digital signal processing apparatus, characterized in that sequentially performed from the LSB (Least Significant Bit) of the internal data memory in m-bit units. A digital signal processor (DSP) of an n-bit processing unit connected to an external memory having an m-bit bandwidth, an internal data memory having a memory width in units of l x k (l is a natural number greater than or equal to 1, k is a least common multiple of m and n); And DSP Direct Memory Access to allow data read out from the external memory in units of m bits to be written to the internal data memory in units of m bits, and to read data written from the internal data memory in units of n bits for operation. Digital signal processing apparatus comprising a control unit. The method of claim 4, wherein The internal data memory is a plurality of digital signal processing apparatus, characterized in that The method of claim 4, wherein And an internal program memory for storing a program. The method of claim 6, And a DSP core that fetches, decodes, and executes a program stored in the internal program memory according to an input command. The method of claim 4, wherein A digital signal processing apparatus further comprising a bus for transmitting data and control signals. The method of claim 8, The bus is a digital signal processing device, characterized in that the AHB (Advanced High-performance Bus) system.

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