KR100842917B1 - Semiconductor device and method for forming thereof - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided to protect effectively an element from plasma damage by connecting electrically a forward diode and a backward diode to an electrode of the element. An element includes an electrode which is electrically connected to conductive lines of an upper part. A first diode(D3) is connected in an electrically backward direction to the electrode. A second diode(D4) is connected in an electrically forward direction to the electrode. Both ends of the second diode are connected to the electrode through two conductive lines of different layers. In the process for forming the conductive lines, plasma charges applied to the element through the electrode are erased by using the first diode and the second diode. The electrode and ends of the first and second diodes are commonly connected to the conductive line of the lowest layer.

Description

Semiconductor device and method for forming the same {SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THEREOF}

1 is a circuit diagram showing an example of a conventional semiconductor device.

2 is a circuit diagram showing another example of a conventional semiconductor device.

3 is a circuit diagram of a semiconductor device according to an embodiment of the present invention.

4 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

5A through 5E are cross-sectional views illustrating processes of forming a semiconductor device in accordance with an embodiment of the present invention.

6 is a circuit diagram of a semiconductor device according to another embodiment of the present invention.

7 is a sectional view of a semiconductor device according to another embodiment of the present invention.

8A through 8E are cross-sectional views illustrating processes of forming a semiconductor device in accordance with another embodiment of the present invention.

TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of protecting an element from plasma damage and a method of forming the same.

In general, a process based on plasma widely used in semiconductor device fabrication, for example, dielectric deposition, dielectric etching, metal etching, and photoresist Plasma process induced damage may occur during resist removal.

That is, the charging current generated during the plasma process during the fabrication of the semiconductor device is accumulated in the gate of the device, and the high electric field generated by the semiconductor device causes the electrical characteristics of the device, for example, the threshold voltage ( transition of threshold voltage, reduction of drain current, deterioration of characteristics of the gate oxide film, and the like, resulting in a decrease in reliability and yield of the device.

As a typical representative method for solving such plasma damage, a structure in which reverse diodes D1 and D2 are connected to gates of transistors N1 and P1 may be disclosed as shown in FIGS. 1 and 2, respectively. .

As described above, when the reverse diodes D1 and D2 are connected to the gates of the transistors N1 and P1, the charging currents generated by the plasma process are discharged to the leakage currents of the protection diodes D1 and D2, respectively. As a result, charging current accumulated in the gate can be reduced.

However, since both positive and negative charges are generated during the plasma process, the structure in which the conventional reverse diodes D1 and D2 are connected has a problem of protecting the device from the plasma charging current.

In other words, the diodes D1 and D2 send a larger leakage current when a forward bias is applied than the reverse bias.

Therefore, in the structure in which the reverse diode D1 is connected to the NMOS transistor N1 as shown in FIG. 1, the negative charge generated during the plasma process may be sufficiently discharged, but the positive charge may not be sufficiently discharged by the reverse diode D1. Damage may occur.

Similarly, in the structure in which the reverse diode D2 is connected to the PMOS transistor P1 as shown in FIG. 2, the positive charge generated during the plasma process may be sufficiently discharged, but the negative charge may not be sufficiently discharged by the reverse diode D2. Damage may occur.

An object of the present invention is to effectively discharge the plasma charge charged to the electrode of the device during the plasma process.

Another object of the present invention is to protect the device from plasma damage regardless of the electrode of the plasma generated during the plasma process.

According to an aspect of the present invention, there is provided a semiconductor device including: an element having an electrode electrically connected to upper conductive lines; A first diode electrically connected in reverse with respect to the electrode; And a second diode electrically connected to the electrode in a forward direction, and a second diode electrically connected to the electrode through two conductive wires of different layers of the conductive wires. The erasing of the plasma charges that can flow into the device through an electrode is performed by the first and second diodes.

Here, it is preferable that the electrode and one end of the first and second diodes are electrically connected in common to the conductive wires formed at the lowest of the conductive wires formed on the electrode.

In addition, the cathode of the second diode is preferably electrically connected to the electrode through the conductive wiring of the upper layer of the two conductive wirings of the different layers.

In addition, the anode of the first diode is preferably connected to ground, and in particular, the anode of the first diode is preferably connected to the bulk of the device.

In addition, the device is preferably a MOS transistor having a gate electrode.

According to another aspect of the present invention, there is provided a semiconductor device including: a substrate having a plurality of junction regions formed in well regions and at least well regions for forming at least first and second diodes and transistors; A gate layer formed on the substrate between two well regions forming a channel region of the transistor; A lowermost conductive wiring layer commonly connecting the gate with at least two of the junction regions for electrically reverse and forward coupling with respect to the gate of the transistor; And upper conductive wiring layers formed on the lower conductive wiring layer and electrically connected to the lower conductive wiring layer, wherein the second diode is different from a well region forming the first diode of the junction regions. A first junction region of a type and a second junction region of the same type constituting said first diode, said second junction region being electrically connected to the gate of said transistor through any one of said upper conductive wiring layers; The erasing path of the plasma charge introduced during the formation of the upper conductive interconnection layers is formed by the first and second diodes.

Here, the first and second diodes preferably discharge the plasma charge flowing through the upper conductive wiring layers to well regions formed in the substrate through the lowest conductive wiring layer.

In addition, the first diode may be formed by forming a junction region in a well region corresponding to the bulk of the transistor.

In addition, the upper conductive wiring layer electrically connected to the second junction region is preferably a conductive wiring layer formed on the top of the upper conductive wiring layers.

The method of forming a semiconductor device of the present invention for achieving the above object comprises the steps of: forming well regions for forming at least first and second diodes and transistors on a substrate and a plurality of junction regions in the well regions; ; Forming a gate layer on the substrate between two well regions of the well regions that form a channel region of the transistor; Forming a bottommost conductive wiring layer commonly connecting the gate with at least two of the junction regions for electrical reverse and forward coupling to a gate of the transistor; And forming upper conductive wiring layers electrically connected to the lowest conductive wiring layer, wherein the second diode comprises: a first junction region of a type different from a well region forming the first diode; A second junction region of the same type constituting a diode, the second junction region being electrically connected to the gate of the transistor through any one of the upper conductive wiring layers, and entering during the formation of the upper conductive wiring layers The plasma charge is discharged to the well regions of the substrate via the first and second diodes.

The first diode may be formed by forming a junction region in a well region corresponding to the bulk of the transistor.

In addition, the upper conductive wiring layer electrically connected to the second junction region is preferably a conductive wiring layer formed on the uppermost of the upper conductive wiring layers.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The semiconductor device of the present invention can effectively discharge the positive and negative charges generated during the plasma process through the reverse diode and the forward diode connected to the electrode of the specific device.

Specifically, the structure of FIG. 3 may be disclosed as an example of the semiconductor device of the present invention.

Referring to FIG. 3, a semiconductor device according to an embodiment of the present disclosure may include an NMOS transistor N2, a reverse diode D3 electrically connected to the gate of the NMOS transistor N2, and an NMOS transistor N2. And forward diode D4 electrically connected to the gate.

Referring to FIG. 4, the structure thereof will be described in detail. In the semiconductor substrate 40 in which the P well 41 and the N well 42 are formed, the NMOS transistor N2 is formed by the gate 43 formed on the P well 41. And N + impurity junction regions 44a and 44b which are source and drain regions formed on both sides of the gate 43.

The reverse diode D3 includes an NP diode including a P well 41 as an anode region and an N + impurity junction region 45 as a cathode region formed in the P well 41.

In addition, the forward diode D4 includes an N well 42 as a cathode region, a P + impurity junction region 46 as an anode region formed in the N well 42, and an N + impurity junction region as a pickup region formed in the N well 42. Including 47, it is made of a PN diode.

The N + impurity junction region 45, the gate 43, and the P + impurity junction region 46 are electrically connected to the conductive wiring M0_1 through the contacts C0_1, C0_2, and C0_3 in common, and the N + impurity junction region ( 47 is electrically connected to the conductive wiring M0_2 through the contact C0_4.

Each of the conductive wires M0_1 and M0_2 is electrically connected to at least one conductive wire of the upper layer, and the conductive wires M0_1 and the conductive wires M0_2 are electrically connected to each other by the conductive wires formed on the uppermost layer. .

For example, when the conductive wiring is laminated in four layers, the conductive wiring M0_1 is electrically connected to the upper conductive wiring M1_1 through the contact C1_1, and the conductive wiring M1_1 is connected to the contact C2_1. It is electrically connected to the upper conductive wiring (M2_1) through. In addition, the conductive wire M0_2 is electrically connected to the upper conductive wire M1_2 through the contact C1_2, and the conductive wire M1_2 is electrically connected to the upper conductive wire M2_2 through the contact C2_2. do. The conductive wires M2_1 and M2_2 are electrically connected to the conductive wires M3 of the uppermost layer through the contacts C3_1 and C3_2, respectively.

A method of forming a semiconductor device according to an embodiment of the present invention having such a structure will be described below with reference to FIGS. 5A to 5E.

First, referring to FIG. 5A, in the semiconductor substrate 40 on which the P well 41 and the N well 42 are formed, the gate 43 having a stacked structure of a gate oxide film and a gate conductive film on the P well 41 is formed. Are formed, and N + impurity junction regions 44a and 44b implanted with high concentration ions are formed in P wells 41 on both sides of the gate 43. In the P well 41, the N + impurity junction region 45 is formed to be spaced apart from one of the N + impurity junction regions 44a and 44b, and the P + impurity junction region 46 and the N + are formed in the N well 42. The impurity junction region 47 is formed.

Next, referring to FIG. 5B, contacts C0_1, C0_2, C0_3, and C0_4 are formed on the N + impurity junction region 45, the gate 43, the P + impurity junction region 46, and the N + impurity junction region 47, respectively. ) Is formed.

Next, referring to FIG. 5C, the conductive wiring M0_1 is formed on the contacts C0_1, C0_2, and C0_3 so that the N + impurity junction region 45, the gate 43, and the contacts C0_1, C0_2, and C0_3 are formed. And the P + impurity junction region 46 and the conductive wiring M0_1 are electrically connected to each other. In addition, the conductive wiring M0_2 is formed on the contact C0_4 so that the N + impurity junction region 47 and the conductive wiring M0_2 are electrically connected to each other through the contact C0_4. Here, the conductive wiring M0_1 and the conductive wiring M0_2 are formed separately to electrically connect the N + impurity junction region 47 and the gate 43 in the uppermost conductive wiring process.

Next, referring to FIG. 5D, a contact C1_1 is formed on the conductive wire M0_1 and a conductive wire M1_1 is formed on the contact C1_1 for electrical connection with another element (not shown). The conductive wire M0_1 and the conductive wire M1_1 are electrically connected to each other through the contact C1_1. In addition, a contact C1_2 is formed on the conductive wiring M0_2, and a conductive wiring M1_2 is formed on the contact C1_2, so that the conductive wiring M0_2 and the conductive wiring M1_2 form a contact C1_2. Are electrically connected to each other through.

Next, referring to FIG. 5E, a contact C2_1 is formed on the conductive wire M1_1 and a conductive wire M2_1 is formed on the contact C2_1 to electrically connect with another element (not shown). The conductive wiring M1_1 and the conductive wiring M2_1 are electrically connected to each other through the contact C2_1. In addition, a contact C2_2 is formed on the conductive wire M1_2 and a conductive wire M2_2 is formed on the contact C2_2, so that the conductive wire M1_2 and the conductive wire M2_2 form a contact C2_2. Are electrically connected to each other through.

A contact C3_1 is formed on the conductive wiring M2_1, and a contact C3_2 is formed on the conductive wiring M2_2, and the uppermost conductive wiring M4 is formed on the two contacts C3_1 and C3_2. The conductive wires M2_1 and M2_2 are electrically connected to the conductive wires M4 through the contacts C3_1 and C3_2.

As can be seen in the process of the semiconductor device according to the embodiment of the present invention, the gate 43 of the NMOS transistor N2, the N + impurity junction region 45 which is a cathode region of the reverse diode D3, and the forward diode The P + impurity junction region 46, which is the anode region of D4, is electrically connected to each other through the lowest conductive wiring M0_1.

Therefore, most of the plasma charges occupied in the conductive film of the gate 43 by the conductive wiring M0_1 process are discharged to the P well 41 via the contact C0_1 and the N + impurity junction region 45 and at the same time, the contact is made. The N well 42 is discharged through the C0_4 and the P + impurity junction regions 46. At this time, most of the plasma negative charge is discharged to the P well 41 through the N + impurity junction region 45, and most of the plasma positive charge is discharged to the N well 42 via the P + impurity junction region 46. do. In addition, the plasma positive / negative charges generated in a subsequent conductive wiring process, that is, a process of forming upper conductive wires M1_1 and M2_1 electrically connected to the conductive wire M0_1, are also reversed diode D3 and forward diode D4. Can be sufficiently discharged.

That is, since the semiconductor device according to the embodiment of the present invention has a structure in which the reverse diode D3 and the forward diode D4 are connected to the gate 43 of the NMOS transistor N2, the semiconductor device may be applied to the positive / negative charges generated during the plasma process. Regardless, there is an effect that can effectively protect the NMOS transistor N2 from plasma damage.

In addition, in the final conductive wiring process, the gate 43 of the NMOS transistor N2 and the N + impurity extension region 47, which is a pickup region of the forward diode D4, are electrically connected to each other through the top conductive wiring M4.

Accordingly, since the anode and the cathode of the forward diode D4 are maintained at an equipotential when the NMOS transistor N2 is operated or the characteristic measurement is turned off, the forward diode D4 is operated during the NMOS transistor N2 operation or the characteristic measurement. It is possible to prevent defects caused by

According to another exemplary embodiment of the inventive concept, as illustrated in FIG. 6, the PMOS transistor P2, the reverse diode D5 electrically connected to the gate of the PMOS transistor P2, and the PMOS transistor P2 are electrically connected to each other. A structure including a forward diode D6 connected in electrical forward direction with respect to the gate of may be disclosed.

Referring to FIG. 7, the structure thereof will be described in detail. In the semiconductor substrate 70 having the N well 71 and the P well 72 formed thereon, the PMOS transistor P2 may have a gate 73 formed on the N well 71. And P + impurity junction regions 74a and 74b which are source and drain regions formed on both sides of the gate 73.

The reverse diode D5 is formed of a PN diode including an N well 71 serving as a cathode region and a P + impurity junction region 75 serving as an anode region formed in the N well 71.

In addition, the forward diode D6 includes the P well 72 as the anode region, the N + impurity junction region 76 as the cathode region formed in the P well 72, and the P + impurity junction region as the pickup region formed in the P well 72. It consists of an NP diode including 77.

The P + impurity junction region 75, the gate 73, and the N + impurity junction region 76 are electrically connected to the conductive wiring M0_1 through the contacts C0_1, C0_2, and C0_3 in common, and the P + impurity junction region ( 77 is electrically connected to the conductive wiring M0_2 through the contact C0_4.

Each of the conductive wires M0_1 and M0_2 is electrically connected to at least one or more conductive wires of the upper layer, and the conductive wires M0_1 and the conductive wires M0_2 are electrically connected to each other by the conductive wires formed on the uppermost layer.

For example, when the conductive wiring is laminated in four layers, the conductive wiring M0_1 is electrically connected to the upper conductive wiring M1_1 through the contact C1_1, and the conductive wiring M1_1 is connected to the contact C2_1. It is electrically connected to the upper conductive wiring (M2_1) through. In addition, the conductive wire M0_2 is electrically connected to the upper conductive wire M1_2 through the contact C1_2, and the conductive wire M1_2 is electrically connected to the upper conductive wire M2_2 through the contact C2_2. do. The conductive wires M2_1 and M2_2 are electrically connected to the conductive wires M3 of the uppermost layer through the contacts C3_1 and C3_2, respectively.

A method of forming a semiconductor device according to another embodiment of the present invention having such a structure may be performed as shown in FIGS. 8A to 8E, and the method of forming the semiconductor device is the same as the method of forming a semiconductor device according to an embodiment of the present invention. Detailed description will be omitted.

As in the embodiment of the present invention, the semiconductor device according to another embodiment of the present invention also has a structure in which the reverse diode D5 and the forward diode D6 are connected to the gate 73 of the PMOS transistor P2. Regardless of the positive / negative charges generated, the PMOS transistor P2 can be effectively protected from plasma damage.

Also, in the final conductive wiring process, the gate 73 of the PMOS transistor P2 and the P + impurity extension region 77 which is the pickup region of the forward diode D6 are electrically connected to each other through the top conductive wiring M4.

Therefore, since the anode and the cathode of the forward diode D6 are maintained at an equipotential and turned off when the PMOS transistor P2 is operated or characterized, the forward diode D6 is operated when the PMOS transistor P2 is operated or measured. Defects can be prevented.

Although the present invention only mentions NMOS and PMOS transistors affected by plasma as an embodiment thereof, it will be apparent to those skilled in the art that the present invention can be applied to all other elements of a semiconductor device where plasma damage may occur.

That is, the lower diode is electrically connected to the reverse diode and the forward diode to the electrode of the specific element during the conductive wiring process, and the upper end of the conductive diode is electrically connected to both ends of the forward diode, so that the device is separated from the plasma charge flowing through the electrode. It effectively protects and does not cause any problems during normal operation.

According to the present invention, diodes are electrically connected to an electrode of a device into which plasma charge is introduced, thereby effectively discharging the plasma charge charged to the electrode of the device during a plasma process.

In addition, the present invention has an effect that the reverse diode and the forward diode is electrically connected to the electrode of the device that the plasma charge is introduced, thereby effectively protecting the device from plasma damage irrespective of the electrode of the plasma.

In addition, the present invention is electrically connected to the electrode, the reverse diode, and the forward diode of the device in which the plasma charge flows in the bottom conductive wiring process, and electrically connected to both terminals of the forward diode in the top conductive wiring process, thereby causing plasma damage The device can be effectively protected from the device and at the same time, as the forward diode is turned off in normal operation, there is an effect of preventing the device degradation due to the forward diode.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (18)

An element having an electrode electrically connected to upper conductive lines; A first diode electrically connected in reverse with respect to the electrode; And A second diode electrically connected to the electrode in a forward direction and electrically connected to the electrode through two conductive wires of different layers of the conductive wires; And erasing plasma charges flowing into the device through the electrode during the formation of the conductive wires by the first and second diodes. The method of claim 1, And the electrode and one end of the first and second diodes are electrically connected in common to conductive wires formed at the lowest of the conductive wires formed on the electrode. delete The method of claim 1, And the cathode of the second diode is electrically connected to the electrode through an upper conductive wire of the two conductive wires of the different layers. The method of claim 1, And the anode of the first diode is connected to ground. The method of claim 5, wherein And the anode of the first diode is connected to the bulk of the device. The method of claim 1, And the device is a MOS transistor having a gate electrode. A substrate in which well regions for forming at least first and second diodes and transistors and a plurality of junction regions are formed in the well regions; A gate layer formed on the substrate between two well regions forming a channel region of the transistor; A lowermost conductive wiring layer commonly connecting the gate with at least two of the junction regions for electrically reverse and forward coupling with respect to the gate of the transistor; And And upper conductive wiring layers formed on the lower conductive wiring layer and electrically connected to the lowest conductive wiring layer. The second diode includes a first junction region of a different type from the well region of the junction region and a second junction region of the same type of the first diode, and the second junction region. Is electrically connected to the gate of the transistor through any one of the upper conductive wiring layers, And an erase path of the plasma charge flowing in the upper conductive wiring layers is formed by the first and second diodes. The method of claim 8, And the first and second diodes discharge plasma charge flowing through the upper conductive wiring layers to well regions formed in the substrate through the lowest conductive wiring layer. The method of claim 8, The first diode is a semiconductor device, characterized in that the junction region is formed in the well region corresponding to the bulk of the transistor. delete delete The method of claim 8, And an upper conductive wiring layer electrically connected to the second junction region is a conductive wiring layer formed on a top of the upper conductive wiring layers. Forming well regions for forming at least first and second diodes and transistors in a substrate and a plurality of junction regions in the well regions; Forming a gate layer on the substrate between two well regions of the well regions that form a channel region of the transistor; Forming a bottommost conductive wiring layer commonly connecting the gate with at least two of the junction regions for electrical reverse and forward coupling to a gate of the transistor; And Forming upper conductive wiring layers electrically connected to the lowest conductive wiring layer; The second diode includes a first junction region of a type different from a well region constituting the first diode, and a second junction region of the same type constituting the first diode, wherein the second junction region is the upper conductive line. Is electrically connected to the gate of the transistor through any one of the layers, And a plasma charge flowing in during the forming of the upper conductive wiring layers is discharged to well regions of the substrate via the first and second diodes. The method of claim 14, And the junction region is formed in a well region corresponding to the bulk of the transistor. delete delete The method of claim 14, And forming an upper conductive wiring layer electrically connected to the second junction region, wherein the upper conductive wiring layer is formed on a top of the upper conductive wiring layers.

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