KR100836534B1 - A low power sub-pixel interpolator architecture - Google Patents

Abstract

The subpixel interpolation blocks are horizontal and vertical interpolators that respectively receive subpixels of a plurality of submacroblocks and generate subpixels to vertically reuse integer pixel data. Buffers all or some of the integer pixels included in the overlapping regions of the interpolation regions of the first and second submacroblocks whose interpolation operations are not adjacent to each other by horizontal lines during the interpolation operation of the first submacroblock. And at least two line buffers for outputting the buffered integer pixels and an integer pixel selectively input from the line buffers and an external memory to the vertical interpolators in an interpolation operation of the second submacroblock. It provides multiplexers.

Description

LOW POWER SUB-PIXEL INTERPOLATOR ARCHITECTURE

1 is a conceptual diagram illustrating a memory reference for subpixel interpolation when a motion estimation and compensation operation is performed at a half sample position.

FIG. 2A is a block diagram of a subpixel interpolation block capable of horizontally reusing a memory value even among submacroblocks spaced apart from each other in an operation order in the prior art, and FIG. 2B is used for the subpixel interpolation block of FIG. 2A. A block diagram of a context switching buffer (CSB).

3 is a conceptual diagram illustrating vertical reuse of memory values in a subpixel interpolation block according to an embodiment of the present invention.

4 is a block diagram illustrating a subpixel interpolation block according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

I0, I1, I2: Interpolation area of sub macroblocks 0 to 2

I01: Area where interpolation areas of sub macroblocks 0 and 1 overlap

I02: Area where interpolation areas of sub macroblocks 0 and 2 overlap with each other

421 to 424: multiplexer

431 to 434: vertical interpolator

441 to 449: register chain

451 to 459: horizontal interpolator

461-464 line buffer

The present invention relates to a video codec, and more particularly, to a structure in which a video codec using motion compensation is implemented in hardware.

MPEG-4 and H.264 are the most popular video codecs in recent years. MPEG-4 was developed by the Moving Picture Experts Group (MPEG), a working group of the International Organization for Standardization (ISO), and H.264 is the Video Coding Experts Group (VCEG), a working group of the International Telecommunications Commission (ITU-T). Started at). While the MPEG-4 and H.264 standards are both involved in the compression and decompression of visual data and often use similar techniques, MPEG-4 can handle a wide range of visual data such as rectangular frames, still images, and video objects. Flexibility is emphasized, and H.264 emphasizes efficiency and reliability to provide exceptional compression and transmission efficiency for video frames.

Like other standards for video codecs such as MPEG-1, MPEG-2, H.261, and H.263, both standards use block-based motion estimation and compensation techniques, discrete cosine transform, quantization, and entropy coding. In this respect, it can be said that they share common features. Among these, block-based motion estimation and compensation are processes that require the most computation among processes of compressing and reconstructing given visual data.

In the above standards, motion estimation and compensation are performed based on a basic macroblock composed of M × N pixels and a macroblock composed of 4 × 4 (ie, 16) submacroblocks. In particular, MPEG-4 and H.264 process video frames in macroblock units. In the following, the terms macroblock or submacroblock, motion estimation and motion compensation are not divided by standard.

The motion estimation of the submacroblock is an operation of finding the 16x16 pixel area in the reference frame that is most similar to the current submacroblock. The reference frame is a previously encoded frame, and the temporal order displayed on the screen may be before or after the current frame. In the reference frame, an area of a predetermined area centered on the current submacroblock position is searched, and the 16x16 area having the smallest difference (error) with the current submacroblock is selected as the most matching area. The relative position of the closest region with respect to the position of the current submacroblock is called a motion vector. The error submacroblock subtracting the most matching region from the current submacroblock is coded together with the motion vector. Motion compensation is an operation for reconstructing the original current submacroblock using a coded error submacroblock, a motion vector, a closest match region, a reference frame, and the like.

In motion estimation and compensation, interpolation allows a video object to have a non-integer, non-integer position (this is called a subpixel position) because the video object may not always move in integers between frames. This is commonly used. Performing motion estimation and compensation at the interpolated sample position of the reference frame is called subpixel interpolation. In general, first-order motion estimation is performed at integer sample positions to find the best match. Secondary motion estimation is performed at a half sample position around the most matched region. If necessary, one more motion estimation may be performed at the quarter-sample position.

1 is a conceptual diagram illustrating a memory reference for subpixel interpolation when a motion estimation and compensation operation is performed at a half sample position.

Referring to FIG. 1, one macroblock of a reference frame includes sub macroblocks 0 to 15 each consisting of 4x4 pixels. In order to perform subpixel interpolation for sub macroblock 0, an interpolation region I0 having a predetermined area surrounding sub macroblock 0 is set, and integer pixel values in the interpolation region I0 are read from memory. Indent the interpolation operation and get half pixels. The corresponding interpolation area I1 is also set for the first sub macroblock. If adjacent submacroblocks have the same motion vector and the operation is subsequently performed, integer pixel values can be reused again for subpixel interpolation. For example, if the submacroblock 0 and the submacroblock 1 have the same motion vector and are sequentially calculated, the overlapping area I01 of the two interpolation areas I0 and I1 corresponding to the two submacroblocks is calculated. Since the integer pixels are the same, the values corresponding to the integer pixels in the area I01 can be reused as they are without being read back from the external memory.

Since adjacent submacroblocks have the same motion vector and operations occur frequently, the computation speed and power consumption can be improved to some extent through the technique of horizontal reuse of values stored in memory.

However, since the submacroblock 1 and the submacroblock 4 are adjacent to each other but are separated from each other in the calculation order, even though the interpolation operation is performed using the same integer pixels, the values of these integer pixels when the interpolation operation is performed on the submacroblock 4 is performed. Could not reuse them.

FIG. 2A is a block diagram of a subpixel interpolation block capable of horizontally reusing a memory value even among submacroblocks spaced in a calculation order in the prior art, and FIG. 2B is a CSB used in the subpixel interpolation block of FIG. 2A. Is a block diagram of.

Referring to FIG. 2A, a subpixel interpolation block performs horizontal interpolation and vertical interpolation on an interpolation region around a sub macroblock. The submacroblock is composed of 4x4 pixels for convenience of description. The subpixel interpolation block includes input buffers 21 for receiving nine integer pixels, vertical interpolators 22 for performing vertical interpolation operations, and integer pixel buffers 23 for sequentially shift storing integer pixels. Half pixel buffers 24 sequentially storing vertical interpolation results, and horizontal interpolators 25 performing horizontal interpolation operations.

The subpixel interpolation block vertically receives six integer pixels per half sample position and performs interpolation using the vertical interpolators 22, and the half pixels, which are the result of the interpolation operation, are stored in each half pixel buffer ( 24) sequentially. Horizontally, the inputs of the six integer pixel buffers 23 or the half pixel buffers 24 obtained above are input to the horizontal interpolators 25 for each half sample position, and an interpolation value corresponding to each half sample position is input. Can be calculated. The vertical interpolators 22 and the horizontal interpolators 25 are finite impulse response (FIR) filters.

Referring to FIG. 2B, the half pixel buffers and the integer pixel buffers of FIG. 2A are referred to as context switch buffers (CSBs), and the first and second multiplexers 231 and 232, the shift register 233, and And a switching register 234. The shift register 233 stores a value currently being interpolated, and the switching register 234 stores a value to be reused later. The first multiplexer 231 transfers a value selected from an input value and a stored value for reuse to the shift register 233. The second multiplexer 232 transfers the current interpolated value to the switching register 234 if it is a value to be reused. Using this CSB 23, the stored integer pixels can be reused between non-contiguous submacroblocks.

Using the subpixel interpolation block of this structure, sub macro blocks 1 and 4, sub macro blocks 3 and 6, sub macro blocks 9 and 12, and 11 in the macroblock of FIG. In four cases of and macroblocks 14 and 14, integer horizontal pixels are stored and reused later.

However, each CSB has two 8-bit registers and two 8-bit multiplexers, and one subpixel interpolation block has 54 CSBs. In this case, each CSB requires a considerable area when implemented in hardware and consumes little power. In addition, the CSB becomes very complicated because it must apply control signals to two multiplexers each. Since the subpixel interpolation block requires such a large number of CSBs, the subpixel interpolation block occupies a large area and consumes a lot of power despite the advantage of reducing the number of references to external memory.

An object of the present invention is to provide a subpixel interpolation block which can reduce the number of times of referencing an external memory during motion estimation and compensation operation.

Another object of the present invention is to provide a video codec including a subpixel interpolation block which can reduce the number of times of referring to an external memory during motion estimation and compensation operation.

Another object of the present invention is to provide a subpixel interpolation method capable of reducing the number of times of referencing an external memory in a motion estimation and compensation operation.

The subpixel interpolation block according to an embodiment of the present invention includes horizontal and vertical interpolators, at least two line buffers, and multiplexers. The vertical interpolator receives the integer pixels of the plurality of submacroblocks and interpolates to generate subpixels. The line buffers may include all or a portion of integer pixels included in an overlapping region among interpolation regions of the first and second submacroblocks that are spatially vertically adjacent and whose interpolation order is not adjacent in time. The interpolation operation of the submacroblock is buffered for each horizontal line, and the buffered integer pixels are output during the interpolation operation of the second submacroblock. The multiplexer provides the vertical interpolators with integer pixels selectively input between the line buffers and an external memory.

In example embodiments, the line buffers may buffer integer pixels of horizontal lines including a lower half of the first submacroblock in the overlapping area. In this case, the line buffers may include at least one reuse register chain each composed of a plurality of registers connected in series to shift the stored value. Further, the submacroblocks are blocks of 4x4 pixels, the at least one reuse register chains each comprising at least 13 registers, and the line buffers are any one of the ninth or thirteenth registers of the respective reuse register chains. It may be configured to selectively provide a stored value of a register to each of the multiplexers. Specifically, the line buffers provide the multiplexer with a stored value of the ninth register of each reuse register chain when the motion estimation and compensation is based on a block of 4x4 pixels and 4x8 pixels, and the motion estimation and compensation is 8x4. When based on a pixel, or block of 8x8 pixels, the multiplexer may be configured to provide a stored value of the thirteenth register of each reuse register chain.

According to an embodiment, the subpixel interpolation block may further include horizontal interpolators for horizontally interpolating the integer pixels and the half pixels.

An image codec according to another embodiment of the present invention includes a subpixel interpolation block that uses block-based motion estimation and compensation, compresses or reconstructs image data, and performs subpixel interpolation during motion estimation and compensation. In this case, the subpixel interpolation blocks are interpolators that receive integer pixels of a plurality of submacroblocks to generate interpixels, and interpolate spatially vertically and interpolate temporally among the plurality of submacroblocks. Buffer all or some of the integer pixels included in the overlapping regions of the interpolation regions of the first and second submacroblocks whose operation order is not adjacent to each other by horizontal lines during the interpolation operation of the first submacroblock, A line burr that outputs the buffered integer pixels during an interpolation operation of the second submacroblock And it includes a multiplexer for selectively providing the input to the integer pixel from said line buffer to the external memory in the interpolation groups.

In example embodiments, the line buffers may buffer integer pixels of horizontal lines including a lower half of the first submacroblock in the overlapping area. In this case, the line buffers may include at least one reuse register chain each composed of a plurality of registers connected in series to shift the stored value. Further, the submacroblocks are blocks of 4x4 pixels, the at least one reuse register chains each comprising at least 13 registers, and the line buffers are any one of the ninth or thirteenth registers of the respective reuse register chains. It may be configured to selectively provide a stored value of a register to each of the multiplexers. Specifically, the line buffers provide the multiplexer with a stored value of the ninth register of each reuse register chain when the motion estimation and compensation is based on a block of 4x4 pixels and 4x8 pixels, and the motion estimation and compensation is 8x4. When based on a pixel, or block of 8x8 pixels, the multiplexer may be configured to provide a stored value of the thirteenth register of each reuse register chain.

The interpolator may include vertical interpolators vertically interpolating the integer pixels and the half pixels, and horizontal interpolators horizontally interpolating the integer pixels and the half pixels, respectively.

In accordance with another aspect of the present invention, a subpixel interpolation method includes performing an interpolation operation using integer pixels of interpolation regions of a first submacroblock; It is included in the region overlapping with the interpolation region of the first sub-macroblock among the interpolation regions of the second sub-macroblocks spatially vertically adjacent to the first sub-macroblock, the temporal interpolation sequence is not adjacent in time. Buffering all or a part of integer pixels for each horizontal line in the interpolation operation of the first submacroblock; Reading integer pixels buffered in the overlapping area and buffered integer pixels except the temporarily stored integer pixels for interpolation of the second submacroblock; And performing an interpolation operation of the second submacroblock using the read integer pixels.

In some embodiments, the buffering of the integer pixels may include buffering integer pixels of horizontal lines including a lower half of the first sub-macroblock among the overlapping regions.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for the components.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

3 is a conceptual diagram illustrating vertical reuse of memory values in a subpixel interpolation block according to an embodiment of the present invention.

Referring to FIG. 3, one macroblock of a reference frame is composed of 16 4x4 pixel submacroblocks. The subpixel interpolation block performs subpixel interpolation on each submacroblock of the reference frame for motion estimation or compensation of one submacroblock of the current frame. The number of submacroblocks corresponds to the order of subpixel interpolation. For convenience of explanation, the subpixel interpolation block of FIG. 3 will be described only when calculating only half pixels.

In the video codec standard such as H.264, the unit block size of motion estimation and compensation can be changed to 4x4, 4x8, 8x4, 8x8, etc., but the subpixel interpolation operation itself is performed in units of 4x4 pixels, and the order thereof is shown in FIG. It is defined to be equal to the number of the indicated submacroblock.

The subpixel interpolation is performed in the order of sub macroblock 1, sub macro block 2, sub macro block 3, and the like.

Looking at the subpixel interpolation for the second macroblock, it can be seen that some of the interpolation region I0 of the submacroblock 0 overlaps with a part of the interpolation region I2 of the submacroblock # 2.

In this case, an interpolation area of a submacroblock is an area interpolated to obtain subpixels of the submacroblock, for example, 2 pixels up, 3 pixels down, and 2 pixels left around a 4 × 4 pixel sub macroblock. , Which extends by 3 pixels to the right. Then, the overlapping interpolation region of the two submacroblocks corresponds to the lower five lines (hereinafter, referred to as the overlapping interpolation region) of the interpolation region of the upper submacroblock.

If the integer pixels of the overlapping interpolation region I02 of the 0 and 2 submacroblocks are stored separately in the subpixel interpolation block during the subpixel interpolation operation of the 0 submacroblock, the subpixels for the 2nd submacroblock When pixel interpolation, integer pixels corresponding to the lower interpolation area of sub macroblock 0 can be directly reused without reading from external memory.

Likewise, the integer pixels of the lower interpolation region of the submacroblock 1 are stored in a line buffering space provided separately in the subpixel interpolation block, and reused when interpixel interpolation of the submacroblock 3 is performed.

In this way, if integer pixels corresponding to the lower interpolation area are stored for each subpixel interpolation of each submacroblock, subpixels 0 and 2, submacros 1 and 3, subblocks 4 and 6 Between the sub macroblocks 5 and 7, sub macro blocks 8 and 10, sub macro blocks 9 and 11, sub macro blocks 12 and 14, and sub macro blocks 13 and 15, respectively. Integer pixels corresponding to the interpolation region may be reused. Therefore, the number of times of reading data corresponding to the integer pixels to be reused from the external memory as a whole can be greatly reduced.

For example, when using an external memory of the 32-bit band, since 8 bits per pixel, without the reuse of pixel data, the number of times to access the external memory to read 9 pixels is three times. However, by reusing only two lines of pixel data as in an embodiment of the present invention, the number of accesses to the external memory is reduced by two times. When the number of external memory accesses is reduced once per subpixel interpolation of one submacroblock, the number of 16 external memory accesses per macroblock is reduced. If the CIF image format is 352x288 pixels and includes 352 (= 22x18) macroblocks, the total number of external memory accesses can be reduced to 5,632 times.

According to an embodiment, increasing the capacity of each of the line buffering spaces enables reuse of integer pixels even between two submacroblocks that are vertically adjacent but far apart in the order of operation. For example, first, for each subpixel interpolation operation of sub macroblocks 2, 3, 4, and 5, integer pixels corresponding to lower interpolation regions of each sub macroblock are included in each submacroblock in one line buffering space. Save it very much. In this way, when performing subpixel interpolation for subpixel 6, the integer interpolators used in interpixel interpolation of subpixel 4 can be provided to the vertical interpolators, and subpixel for submacroblock 7 When interpolating, integer pixels used to interpolate subpixel of subblock 5 may be provided to the vertical interpolators. Similarly, when performing subpixel interpolation on submacroblock 8, the integer interpolators used in subpixel interpolation of submacroblock 2 may be provided to the vertical interpolators, and subpixel interpolation on submacroblock 9 is performed. In this case, integer pixels used in interpixel interpolation of subpixel block 3 may be provided to the vertical interpolators.

Even though the block size is variable, the subpixel interpolation operation is performed in blocks of 4x4 pixels, so the line buffering space can store and output 9 or 13 integer pixels per line according to the block size for motion estimation and compensation. have. The subpixel interpolation block performs subpixel interpolation from nine integer pixels when performing motion estimation and compensation on blocks of 4x4 pixels and blocks of 8x4 pixels, but blocks of 4x8 pixels, blocks of 8x8 pixels, and blocks of 8x16 pixels When performing motion estimation and compensation on a block, a 16x8 pixel block, or a 16x16 pixel block, subpixel interpolation may be performed from 13 integer pixels.

For example, if the sub macroblocks 0 and 1 and the sub macro blocks 2 and 3 are motion compensation blocks of 4x8 pixels, respectively, an integer pixel corresponding to the lower interpolation area of the sub macroblocks 0 and 1 These include 13 integer pixels in a line, and these integer pixels can be reused in the interpixel interpolation of subblocks 2 and 3. It is more effective to selectively reuse 9 or 13 integer pixels in some cases than to always reuse only 9 integer pixels.

In the above example, all integer pixels of overlapping regions of the interpolation regions of the two submacroblocks are all stored. However, storing all the corresponding integer pixels requires space and complexity, so that the advantages obtained by reducing the number of memory references may be canceled out. Therefore, according to the exemplary embodiment, only integer pixels of the interpolation region I02 ′ including horizontal lines 3 and 4 of the submacroblock may be stored. In this case, the number of integer pixels to be reused is rather small, but the principle is as described above.

4 is a block diagram illustrating a subpixel interpolation block according to an embodiment of the present invention. Referring to FIG. 4, the subpixel interpolation block 40 includes first to ninth input buffers 411 to 419, first to fourth multiplexers 421 to 424, and first to fourth vertical interpolators. 431 to 434, first to ninth register chains 441 to 449, first to ninth horizontal interpolators 451 to 459, and first to fourth line buffers 461 to 464. do.

The subpixel interpolation block 40 illustrated in FIG. 4 basically performs subpixel interpolation on a submacroblock of 4x4 pixels. H.264 and the like have been designed such that the basic block unit of motion estimation and compensation can be varied, and the subpixel interpolation block is designed to perform subpixel interpolation even in units of 4x8 pixels or 8x4 pixels.

The subpixel interpolation block 40 exemplifies a case of storing only integer pixels of an interpolation region (eg, I02 ') including horizontal lines 3 and 4 of one sub macroblock.

The submacroblock has four integer pixels vertically, and four half pixels are obtained with vertical interpolation. In addition, the subpixel interpolation block 40 interpolates six integer pixels to obtain one half pixel. Therefore, a total of nine integer pixels must be input to the subpixel interpolation block at one time.

The subpixel interpolation block 40 receives the total of nine integer pixels. The first vertical interpolator 431 interpolates six integer pixels from the first to fourth multiplexers 421 to 424 and the fifth and sixth input buffers 415 and 416 to interpolate the first half pixel. Create The second vertical interpolator 432 interpolates six integer pixels from the second to fourth multiplexers 422 to 424 and the fifth to seventh input buffers 415 to 417 to interpolate the second half pixel. Create The third vertical interpolator 433 receives six integer pixels from the third and fourth multiplexers 423 and 424 and the fifth to eighth input buffers 415 to 418 to interpolate the third half pixel. Create The fourth vertical interpolator 434 receives six integer pixels from the fourth multiplexer 424 and the fifth to ninth input buffers 415 to 419 to interpolate to generate a fourth half pixel. In this way, a total of four half pixels, one for each of four integer pixels vertically of the submacroblock, can be interpolated.

For example, in the case of subpixel interpolation in sub macro block 3, the first half pixel of the first vertical line in sub macro block 3 is integer pixels 3 and 4 of the first vertical line in sub macro block 1, The integer pixels 1 through 4 of the first vertical line in the sub macroblock 3 are interpolated. The second half pixel is the integer pixel 4 of the first vertical line in submacro block 1, the integer pixels 1 to 4 of the first vertical line in submacro block 3, and the integer 1 of the first vertical line in submacro block 9 Created by interpolating pixels.

The first register chain 441 receives integer pixels from the third multiplexer 423 and stores them in order. The second register chain 442 receives half pixels from the first vertical interpolator 431 and sequentially stores the half pixels. The third register chain 443 receives integer pixels from the fourth multiplexer 424 and sequentially stores the integer pixels. The fourth register chain 444 receives half pixels from the second vertical interpolator 432 and sequentially stores them. The fifth register chain 445 receives integer pixels from the fifth input buffer 415 and stores them sequentially. The sixth register chain 446 receives half pixels from the third vertical interpolator 433 and sequentially stores them. The seventh register chain 447 receives integer pixels from the sixth input buffer 416 and stores them sequentially. The eighth register chain 448 receives half pixels from the fourth vertical interpolator 434 and sequentially stores them. The ninth register chain 449 receives integer pixels from the seventh input buffer 417 and sequentially stores them. To this end, the first to ninth register chains may each include six serially connected registers.

The first through ninth horizontal interpolators 451 through 459 interpolate inputs of six registers in the first through ninth register chains 441 through 449, respectively. The vertical interpolators 431 to 434 and the horizontal interpolators 451 to 459 are digital filters, and in particular, may be finite impulse response (FIR) filters.

In the ideal case where the motion vector exactly points to a certain submacroblock position, integer pixels corresponding to the bottom two lines of the submacroblock may be reused in the subpixel interpolation operation of the next lower submacroblock. However, otherwise, the motion vector often points to an arbitrary pixel in the submacroblock. In this case, the next integer pixels to be reused may not be integer pixels corresponding to two lines at the bottom of the submacroblock. In this case, a total of four line buffers, that is, the first to fourth line buffers 461 to 464, are respectively connected to the fifth to ninth input buffers 415 to 419, and two consecutive lines are included. Store integer pixels in buffers. For example, the integer pixels of the fifth and sixth input buffers 415 and 416 are stored in the first and second line buffers 461 and 462, respectively.

The line buffers 461 to 462 have at least two reuse register chains 4611 and 4612 and a multiplexer 4613 therein. The reuse register chains 4611 and 4612 may each include at least 13 serially connected registers with the switch. The switch passes the input integer pixel data when integer pixel data is to be stored in the reuse register chains 4611 and 4612. Thirteen serially connected registers in the reuse register chains 4611 and 4612 shift and store integer pixel data each time integer pixel data is input. The multiplexer 4613 is selected from among 13th registers or 9th registers of the selected reuse register chain among the at least two reuse register chains 4611 and 4612 according to whether the motion compensation block is 16x, 8x, or 4x. From the register, output integer pixel data to be reused. The output reuse reuse pixel data are transmitted among the first to fourth multiplexers 421 to 424, respectively.

The subpixel interpolation block 40 of FIG. 4 illustrates a structure in which only integer pixels corresponding to two lines are reused, not all integer pixels in the overlapping interpolation region, but as described above, the integer pixels in the overlapping interpolation region may be changed. Of course, you can also save and reuse everything.

With this configuration, the subpixel interpolation block 40 can vertically reuse a part of the interpolation area, thereby reducing the number of times of referring to the external memory.

In general, an image codec using a block-based motion estimation and compensation technique includes a motion estimator or a motion compensator that performs motion estimation or compensation, and the motion estimator or motion compensator typically performs subpixel interpolation that performs subpixel interpolation. Contains a block. Since the basic rules that the subpixel interpolation block must have are all defined in the standards of the image codec, a subpixel interpolation block such as the embodiments of the present invention can be easily applied in such an image codec. Therefore, a separate description of applying the above-described subpixel interpolation block to the codec is omitted.

The subpixel interpolation block according to an embodiment of the present invention may be implemented in software or hardware. When implemented in hardware, the subpixel interpolation block requires less registers or multiplexers, thus consumes less power or occupy less space than conventional horizontal reuse structures, and is less complicated to control the multiplexers. In addition, in the conventional horizontal reuse structure, the number of horizontal reuses is typically only four times in one macroblock, but in the subpixel interpolation block according to an embodiment of the present invention, the number of vertical reuses of integer pixels is one macroblock. The number of references to external memory can be reduced by about 8 times and up to 12 times. Reducing the number of references to memory reduces the time it takes to reference, as well as saving the power consumed by the memory, bus, and peripherals during the reference.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (14)

Vertical interpolators which receive integer pixels of the plurality of submacroblocks and interpolate to generate subpixels, respectively; All or part of the integer pixels included in the overlapping regions of the interpolation regions of the first and second submacroblocks that are spatially vertically adjacent and whose interpolation operation order is not adjacent in time are selected from the first submacroblock. At least two line buffers that buffer each horizontal line during the interpolation operation and output the buffered integer pixels during the interpolation operation of the second submacroblock; And And a multiplexer providing the vertical interpolators with integer pixels selectively input between the line buffers and an external memory. The subpixel interpolation block of claim 1, wherein the line buffers buffer integer pixels of horizontal lines including a lower half of the first submacroblock in the overlapping area. 3. The subpixel interpolation block of claim 2, wherein the line buffers comprise at least one reuse register chain each composed of a plurality of registers connected in series such that a stored value thereof is shifted. 4. The method of claim 3, wherein the submacroblocks are blocks of 4x4 pixels, the at least one reuse register chains each comprising at least 13 registers, and the line buffers are the ninth or thirteenth registers of the respective reuse register chains. A subpixel interpolation block configured to selectively provide a stored value of any one of the registers to the multiplexers, respectively. 5. The apparatus of claim 4, wherein the line buffers provide the multiplexer with a stored value of a ninth register of each reuse register chain when motion estimation and compensation is based on a block of 4x4 and 4x8 pixels. When the compensation is based on a block of 8x4 pixels, 8x8 pixels, 8x16 pixels, 16x8 pixels, or 16x16 pixels, subpixel interpolation characterized in that it provides the multiplexer with the stored value of the thirteenth register of each reuse register chain. block. The subpixel interpolation block of claim 1, further comprising horizontal interpolators for horizontally interpolating the integer pixels and the subpixels, respectively. An image codec including a subpixel interpolation block that uses block-based motion estimation and compensation and compresses or reconstructs image data, and performs subpixel interpolation in motion estimation and compensation, wherein the subpixel interpolation block includes: Interpolators that receive integer pixels of the plurality of submacroblocks and interpolate to generate subpixels, respectively; All or some of the integer pixels included in the overlapping regions of the interpolation regions of the first and second submacroblocks of the plurality of submacroblocks, which are spatially vertically adjacent and whose interpolation calculation order is not adjacent in time. Line buffers for buffering the horizontal lines during the interpolation operation of the first submacroblock and outputting the buffered integer pixels during the interpolation operation of the second submacroblock; And And multiplexers for providing the interpolators with integer pixels selectively input between the line buffers and an external memory. 8. The image codec of claim 7, wherein the line buffers buffer integer pixels of horizontal lines including a lower half of the first submacroblock among the overlapping regions. 9. The image codec of claim 8, wherein the line buffers comprise at least one reuse register chain each composed of a plurality of registers connected in series such that a stored value thereof is shifted. 10. The method of claim 9, wherein the submacroblocks are blocks of 4x4 pixels, the at least one reuse register chains each comprising at least 13 registers, and the line buffers are the ninth or thirteenth registers of the respective reuse register chains. And provide the stored value of any one of the registers selectively to the multiplexers, respectively. 11. The apparatus of claim 10, wherein the line buffers provide the multiplexer with a stored value of a ninth register of each reuse register chain when motion estimation and compensation is based on a block of 4x4 pixels, 4x8 pixels. An image codec configured to provide the multiplexer with a stored value of a thirteenth register of each reuse register chain when the compensation is based on a block of 8x4 pixels, or 8x8 pixels, 8x16 pixels, 16x8 pixels, or 16x16 pixels. . 8. The interpolator of claim 7, wherein the interpolator comprises vertical interpolators vertically interpolating the integer pixels and the subpixels, and horizontal interpolators horizontally interpolating the integer pixels and the subpixels, respectively. Video codec made. Performing an interpolation operation using integer pixels of interpolation regions of the first submacroblock; It is included in the region overlapping with the interpolation region of the first sub-macroblock among the interpolation regions of the second sub-macroblocks spatially vertically adjacent to the first sub-macroblock, the temporal interpolation sequence is not adjacent in time. Buffering all or a part of integer pixels for each horizontal line in the interpolation operation of the first submacroblock; For the interpolation operation of the second submacroblock, integer pixels included in the overlapping region are read and buffered, and integer pixels except the integer pixels included in the overlapping region are read from an external memory. step; And Performing an interpolation operation of the second submacroblock using the read integer pixels. 14. The subpixel interpolation of claim 13, wherein the buffering of the integer pixels comprises buffering integer pixels of horizontal lines including a lower half of the first submacroblock among the overlapping regions. Way.

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