KR100835626B1 - Timing adjustment for data transmitting/receiving circuit, lsi and data transmitting/receiving system - Google Patents

Abstract

An object of the present invention is to provide a timing adjustment circuit for realizing data transmission and reception without being affected by process variation or power supply voltage / temperature variation even at a high data transfer rate.

Compare the phase of the data outputted by the data transmitter with the phase of the clock that defines the timing at which the data receiver receives the data, and adjust the phase of the clock that defines the timing at which the data transmitter transmits the data according to the comparison result. .

Description

Timing ADJUSTMENT FOR DATA TRANSMITTING / RECEIVING CIRCUIT, LSI AND DATA TRANSMITTING / RECEIVING SYSTEM}

1 is a view showing the basic configuration of the present invention.

FIG. 2 is a diagram showing an application example of the basic configuration of the present invention shown in FIG. 1; FIG.

3 is a diagram showing a configuration of a first embodiment of the present invention.

4 is a timing chart of data change detection in the first embodiment.

5 is a timing chart of phase comparison of the first embodiment;

6 is a diagram showing a configuration of a second embodiment of the present invention.

7 shows a timing chart of phase comparison in a second embodiment;

8 shows a third embodiment of the present invention;

9 shows a fourth embodiment of the present invention.

10 is a diagram showing a configuration example of a conventional data transmission circuit.

FIG. 11 is a view for explaining data transmission and reception between multiplexers of the data transmission circuit shown in FIG. 10; FIG.

12 is a timing chart in the case where data transmission and reception between the multiplexers shown in FIG. 11 is performed normally.

FIG. 13 is a timing chart in a case where data transmission and reception between the multiplexers shown in FIG. 11 is not normally performed. FIG.

<Description of the symbols for the main parts of the drawings>

10: data transmission unit

12: front end latch

20: data receiving unit

22: rear latch

30, 32: phase comparison unit

40, 42: phase adjusting unit

52: data change detection unit

100: PLL

110: data buffer

120: 16: 8 multiplexer

130: 8: 4 multiplexer

140: 4: 2 multiplexer

160: dummy data output unit

170: 2: 1 Multiplexer

180: output buffer

The present invention provides a timing adjustment circuit of a data transmission / reception circuit for performing data transmission and reception between a data transmission unit and a data reception unit, for example, a plurality of elements or circuit blocks in an LSI, data transmission and reception between LSIs, and data transmission and reception between boards or casing bodies. The present invention relates to an LSI having a timing adjustment circuit and a data transmission / reception system. In particular, the input parallel data for converting input parallel data into serial data, for example, input bit data having a data bit width of 16 bits and a speed of 2.5 Gbps is converted from 8 bit 5 Gbps to 4 bit 10. In a data transmission circuit that converts the internally generated clock step by step using a divided clock such as Gbps → 2 bit 20 Gbps → 1 bit 40 Gbps, data transmission and reception between the multiplexers performing the stepwise conversion of the data bit width is assured. Timing adjustment circuit for adjusting the phase relationship between the data and the clock so that will be.

Recently, in the computer and communication field, the amount of information to be processed is increasing. In order to cope with the increasing amount of information, the data transmission / reception rate between LSIs is also increasing. Although in the research stage, a CMOS 10 Gbps transceiver was introduced in 2002. Since then, the research of CMOS 40 Gbps transceivers has attracted attention. In particular, in the area where these high data transfer rates are required, the most advanced technology is applied. For example, CMOS 40 Gbps transceivers are under study assuming technology of 0.1 um or less. However, in a data transmission / reception system requiring a high data transmission rate, it is necessary to further increase the LSI internal clock frequency. In contrast to the performance improvement of transistors with miniaturization of semiconductor processes, the process variation is very large. Conventionally, the study of layout has ensured that the blocks that perform data transmission and reception are as close as possible to secure timing margins for data reception. However, these techniques are also reaching their limits due to the improvement of data transfer rate and the influence of process variation.

10 shows an example of the configuration of a data transmission circuit as an example of the high speed transceiver. The data transmission circuit of FIG. 10 stores the 2.5-Gbps parallel data at 16 bits wide in the data buffer 110 of the first in first out (FIFO) and then divides the internally generated clock generated by the PLL 100. The input parallel data is converted into serial data step by step using a clock in which the periods 210, 220, and 230 are sequentially divided. That is, the input 16 bit 2.5 Gbps data is converted into 8 bit and 5 Gbps data by the 16: 8 multiplexer 120, and then converted into 4 bit 10 Gbps data by the 8: 4 multiplexer 130. The data is converted into 2 bit 20 Gbps data by the 4: 2 multiplexer 140 and serial data of 1 bit, that is, 40 Gbps by the 2: 1 multiplexer 170. Then, 40 Gbps of data is output to the outside through the last stage buffer 180.

Next, an example of the 4: 2 multiplexer 140 and the 2: 1 multiplexer 170 will be described with reference to FIG. 11 for data conversion by the multiplexer of the data transmission circuit shown in FIG. 10 and data transmission and reception between the multiplexers. .

The 4-bit inputs DT_IN [0], DT_IN [1], DT_IN [2], and DT_IN [3] from the 8: 4 multiplexer 130 at the front end are supplied to the second 2: 1 multiplexer 170 at 20 GHz. The clock CLK_A is received by the first stage latch circuits 141, 143, 151, and 153 of the 4: 2 multiplexer 140 in synchronization with the 10 GHz clock CLK_B divided into 1/2 by the divider 210. DT_IN [0] is supplied to the selector 146 through the latch circuit 142, DT_IN [2] is supplied to the selector 146 through the latch circuits 144 and 145, and DT_IN [1] is supplied through the latch circuit 152. ] Is supplied to the selector 156 through the latch circuits 154 and 155.

The selectors 146 and 156 select DT_IN [0] and DT_IN [1] respectively by the vertical rise of the clock CLK_B, and select DL_IN [2] and DL_IN [3] respectively by the vertical rise of the clock CLK_B. The output DT of the selector 146 obtains serial data of DT_IN [0] and DT_IN [2], which is twice the speed of 10 GHz. The same output can be obtained with respect to the output DTX of the selector 156.

DT and DTX, which are outputs of the 4: 2 multiplexer 140, are received by the first stage latch circuits 171 and 173 of the 2: 1 multiplexer 170 in synchronization with the clock CLK_A of 20 GHz, respectively, and the latch circuit 172 and the latches. The selector 176 is supplied to the selector 176 through the circuits 174 and 175, and is selected by the selector 176 in synchronization with the vertical rise and the vertical fall of the clock CLK_A, respectively, and output as the output circuit DT_OUT of the transmission circuit.

12 is a timing chart when data transmission and reception between the 4: 2 multiplexer 140 and the 2: 1 multiplexer 170 shown in FIG. 11 is performed normally.

The clock CLK_A is a clock that defines the timing of receiving data at a later 2: 1 multiplexer 170. The clock CLK_B is a clock that defines the timing of outputting data from the 4: 2 multiplexer 140, which is the front end, and is a divided clock synchronized with the vertical rising edge of the clock CLK_A. Currently, data is output from the 4: 2 multiplexer 140 by the vertical rise of the clock CLK_B in synchronization with the vertical rise of the clock CLK_A. The 2: 1 multiplexer 170 receives this data as the vertical rise of the next cycle clock CLK_A. Designs must realize this timing chart under conditions that take into account process variations, supply voltage and temperature variations. In the prior art, the physical distance between the multiplexers is shortened, and the circuit configuration of the multiplexer or divider is studied to realize the timing chart shown in FIG.

However, in the example of the high speed transmission circuit which finally outputs data of 40 Gbps speed shown in FIG. 10, it is difficult to reliably transmit and receive data between the multiplexers. 13 is a timing chart when data transmission and reception between the multiplexers is not normally performed. As shown in FIG. 13, when there is a displacement of the received data due to the vertical rising timing of the clock CLK_A, the first stage latch circuits 171 and 173 of the 2: 1 multiplexer 170 cannot accurately latch data, and 2: 1. Multiplexer 170 cannot correctly receive data.

Conventional techniques related to data transmission and reception, such as between LSIs, are described in, for example, Patent Documents 1 to 3 and Non-Patent Document 1 below. Patent Documents 1 and 2 apply a circuit technique commonly referred to as a DLL. The phase relationship between the output data and the output clock is adjusted in the data transmission circuit so as to reliably perform data reception in the data reception circuit. However, when the transmission distance is extended or the transmission speed is higher, it is difficult to reliably perform data reception in the data receiving circuit due to the influence of process variations and power supply voltage and temperature variations.

On the other hand, the data transmission / reception techniques described in Patent Document 3 and Non-Patent Document 1 adjust the phase of a clock that defines the data reception timing of the data reception circuit with respect to the output data from the data transmission circuit in the data reception circuit. Therefore, in consideration of data reception, data reception can be reliably performed in the data receiving circuit. However, when the clock frequency becomes high, processing in the data receiving circuit after data reception and the accuracy of the multiplexer output of the transmitting circuit shown in FIG. Considering this, it is undesirable to adjust the clock on the receiving side.

[Patent Document 1] Japanese Patent Application Laid-Open No. 10-112182

[Patent Document 2] Japanese Patent Application Laid-Open No. 2004-145999

[Patent Document 3] Japanese Patent Application Laid-Open No. 10-228449

[Non-Patent Document 1] Tamura Hirotaka, Kotou Kotarou "High Speed Signal Transmission Technology: Synfinity II" FUJITSU Vol. 50 No. 4 (07, 1999) pp. 235-241

The problem to be solved by the present invention includes a timing adjusting circuit for realizing data transmission and reception without being affected by process variation or power supply voltage / temperature variation even at a high data transfer rate, and such a timing adjusting circuit. To provide a data transmission and reception system with the LSI.

The timing adjustment circuit provided by this invention compares the phase of the data which a data transmitter outputs, the phase of a data, and the phase of the clock which prescribes the timing of receiving data, and the said data transmitter transmits data according to the comparison result. The phase of the clock that prescribes the timing is adjusted.

The LSI of the present invention includes a data change detection unit that detects a change in data outputted by a data transmission side block for each of the blocks to be transmitted and the blocks to be the transmission side, and the data are sequentially transmitted and received among a plurality of blocks. A phase comparison unit for performing a phase comparison between a clock defining a timing at which the data receiving side block receives data and data output from the data transmitting side block, and the data change detection unit outputting the data change side block. And a timing adjusting circuit having a phase adjusting section for changing a phase of a clock that defines a timing at which the data transmitting side block transmits data in accordance with a phase comparison result of the phase comparing section when detecting a change in data.

In addition, the data transmission / reception system between the LSIs of the present invention includes a data change detection unit for detecting a change in data output by the first LSI, a clock defining a timing at which the second LSI receives data, and the first LSI outputting the data. The first LSI transmits data according to a phase comparison result of the phase comparison unit when the phase comparison unit which performs a phase comparison with the data to be compared and the data change detection unit detects a change in the data output by the first LSI. And a timing adjusting circuit having a phase adjusting section for changing a phase of a clock that defines a timing to be specified.

The basic structure of this invention is shown in FIG. In the present invention, the phase comparison section 30 compares the phase of the data transmitted from the data transmitter 10 to the data receiver 20 with the phase of the clock on the receiving side that defines the timing of data reception in the data receiver 20, and the phase is compared. According to the comparison result in the comparison section 30, the phase adjuster 40 adjusts the phase of the clock on the transmission side, which defines the timing of data transmission in the data transmitter 10, and supplies it to the data transmitter 10. FIG.

The data transmitter 10 and the data receiver 20 are circuits for transmitting and receiving data between a plurality of elements or circuit blocks in the LSI, such as the multiplexer shown in FIG. 10, or circuits for transmitting and receiving data between the LSIs, between boards, or It can be implemented as a data transmission / reception circuit which performs data transmission and reception between casing bodies.

FIG. 2 is an application example of the basic configuration of the present invention shown in FIG. 1, wherein input data input to the front end latch unit 12 corresponding to the data transmitter 10 of FIG. 1 is input to the data receiver 20 of FIG. 1. The system is output as output data through the corresponding rear end latch section 22, and the clock defining the data reception timing of the rear end latch section 22 is phase adjusted to adjust the data or output timing of the front end latch section 12. It is supplied as a prescribed clock. Then, a data change detector 52 for detecting the timing at which the value of the data output from the front end latch unit 12 has changed from "0" to "1" or "1" to "0" is provided. When detected, the enable signal is sent to the phase comparator 32.

When the phase comparator 32 receives the enable signal, the phase comparator 32 performs a phase comparison between the output data of the front latch unit 12 and a clock defining the timing of data reception by the rear latch unit 22, and according to the comparison result, the phase adjuster Reference numeral 42 adjusts the phase of the clock that defines the data and output timing of the front end latch portion l2.

Instead of providing the data change detection unit 52, a replica that always outputs data having a change in data in the same configuration as the front end is provided on the front end latch unit 12 side, and the output is supplied to the phase comparator. You may give it.

As apparent from the contrast with FIG. 1, the phase comparator 32 and the data change detector 52 or the data change detector 52 of FIG. 2 are provided on the front end latch 12 side instead of the one provided. The phase comparator which performs phase comparison between the output of the replica and the clock defining the data reception timing of the rear latch 22 is corresponding to the phase comparator 30 of FIG.

The present invention can realize a data transmission / reception system which is not influenced by process variation, power supply voltage and temperature variation regardless of the data transfer rate. When the configuration of FIG. 2 is applied to the transmission circuit described in FIG. 10, for example, the 4: 2 multiplexer 140 corresponds to the front latch portion 12, and the 2: 1 multiplexer 170 is applied to the rear latch portion 22. Corresponding. The present invention compares the phase of the data output by the data transmission block corresponding to the front end with the phase of the clock in the data receiving block corresponding to the rear end in the data transmission / reception system performing data transmission and reception. The phase of the clock relative to the front end is changed so that the output data can be reliably received.

Hereinafter, as a timing adjustment circuit for data transmission and reception between the 4: 2 multiplexer 140 and the 2: 1 multiplexer 170 shown in FIG. 11, a data change detection unit 52 is provided. A replica that always outputs data with a change in data will be described in detail as a second embodiment of the present invention.

First, the first embodiment of the present invention will be described with reference to FIGS. 3, 4 and 5.

Fig. 3 shows the construction of the first embodiment of the present invention in detail. The same code | symbol as the code | symbol provided in FIG. 11 is the same as that demonstrated in FIG. In addition, the data change detection part 52 and the phase comparison part 32 show the specific structural example of the data change detection part 52 and the phase comparison part 32 of the application example shown in FIG. Phase interpolator PI (421) and PI control unit 422 having a function of changing the phase of the clock with respect to 140 correspond to the phase adjusting unit 42 of FIG.

The operation outline of the structural example shown in FIG. 3 will be described below.

The 20 GHz clock CLK_A supplied from the PLI (not shown) is distributed to the divider 210, the 2: 1 multiplexer 170, and the phase shifter 320.

The divider 210 divides the clock CLK_A and supplies a clock having a frequency of 10 GHz and a phase difference of 0, 90, 180, and 270 ° to the phase interpolator PI 421. The phase interpolator PI 421 supplies the 4: 2 multiplexer 140 with the clock CLK_B of 10 GHz whose phase was adjusted by the control of the PI control unit 422.

The data change detection unit 52 outputs the data change detection signal PI_EN to the PI control unit 422, and the PI control unit 422 sets the phase of the clock CLK_B for the 4: 2 multiplexer only during the period in which the data change detection signal PI_EN is High. The phase interpolator PI 421 having a function of changing is made valid. In addition, although the phase interpolator PI 421 was employ | adopted as a means of changing the phase of a clock in this embodiment, it does not need to be limited to this. For example, a clock buffer may be connected in series instead of the phase interpolator PI 421 and the output terminal may be adjusted to change the clock phase. This also applies to the following examples.

The phase shifter 320 supplies the clock CLK_A_DMY obtained by shifting the phase of the clock CLK_A by a fixed amount to the latch circuit 321 of the phase comparator 32.

Phase comparison in this embodiment is performed every time a change in data is detected. This is because the change in data reflects the phase of the clock in the 4: 2 multiplexer 140. The detection of the change in the data is performed by the XOR logic circuit 524 of the data change detection unit 52 with respect to the continuous data output by the 4: 2 multiplexer l40. The output XOR logic of the latch circuit 522 and the latch circuit 523 is determined. Is computed.

4 shows a timing chart relating to the detection of this change in data.

The data change detection unit 52 extracts the output DT of the 4: 2 multiplexer 140 by 2 bits in synchronization with the clock CLK_B, and detects the presence or absence of data change.

As shown in the figure, the latch circuit 521 latches the output data DT "1" by the vertical drop of the clock CLK_B, and the output SFT0 becomes "1". The latch circuit 523 latches the 2nd bit DT "0" by the vertical rise of the next clock CLK_B, and the SFT0 which is the 1st bit data is latched by the latch circuit 522, and the latch circuit 522 The output SFT1 and the output SFT2 of the latch circuit 523 are computed by the XOR logic circuit 524, output as a PI_EN_TMP signal, and are delayed by one clock in the latch circuit 525 and input to the PI control unit 422 as a PI_EN signal. . Hereinafter, the same processing is performed also about the 3rd bit and the 4th bit after the output data DT, and a PI_EN signal is generated.

Next, the operation of the phase comparison unit 32 will be described.

The object of phase comparison is the clock CLK_A_DMY which phase shifted the clock data CL of the 4: 2 multiplexer 140 and the clock CLK_A for the 2: 2 multiplexer 170 to the phase shifter 320. The phase of the clock CLK_B which outputs the output data DT is adjusted so that the change timing of the output data DT coincides with the change timing of the clock CLK_A_DMY. Here, when the clock CLK_A is applied as the phase comparison object instead of the clock CLK_A_DMY, the vertical rising edge of the clock CLK_A is positioned at the change timing of the output data DT. In this state, the 2: 1 multiplexer l70 cannot reliably receive the output data of the 4: 2 multiplexer 140. For this reason, in the phase comparison, the clock CLK_A_DMY in which the clock CLK_A is phase shifted by a predetermined amount (adding a phase offset) must be used. In addition, the latch circuit 321 for receiving the output data DT as the vertical rising edge of the clock CLK_A_DMY should have the same physical configuration as the latch circuits 171 and 173 at the first stage of the 2: 1 multiplexer 170.

The phase comparison is a vertical rising edge of the clock CLK_A_DMY with respect to the continuous data output from the 4: 2 multiplexer 140, and the clock CLK_A_DMY for the output data DT depending on which data is received before or after time. Determine the phase delay, or phase progression of. The timing chart of this phase comparison is shown in FIG.

As shown in the figure, the clock CLK_B latches the second half of the output data DT by two bits shown in FIG. 4 in the latch circuit 323, and the second-bit output data DT "0" is vertically raised by the clock CLK_B. The latch circuit 323 is latched, and the value of the output DT_B0 is " 0 ". On the other hand, the value of the output data DT latched to the latch circuit 321 by the vertical rise of the clock CLK_A_DMY is also " 0 ", which is the second bit output data DT. The output DT_A of the latch circuit 321 is latched to the latch circuit 322 by the vertical rise of the clock CLK_B, and the output DT_B1 is outputted by performing an XOR logic operation on the output DT_BO of the latch circuit 323 and the XOR logic circuit 324. PI_SFT_TMP is generated and delayed by one clock in the latch circuit 325 and input to the PI control unit 422 as the phase comparison result signal PI_SFT. In this case, the value of the phase comparison signal PI_SFT is "0", indicating that the data latched by the clock CLK_A_DMY is data of the latter half. Although the same processing is continued, the output data DT of the third bit and the fourth bit is output data DT latched to the latch circuit 321 at the vertical rise of the clock CLK_A_DMY as shown in the drawing, and the third bit data is the third bit data. That is, it is data of the first half of the output data DT by two bits, and the value of the phase comparison signal PI_SFT is "1".

As described above, in the timing chart, when the clock CLK_A_DMY receives the preceding data in time, the phase comparison signal PI_SFT = 1 is output as the phase comparison result. In this case, the PI control unit 422 is instructed to advance the phase of the clock CLK_B. On the contrary, when the clock CLK_A_DMY receives data later in time, the phase comparison signal PI_SFT = 0 is output. In this case, the PI control unit 422 is instructed to delay the phase of the clock CLK_B.

In the PI controller 422, even if the value of the phase comparison signal PI_SFT is "0", if there is no data change in the continuous data described in FIG. 4, the output data DT latched to the latch circuit 321 by the vertical rise of the clock CLK_A_DMY is Since the first half or the second half cannot be identified, the phase comparison result signal is valid only with respect to the continuous data in which the data change detection unit 52 detects the data change, for example, by integrating or controlling the effective phase comparison result signal. A signal is supplied to the phase interpolator PI 421 to adjust the phase of the clock CLK_B.

By repeating the above series of operations, the phase of the output data DT and the clock CLK_A_DMY coincide, and the 2: 1 multiplexer 170 can reliably receive the 4: 2 multiplexer 140 output data. According to the present embodiment, it is possible to realize a data transmission / reception system which is not influenced by process variation or power supply voltage / temperature variation regardless of the data transfer rate.

Next, a second embodiment of the present invention will be described with reference to Figs.

As described above, the present embodiment is provided with a duplicate which always outputs data with a change of data, and Fig. 6 shows the configuration of this embodiment in detail, and Fig. 7 shows a timing chart of phase comparison in this embodiment. will be.

In the components shown in FIG. 6, the same reference numerals as those shown in FIG. 3 are assigned to the input data of the phase comparison unit 32 and the clock of the latch circuit 321 to be different, but functionally described in FIG. 3. Same as As shown in FIG. 6, in the present embodiment, the data change detection unit 52 described in FIG. 3 does not exist, and instead, the physical change is the same as that of the last stage selectors l46 and 156 of the 4: 2 multiplexer 140. The dummy data output unit 160 is a block for generating 1010 repetitive data using the selector 166 having the configuration. This 1010 repetitive data extends in parallel with the 4: 2 multiplexer 140 output data, although not shown, the dummy data output unit 160 is the 4: 2 multiplexer 140 similarly to the selectors 146 and 156. Is installed on.

Making the physical configuration of the selector 166 the same as the final stage selectors 146 and 156 of the 4: 2 multiplexer 140 is the final stage selectors 146 and 156 which are the original output data of the 4: 2 multiplexer 140. This is to accurately simulate the timing of the change of the output data.

Therefore, in general, a circuit having the same physical configuration as the circuit of the final stage of the data transmission section is used as the dummy data output section, not just the selector.

In the case of 1010 repetitive data, since there is always a change of data, it is not necessary to detect the change of data. Phase comparison is made between this 1010 repetitive data DT_DMY and the clock CLK_A for the 2: 1 multiplexer 170. In the first embodiment shown in Fig. 3, the clock CLK_A_DMY is used in which the phase of the clock CLK_A is fixed-phase shifted, but in this embodiment, the phase shifter 167 shifts the phase of the clock CLK_B by the phase shifter 167. One clock CLK_B_DMY is used. The reason for using the phase shifter 167 is the same as the reason for using the phase shifter 320 and can be replaced with each other.

Hereinafter, with reference to FIG. 7, the operation of phase comparison in this embodiment will be described.

As shown, the data "0" of the 1010 repetitive data DT_DMY is latched to the latch circuit 323 by the vertical rising of the clock CLK_B_DMY, and the 1010 repetitive data DT_DMY is latched by the vertical rising edge of one clock CLK_A. The output DT_A is latched to the latch circuit 322 by the mathematical rise of the clock CLK_B_DMY. The output DT_B1 of the latch circuit 322 and the output DT_B0 of the latch circuit 323 are compared in the XOR logic circuit 324 to generate a signal PI_SFT_TMP indicating a coincidence mismatch, and is delayed by one clock in the latch circuit 325. The phase comparison result signal is input to the PI control unit 423 as PI_SFT. Since the data displacement always occurs in the 1010 repetitive data DT_DMY, the PI control unit 423 has a configuration such that the PI_EN_TMP signal shown in FIG. 3 is always input. By the control signal based on this phase comparison result, the phase interpolator PI 421 adjusts the phase of the clock CLK_B with respect to the 4: 2 multiplexer 140.

According to the present embodiment, since the data change detection block can be omitted, a data transceiver system can be realized with a smaller circuit scale that is not affected by process variations or power supply voltage / temperature variations regardless of the data transfer rate.

8 and 9 respectively show a configuration of a timing adjustment circuit for transmitting and receiving data between the 4: 2 multiplexer 140 and the 2: 1 multiplexer 170 of the first and second embodiments. The third and fourth embodiments are applied between the multiplexers of the data transmission circuit. In addition, it abbreviate | omits about the structure of phase comparison here.

The difference between the third embodiment shown in FIG. 8 and the fourth embodiment shown in FIG. 9 is the arrangement of the phase interpolators PI 421, 431, and 441.

In the third embodiment of Fig. 8, the multiplexers are arranged so that the phase of their clocks can be adjusted individually. Therefore, the influence of the phase change of the clock does not propagate to the shear multiplexer.

For example, in order to ensure data transmission and reception between the 4: 2 multiplexer 140 and the 2: 1 multiplexer 170, the phase interpolator PI 421 of the 10 GHz clock for the 4: 2 multiplexer 140 is guaranteed. When the output phase is changed, the phase relationship between the data and the clock between the 8: 4 multiplexer 130 and the 4: 2 multiplexer 140 at the front end is changed. Therefore, it may be necessary to sequentially adjust the output phases of the phase interpolator PI 431 and the phase interpolator PI 441.

On the other hand, in the fourth embodiment of Fig. 9, the phase interpolator PI is arranged so that the output of the phase interpolator PI is supplied to the frequency divider of the front end. If the output phase of the phase interpolator PI 421 of the 10 GHz clock is varied to ensure data transmission and reception between the 4: 2 multiplexer 140 and the 2: 1 multiplexer 170, the 8: 4 on the front end of the The phase relationship of the clock and data between the multiplexer 130 and the 4: 2 multiplexer 140 is maintained. This is because the clock for the 8: 4 multiplexer l30 in front of it is generated based on the clock for the 4: 2 multiplexer 140.

By the third and fourth embodiments, the present invention can be applied to the entire data transmission circuit. In particular, the configuration of the fourth embodiment shown in Fig. 9 can provide a data transmission / reception system with good usability since the phase adjustment result does not propagate between other circuit blocks.

The present invention can also be applied to data transmission and reception between LSIs. As the miniaturization of a semiconductor process progresses, the influence of the process variation becomes remarkable. The circuit technology corresponding to the process variation such as the timing adjustment circuit of the present invention is considered to be an important element technology for realizing the LSI thereafter.

(Book 1)

A timing adjustment circuit for adjusting the timing of data transmission and reception between a data transmission unit for transmitting data and a data receiving unit for receiving data, the timing adjustment circuit defining a phase of data output by the data transmission unit and a timing at which the data receiving unit receives data. And comparing the phases of the clocks and adjusting the phases of the clocks defining the timings at which the data transmission unit transmits data in accordance with the comparison result.

(Supplementary Note 2)

A data change detection section for detecting a change in data output from the data transmission section, a phase comparison section for performing a phase comparison between a clock defining a timing at which the data reception section receives data and data output from the data transmission section, and And a phase adjuster for changing a phase of a clock that defines a timing at which the data transmitter transmits data according to a phase comparison result of the phase comparator when the data change detector detects a change in data output by the data transmitter. The timing adjustment circuit of Appendix 1 characterized by the above-mentioned.

(Supplementary Note 3)

The phase comparator is a circuit for receiving data output by the data transmitting circuit based on a clock that defines a timing at which the data receiving unit receives data. The phase comparing unit is configured to receive a latch circuit having the same configuration as that of the first circuit of the data receiving unit block. The timing adjustment circuit as described in Appendix 2 characterized by the above-mentioned.

(Appendix 4)

And the latch circuit receives data output from the data transmitter in synchronization with a clock in which the data receiver determines a timing at which data is received by a phase shifted by a predetermined amount.

(Supplementary Note 5)

A dummy data output circuit for outputting 1010 repetitive data which always changes in data based on a clock defining a timing at which the data transmitter transmits data, a clock defining a timing at which the data receiver receives data, and A phase comparator for performing phase comparison with data output from the dummy data output circuit, and a phase adjuster for changing a phase of a clock that defines a timing at which the data transmitter transmits data according to a phase comparison result of the phase comparator. The timing adjustment circuit as described in Appendix 1 characterized by the above-mentioned.

(Supplementary Note 6)

The dummy data output circuit has the same configuration as that of the last stage of the data transmitter. The timing adjustment circuit according to Appendix 5.

(Appendix 7)

The dummy data output circuit outputs 1010 repetitive data of which data is always changed in synchronization with a clock having a predetermined amount of phase shifted a clock that defines a timing at which the data transmission unit transmits data. One timing adjustment circuit.

(Appendix 8)

A data change detection section for detecting a change in data output from the data transmission side block for each block serving as a transmitting side and a receiving side block in an LSI in which data is sequentially transmitted and received between a plurality of blocks; and the data receiving side A phase comparison section for performing a phase comparison between a clock defining a timing at which the block receives data and data output from the data transmission side block, and the data change detection section detecting a change in data output from the data transmission side block And a timing adjusting circuit including a phase adjusting section for changing a phase of a clock that defines a timing at which the data transmitting side block transmits data in accordance with a phase comparison result of the phase comparing section.

(Appendix 9)

The phase adjusting unit is arranged such that a clock, which is a target of phase adjustment, between a data transmitting side block and a data receiving side block affects the timing of data transmission and reception between another data transmitting side block and the data receiving side block. LSI described in Appendix 8.

(Book 10)

The phase adjuster is arranged so that a clock that is subject to phase adjustment between a data transmitting side block and a data receiving side block does not affect the data transmission / reception timing between the other data transmitting side block and the data receiving side block. LSI according to Annex 8 characterized by the above-mentioned.

(Appendix 11)

The plurality of blocks are a plurality of multiplexers for converting parallel data into sequential serial data, and constitute a data transmission circuit for outputting data from the LSI to the outside.

(Appendix 12)

The LSI according to Appendix 11, wherein each multiplexer outputs data at half the bit width of the input data and at twice the speed.

(Appendix 13)

The clock which defines the timing at which the last stage multiplexer receives data among the multiplexers is generated by the clock generation means of the LSI, and a 1/2 divider is generated for each of the multiplexer serving as the transmitting side and the multiplexer serving as the receiving side. And a multiplexer other than the final stage supplies a clock that divides the clock defining the data reception timing of the multiplexer of the rear stage into 1/2 frequency dividers through the phase adjusting unit, and supplies the clock by the supplied clock. The LSI according to Appendix 12, which specifies a transmission timing of data to be transmitted to the multiplexer after the multiplexer.

(Book 14)

The clock generated by the clock generation means of the LSI is input to the 1/2 divider corresponding to the multiplexer of the last stage and the multiplexer of the preceding stage, and the half divider of the rear stage is input to the other half divider. The output of LSI according to Appendix 13, characterized in that the output of.

(Supplementary Note 15)

The clock generated by the clock generation means of the LSI is input to the 1/2 divider corresponding to the multiplexer at the last stage and the multiplexer at the front end thereof, and the clock generated by the clock generation means of the LSI is input. The LSI according to Appendix 13, wherein an output is input through a phase adjuster.

(Appendix 16)

A data transmission / reception system for performing data transmission and reception between a first LSI and a second LSI, comprising: a data change detector for detecting a change in data output by the first LSI and a timing at which the second LSI receives data; A phase comparator for performing a phase comparison between a clock and data output by the first LSI, and when the data change detector detects a change in data output by the first LSI, according to a phase comparison result of the phase comparator And a timing adjusting circuit including a phase adjusting section for changing a phase of a clock that defines a timing at which the first LSI transmits data.

(Appendix 17)

The first LSI includes a plurality of multiplexers for converting parallel data into serial data sequentially, and includes a data transmission circuit for outputting data from the first LSI to the outside. .

(Supplementary Note 18)

The data transmission / reception system according to Appendix 17, wherein the multiplexers output data at half the bit width of the input data and double the speed.

(Appendix 19)

A data change detection unit for detecting a change in data output from the data transmission side multiplexer for each multiplexer serving as the transmitting side and the multiplexer serving as the receiving side, a clock defining the timing at which the data receiving side multiplexer receives data, and the data transmission A phase comparison section for performing a phase comparison with data output from the side multiplexer, and when the data change detection section detects a change in data output from the data transmission side multiplexer, the data transmission according to a phase comparison result of the phase comparison section A data transmitting / receiving system according to Appendix 18, comprising a timing adjusting circuit including a phase adjusting section for changing a phase of a clock that defines a timing at which the side multiplexer transmits data.

According to the present invention, even at a high data transfer rate, data transmission and reception between circuit blocks that perform data transmission and reception can be reliably performed without being affected by process variations or power supply voltage and temperature variations.

Claims (10)

A timing adjusting circuit for adjusting the timing of data transmission and reception between a data transmission unit for transmitting data and a data receiving unit for receiving the data, A phase comparison unit for comparing a phase of data output by the data transmitter and a phase of a clock that defines a timing at which the data receiver receives data; And And a phase adjuster for adjusting a phase of a clock that defines a timing at which the data transmitter transmits data according to a comparison result of the phase comparator. The apparatus of claim 1, further comprising a data change detector configured to detect a change in data output by the data transmitter. The phase adjuster is configured to determine a timing at which the data transmitter transmits the data according to a phase comparison result of the phase comparator when the data change detector detects a change in data output by the data transmitter. The timing adjustment circuit which changes a phase. A timing adjusting circuit for adjusting the timing of data transmission and reception between a data transmission unit for transmitting data and a data receiving unit for receiving the data, A dummy data output circuit for outputting 1010 repetitive data which always changes in data based on a clock defining a timing at which the data transmitter transmits data; A phase comparator for comparing a phase of a clock defining a timing at which the data receiver receives data with a phase of data output from the dummy data output circuit; And And a phase adjuster for changing a phase of a clock that defines a timing at which the data transmitter transmits data in accordance with a phase comparison result of the phase comparator. In an LSI in which data is sequentially transmitted and received between a plurality of blocks, A data change detection section for detecting a change in data output from the data transmitting block, and a phase of a clock defining a timing at which the data receiving block receives data and a phase of data output from the data sending block; When the phase comparison section and the data change detection section detect a change in data output from the data transmission side block, the data comparison side block defines a timing at which the data transmission side block transmits data according to the phase comparison result. And a timing adjusting circuit including a phase adjusting unit for changing a phase of a clock for each of the transmitting block and the receiving block. The phase adjustment according to claim 4, wherein the clock which is the object of phase adjustment between the specific data transmitting block and the data receiving block affects the data transmission / reception timing between the other data transmitting block and the data receiving block. LSI, characterized in that the additional arrangement. 5. The phase according to claim 4, wherein the clock which is the object of phase adjustment between the specific data transmitting side block and the data receiving side block does not affect the data transmission / reception timing between the other data transmitting side block and the data receiving side block. LSI, characterized in that the adjuster is arranged. 5. The apparatus of claim 4, wherein the plurality of blocks are a plurality of multiplexers for converting parallel data into sequential serial data. LSI, which outputs data at half speed and double speed. 8. A clock according to claim 7, wherein a clock defining a timing at which a final multiplexer of the plurality of multiplexers receives data is generated by clock generation means of the LSI, and each of the multiplexers on the transmitting side and the multiplexer on the receiving side is one-half minute. A cycle is provided, and the multiplexers other than the final stage supply a clock that divides the clock defining the data reception timing of the multiplexer of the subsequent stage into 1/2 frequency dividers through the phase adjuster, and the supplied clock LSI, characterized in that for specifying the transmission timing of data to be transmitted to the multiplexer after the multiplexer. In a data transmission and reception system for performing data transmission and reception between a first LSI and a second LSI, A data change detector for detecting a change in data output by the first LSI, a phase comparison comparing a phase of a clock defining a timing at which the second LSI receives data with a phase of the data output by the first LSI And a phase of a clock defining a timing at which the first LSI transmits data according to a phase comparison result of the phase comparator, when the data change detection unit detects a change in data output from the first LSI. And a timing adjusting circuit including a phase adjusting unit for changing the phase. 10. The method of claim 9, wherein the first LSI includes a plurality of multiplexers for converting parallel data into sequential serial data, and data transmission and reception, characterized in that it comprises a data transmission circuit for outputting data from the first LSI to the outside. system.

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