KR100835436B1 - Method for effectively arranging switch on ic lay out by use of mtcmos - Google Patents

Method for effectively arranging switch on ic lay out by use of mtcmos Download PDF

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KR100835436B1
KR100835436B1 KR1020060129645A KR20060129645A KR100835436B1 KR 100835436 B1 KR100835436 B1 KR 100835436B1 KR 1020060129645 A KR1020060129645 A KR 1020060129645A KR 20060129645 A KR20060129645 A KR 20060129645A KR 100835436 B1 KR100835436 B1 KR 100835436B1
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mtcmos
cells
logic
cell
logic cell
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KR1020060129645A
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Korean (ko)
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정현섭
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H01L2027/11809—Microarchitecture
    • H01L2027/11851—Technology used, i.e. design rules
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H01L2027/1189—Latch-up prevention

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

An effective arrangement method of switches is provided to enhance flexibility of IC design by adding a separation cell which connects only real grounds so as to arrange separately MTCMOS logic cells and non-MTCMOS logic cells. Non-MTCMOS cells(200) which is not applied by the MTCMOS method are arranged by a column unit. MTCMOS logic cells(202) applied by the MTCMOS method is arranged by the column unit. A separation cells(204) separate the MTCMOS logic cells into the two logic cell lines by being inserted between the MTCMOS logic cells. The non-MTCMOS logic cell is arranged on the line of the MTCMOS logic cell which is separated by the separation cells.

Description

ＭＴＣＭＯＳ를 이용한 ＩＣ 설계시 효율적 스위치 배치방법{METHOD FOR EFFECTIVELY ARRANGING SWITCH ON IC LAY OUT BY USE OF MTCMOS}Efficient switch placement method for IC design using MTCMOS (Method for EFFECTIVELY ARRANGING SWITCH ON IC LAY OUT BY USE OF MTCMOS)

도 1은 종래 MTCMOS 기법을 이용한 IC 설계 로직셀 배치 예시도,1 is a diagram illustrating an IC design logic cell arrangement using a conventional MTCMOS technique;

도 2는 본 발명의 실시 예에 따른 MTCMOS 기법을 이용한 IC 설계 로직셀 배치 예시도,2 is a diagram illustrating an IC design logic cell arrangement using the MTCMOS method according to an embodiment of the present invention;

도 3은 종래 MTCMOS 로직셀과 Non-MTCMOS 로직셀의 도메인간 신호 인터페이스 개념도,3 is a conceptual diagram of a signal interface between domains of a conventional MTCMOS logic cell and a Non-MTCMOS logic cell;

도 4는 본 발명의 실시 예에 따른 MTCMOS 로직셀과 Non-MTCMOS 로직셀간 신호 인터페이스 개념도, 4 is a conceptual diagram illustrating a signal interface between an MTCMOS logic cell and a Non-MTCMOS logic cell according to an embodiment of the present invention;

<도면의 주요 부호에 대한 간략한 설명><Brief description of the major symbols in the drawings>

200 : Non-MTCMOS 로직셀 204 : 구분셀200: Non-MTCMOS logic cell 204: Division cell

202 : MTCMOS 로직셀 206 : 리얼 그라운드202: MTCMOS logic cell 206: real ground

208 : 가상 그라운드208: virtual ground

본 발명은 MTCMOS(Multi-Threshold complementary metal-oxide semiconductor)를 이용한 IC 설계에 관한 것으로, MTCMOS 기술을 사용하는 IC 설계에서 효율적인 스위치 셀 배치 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to IC design using multi-threshold complementary metal-oxide semiconductor (MTCMOS), and to an efficient switch cell placement method in IC design using MTCMOS technology.

MTCMOS 기술은 CMOS를 사용하는 IC의 누설 전류(leakage current)를 줄이는데 효과적으로 사용되는 기술로서, 공급전원 및 논리회로 사이에 문턱전압(threshold voltage)이 상대적으로 높은 MOS(metal-oxide semiconductor) 트랜지스터 스위치를 직렬로 연결한 구조를 가지며, 위 MOS 스위치의 개폐여부에 따라 문턱 전압이 상대적으로 낮은 MOS 트랜지스터로 구성된 논리회로에 공급전원을 공급시키거나 차단시킴으로써 소모 전력을 줄일 수 있도록 하는 기술을 말한다.MTCMOS technology is effectively used to reduce leakage current of ICs using CMOS, and it has a metal-oxide semiconductor (MOS) transistor switch having a relatively high threshold voltage between the power supply and logic circuit. It has a structure connected in series and refers to a technology that can reduce power consumption by supplying or interrupting supply power to a logic circuit composed of MOS transistors having a relatively low threshold voltage depending on whether the MOS switch is opened or closed.

위와 같은 MTCMOS 기술을 위해 현재 많은 설계 방법론이 제안되어 있으나, 실제 구현방법은 상용 EDA tool의 기능적 한계에 많은 제약을 받고 있다.Many design methodologies have been proposed for the above MTCMOS technology, but the actual implementation method is limited by the functional limitations of commercial EDA tools.

즉, 현재 칩 설계 업무에 적용되는 Cadence 및 Synopsys의 제품인 P&R tool 들을 사용하여 MTCMOS 스위치 셀(switch cell)을 배치하는 경우 도 1에서 보여지는 바와 같이 행(row) 단위로 배치된 로직셀(logic cell)들에 대하여 스위치 셀(101)을 추가함으로써, 행 단위로 배치된 셀들의 누설 전류를 차단하는 기법이 주로 적용되고 있으나, 위 종래 기법에서는 MTCMOS 기법이 적용된 MTCMOS 로직셀들(100)과 MTCMOS 기법이 적용되지 않은 Non-MTCMOS 로직셀들(102)이 행 단위로만 배치되어야 하는 문제점이 있어 IC 설계상 유연성이 떨어지는 문제점이 있었다.That is, in case of arranging MTCMOS switch cell using P & R tools of Cadence and Synopsys, which are applied to current chip design work, logic cells arranged in rows as shown in FIG. By adding the switch cell 101 to the plurality of cells), a technique of blocking leakage current of cells arranged in rows is mainly applied. However, in the conventional technique, MTCMOS logic cells 100 and MTCMOS technique to which the MTCMOS technique is applied are applied. The non-MTCMOS logic cells 102, which are not applied, have to be disposed only in units of rows, thereby deteriorating flexibility in IC design.

따라서, 본 발명의 목적은 MTCMOS 기술을 사용하는 IC 설계에서 IC 설계의 유연성을 증가시키는 효율적인 스위치 셀 배치 방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide an efficient switch cell placement method that increases the flexibility of IC design in IC design using MTCMOS technology.

상술한 목적을 달성하기 위한 본 발명은 MTCMOS를 이용한 IC 설계시 효율적 스위치 배치방법으로서, (a)상기 MTCMOS 기법이 적용되지 않은 Non-MTCMOS 로직셀을 행단위로 배치시키는 단계와, (b)상기 MTCMOS 기법이 적용된 MTCMOS 로직셀을 행단위로 배치시키는 단계와, (c)상기 MTCMOS 로직셀 라인 중간에 삽입되어 상기 MTCMOS 로직셀 라인을 두 개의 로직셀 라인으로 분리시키는 구분셀을 배치시키는 단계와, (d)상기 구분셀로 분리된 MTCMOS 로직셀 라인상에 상기 Non-MTCMOS 로직셀을 배치시키는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides an efficient switch arrangement method for IC design using MTCMOS, comprising: (a) arranging non-MTCMOS logic cells to which the MTCMOS technique is not applied, and (b) the MTCMOS; Arranging the MTCMOS logic cells to which the technique is applied in rows, (c) disposing a separator cell inserted in the middle of the MTCMOS logic cell line to separate the MTCMOS logic cell line into two logic cell lines, and (d And disposing the non-MTCMOS logic cell on an MTCMOS logic cell line separated into the division cells.

이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시 예의 동작을 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment according to the present invention.

도 2는 본 발명의 실시 예에 따른 MTCMOS 기법을 이용한 IC 설계시 효율적인 스위치 배치 방법을 도시한 것이다.2 illustrates an efficient switch placement method in IC design using the MTCMOS technique according to an embodiment of the present invention.

이하, 위 도 2를 참조하여 MTCMOS 기술을 이용한 IC 설계시 효율적인 스위치 배치방법에 대해 상세히 설명하기로 한다.Hereinafter, an efficient switch arrangement method in designing an IC using MTCMOS technology will be described in detail with reference to FIG. 2.

먼저, 칩 설계 업무에 적용되는 Cadence 및 Synopsys의 제품인 P&R tool 들을 사용하여 MTCMOS 스위치 셀을 배치하는 경우 종래 행 단위로 배치된 셀들의 누설 전류를 차단하는 기법에서는 MTCMOS 기법이 적용된 MTCMOS 로직셀들과 MTCMOS 기법이 적용되지 않은 Non-MTCMOS 로직셀들이 행 단위로만 배치되어야 함에 따라 설계상 유연성이 떨어지는 문제점이 있었음은 전술한 바와 같다.First, in case of arranging MTCMOS switch cells using Cadence and Synopsys' P & R tools that are applied to chip design work, MTCMOS logic cells and MTCMOS applied MTCMOS method are used to block leakage current of cells arranged in a row unit. As described above, the non-MTCMOS logic cells to which the technique is not applied have to be disposed only in rows.

따라서 본 발명에서는 종래 행 단위로 MTCMOS 기법이 적용되는 단점을 개선하고자, 행 단위의 로직셀 내에 MTCMOS 동작을 구분할 수 있도록 도 2에서와 같이 리얼 그라운드에 연결되는 간단한 구분셀을 추가하여 행 단위 내에서 MTCMOS 기법이 적용되는 부분과 적용되지 않는 부분이 구분되도록 하여 설계의 유연성을 높이도록 하였다.Therefore, in the present invention, in order to improve the disadvantage that the conventional MTCMOS technique is applied on a row-by-row basis, a simple separator cell connected to real ground is added within a row-by-row unit as shown in FIG. The design flexibility is increased by distinguishing between the part where MTCMOS technique is applied and the part that is not.

즉, 본 발명에서는 위 도 2에서 보여지는 바와 같이 MTCMOS를 이용한 IC 설계시 효율적 스위치 배치방법으로서, MTCMOS 기법이 적용되지 않은 Non-MTCMOS 로직셀(200)과 MTCMOS 기법이 적용된 MTCMOS 로직셀(202)을 행단위로 배치시킨 후, MTCMOS 기법이 적용된 MTCMOS 로직셀 행에 MTCMOS 기법이 적용되지 않은 Non-MTCMOS 로직셀을 위치시켜야 하는 경우, 셀과 셀사이의 리얼 그라운드(Real GND)(204)만을 연결하는 구분셀(204)을 추가하여 IC를 설계함으로써, 같은 행 단위 내에서도 MTCMOS 기법이 적용된 MTCMOS 로직셀(202)과 MTCMOS 기법이 적용되지 않은 Non-MTCMOS 로직셀(200)을 구분할 수 있게 되는 것이다.That is, in the present invention, as shown in FIG. 2, as an efficient switch arrangement method for IC design using MTCMOS, the non-MTCMOS logic cell 200 to which the MTCMOS technique is not applied and the MTCMOS logic cell 202 to which the MTCMOS technique is applied are shown. Is arranged row by row, and when only the non-MTCMOS logic cell without the MTCMOS technique is to be placed in the MTCMOS logic cell row to which the MTCMOS technique is applied, only the real GND 204 is connected between the cells. By designing the IC by adding the division cells 204, the MTCMOS logic cell 202 to which the MTCMOS technique is applied can be distinguished from the non-MTCMOS logic cell 200 to which the MTCMOS technique is not applied.

도 3은 종래 MTCMOS 기법이 적용된 MTCMOS 로직셀(202)과 MTCMOS 기법이 적용되지 않은 Non-MTCMOS 로직셀(200)의 서로 다른 전원/그라운드(power/ground) 도메인(domain)(300, 302)간 신호 인터페이스(signal interface) 개념을 도시한 것으로, 위 도 3에 도시된 바와 같이, 종래 행 단위로 배열된 로직셀들 간에는 파워 게이팅이 적용된 MTCMOS 로직셀(202)과 파워 게이팅이 적용되지 않은 Non-MTCMOS 로직셀(200)간에 신호 송수신에 있어서는, 도메인간 신호의 송수신이 이루어질 수밖에 없어 로직셀간 신호 송수신에 있어서 지연(delay)이 발생하는 것을 알 수 있다.FIG. 3 is a diagram illustrating an operation between different power / ground domains 300 and 302 of an MTCMOS logic cell 202 to which a conventional MTCMOS technique is applied and a non-MTCMOS logic cell 200 to which an MTCMOS technique is not applied. As shown in FIG. 3, the MTCMOS logic cell 202 to which power gating is applied and the non-power gating are not applied to each other. In the transmission and reception of signals between the MTCMOS logic cells 200, it is inevitable that the transmission and reception of signals between domains is performed, and thus, a delay occurs in the transmission and reception of signals between logic cells.

이에 반해, 도 4는 MTCMOS 기법이 적용된 MTCMOS 로직셀(202)과 MTCMOS 기법이 적용되지 않은 Non-MTCMOS 로직셀(200)이 같은 전원/그라운드 도메인(400)내 셀간 신호 인터페이스 개념을 도시한 것으로, 위 도 4에 도시된 바와 같이, 본 발명의 실시 예에 따라 셀과 셀사이의 리얼 그라운드(Real GND)(206)만을 연결하는 구분셀(204)을 추가하여 같은 행 단위 내에서도 MTCMOS 기법이 적용된 MTCMOS 로직셀(202)과 MTCMOS 기법이 적용되지 않은 Non-MTCMOS 로직셀(200)이 함께 위치되도록 함으로써, 파워 게이팅이 적용된 MTCMOS 로직셀(202)과 파워 게이팅이 적용되지 않은 Non-MTCMOS 로직셀(200)간 신호의 송수신에 있어서, 셀간 신호 송수신이 이루어질 수 있도록 함으로써, 로직셀간 신호 송수신에 있어서 지연의 발생을 방지시킬 수 있음 알 수 있다.In contrast, FIG. 4 illustrates a concept of a signal interface between cells in the power / ground domain 400 in which the MTCMOS logic cell 202 to which the MTCMOS technique is applied and the non-MTCMOS logic cell 200 to which the MTCMOS technique is not applied are the same. As shown in FIG. 4, according to an embodiment of the present invention, the MTCMOS is applied to the MTCMOS even within the same row unit by adding a division cell 204 connecting only a real ground (GND) 206 between cells. By placing the logic cell 202 and the non-MTCMOS logic cell 200 to which the MTCMOS technique is not applied together, the MTCMOS logic cell 202 to which power gating is applied and the non-MTCMOS logic cell 200 to which the power gating is not applied In the transmission and reception of signals between), it is possible to prevent the occurrence of a delay in the transmission and reception of signals between logic cells by allowing signal transmission and reception between cells.

상기한 바와 같이, 본 발명에서는 MTCMOS 기술을 사용하는 IC 설계에서 효율적인 스위치 셀 배치 방법에 있어서, 행 단위로 배열되는 로직셀 사이에 리얼 그라운드만을 연결하는 구분셀을 추가하여 행 단위 내에서도 MTCMOS 기법이 적용된 MTCMOS 로직셀과 MTCMOS 기법이 적용되지 않은 Non-MTCMOS 로직셀이 구분되어 위치될 수 있도록 함으로써, IC 설계의 유연성을 높일 수 있게 된다.As described above, in the present invention, in an efficient switch cell arrangement method in an IC design using the MTCMOS technology, the MTCMOS technique is applied within a row unit by adding a division cell connecting only real ground between logic cells arranged in a row unit. By allowing MTCMOS logic cells and non-MTCMOS logic cells without MTCMOS techniques to be located separately, the IC design flexibility can be increased.

한편 상술한 본 발명의 설명에서 실시 예에는 구체적인 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.Meanwhile, the embodiments of the present invention described above have been described in detail, but various modifications can be made without departing from the scope of the present invention. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.

이상에서 설명한 바와 같이, 본 발명에서는 MTCMOS 기술을 사용하는 IC 설계에서 효율적인 스위치 셀 배치 방법에 있어서, 행 단위로 배열되는 로직셀 사이에 리얼 그라운드만을 연결하는 구분셀을 추가하여 행 단위 내에서도 MTCMOS 기법이 적용된 MTCMOS 로직셀과 MTCMOS 기법이 적용되지 않은 Non-MTCMOS 로직셀이 구분되어 위치될 수 있도록 함으로써, IC 설계의 유연성을 높일 수 있는 이점이 있다.As described above, in the present invention, in an efficient switch cell arrangement method in an IC design using the MTCMOS technology, the MTCMOS technique is applied within a row unit by adding a division cell connecting only real ground between logic cells arranged in a row unit. By applying the MTCMOS logic cell and the non-MTCMOS logic cell to which the MTCMOS technique is not applied, the IC design flexibility can be increased.

Claims (3)

MTCMOS를 이용한 IC 설계시 효율적 스위치 배치방법으로서,As an efficient switch placement method in IC design using MTCMOS, (a)상기 MTCMOS 기법이 적용되지 않은 Non-MTCMOS 로직셀을 행단위로 배치시키는 단계와,(a) arranging non-MTCMOS logic cells to which the MTCMOS technique is not applied, in rows; (b)상기 MTCMOS 기법이 적용된 MTCMOS 로직셀을 행단위로 배치시키는 단계와,(b) arranging MTCMOS logic cells to which the MTCMOS technique is applied, in rows; (c)상기 MTCMOS 로직셀 라인 중간에 삽입되어 상기 MTCMOS 로직셀 라인을 두 개의 로직셀 라인으로 분리시키는 구분셀을 배치시키는 단계와,(c) disposing a separator cell inserted in the middle of the MTCMOS logic cell line to separate the MTCMOS logic cell line into two logic cell lines; (d)상기 구분셀로 분리된 MTCMOS 로직셀 라인상에 상기 Non-MTCMOS 로직셀을 배치시키는 단계(d) disposing the non-MTCMOS logic cell on an MTCMOS logic cell line separated into the division cells; 를 포함하는 MTCMOS를 이용한 IC 설계시 효율적 스위치 배치방법.Efficient switch placement method for IC design using MTCMOS comprising a. 제 1 항에 있어서,The method of claim 1, 상기 (c)단계에서, 상기 구분셀은, 행으로 배치된 로직 셀들의 리얼 그라운드 공급을 위해 셀과 셀간의 리얼 그라운드를 전기적으로 연결하는 것을 특징으로 하는 MTCMOS를 이용한 IC 설계시 효율적 스위치 배치방법.In the step (c), the division cell, the IC switch using the MTCMOS method for efficient switch arrangement, characterized in that for electrically connecting the real ground between the cells for the real ground supply of the logic cells arranged in a row. 삭제delete
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