KR100831968B1

KR100831968B1 - Method of Packaging Semiconductor and Semiconductor Package of manufactured by using the same

Info

Publication number: KR100831968B1
Application number: KR1020060084383A
Authority: KR
Inventors: 정유환
Original assignee: 엠텍비젼 주식회사
Priority date: 2006-09-01
Filing date: 2006-09-01
Publication date: 2008-05-27
Also published as: KR20080020894A

Abstract

A packaging method for a wafer on which a bump is formed by a flip chip type or a wafer level package and a semiconductor package implemented thereby are disclosed. A protective layer is formed on the back surface of the wafer on which the bumps are formed. The protective layer is an elastomer having at least one reactor. Further, a buffer layer is interposed between the protective layer and the wafer in order to increase the bonding force between the protective layer and the wafer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor packaging method and a semiconductor package manufactured by the method.

1 is a flow chart illustrating a method of fabricating a wafer level package in accordance with the prior art.

2 is a cross-sectional view of a packaged wafer according to a preferred embodiment of the present invention.

3 to 6 are sectional views for explaining a process of packaging a wafer according to a preferred embodiment of the present invention.

Description of the Related Art

100: wafer 120: buffer layer

140: Protective layer 160: Bump

200: semiconductor chip

The present invention relates to a semiconductor device, and more particularly, to a semiconductor package device and a packaging method.

A semiconductor that performs a predetermined function is manufactured on a wafer-by-wafer basis. The wafer is provided with a plurality of chips having the same structure. Each chip is protected from the external environment through packaging, and can be easily mounted on a substrate.

The method of packaging the semiconductor and the type of the semiconductor package can be variously classified according to the function, shape, and mounting environment of the chip. In a typical case, a method of electrically connecting the pad formed on the chip and the lead pin through wire bonding and embedding the chip and the wire in a molding compound is used. Further, a method of using solder bumps to mount a plurality of chips on a limited area is also used.

The types of packages using bumps are largely divided into flip chip type packages and wafer level packages. The flip chip type package forms bumps directly on the pads formed on each chip. Further, the wafer level package is formed with a separate wiring electrically connected to the pad formed on the chip, and the bump or the ball grid is formed on the wiring.

Referring to FIG. 1, a semiconductor chip is formed on a wafer according to a conventional manufacturing process (S10). As described above, a plurality of semiconductor chips are regularly arranged on the wafer. Further, each chip is provided with a passivation film for protecting each functional block of the exposed pad and the chip.

Subsequently, a passivation film is formed on the passivation film, and a metal interconnection is formed on the passivation film surface (S20). The metal wiring is electrically connected to a pad provided on the chip.

Then, a bump is formed on the metal wiring (S30). The bumps have a substantially ball shape and may be formed through various methods such as using wire bonders, using dispensing, using solder paste, or solder depositing.

When a plurality of bumps are formed on the wafer, a test is performed to determine whether each chip is operating normally (S40). The probe is in contact with each pad to perform the test. A test signal is applied through a probe in contact with the pad, and a normal operation of the chip is determined through a probe connected to the output pad.

Subsequently, the chips on the wafer are separated from each other by sawing (S50). That is, each chip is separated along a scribing line provided between adjacent chips in the wafer.

The separated chips are mounted on a printed circuit board (S60). Methods for mounting the chip package on the printed circuit board are variously provided depending on the mounting environment. In most cases, the internal space formed by the contact between the ball and the printed circuit board provided in the package is filled with insulating material or the like. Generally, the process of filling with such an insulator is referred to as under-fill.

In the above-described package assembly process and package mounting process, the silicon constituting the chip has a characteristic that it is easily broken by an external force due to a weak ductility or malleability. Accordingly, a technique for protecting a single crystal silicon chip from an external environment by forming a protective film such as epoxy on the back surface of the chip has been developed.

U.S. Patent Nos. 6023094 and 6175162 disclose techniques for forming a protective film on the silicon backside. In the above patents, the protective film is made of a plastic material or an epoxy material. However, when only the protective film is provided on the back surface as in the above-mentioned patents, the protective film is peeled off due to environmental factors such as changes in humidity and temperature. Particularly, in the case of a protective film as a polymer material, the aging phenomenon is intensified by moisture and the like, and the film is repeatedly stretched and shrunk as the temperature changes, so that the protective film is peeled off from the silicon. When the protective film is peeled off from the silicon, the silicon is easily damaged by an external force, and in some cases, a progressive defect, which is continuously deteriorated in characteristics, may occur.

A first object of the present invention is to provide a semiconductor packaging method for protecting a semiconductor from an external environment.

A second object of the present invention is to provide a semiconductor package capable of protecting a semiconductor from an external environment.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: electrically connecting a bump to a pad of a wafer; Forming a buffer layer on the back surface of the wafer on which the bumps are formed; Forming a protective layer on the buffer layer; And curing the buffer layer and the protective layer, wherein the protective layer comprises an elastomer, and the buffer layer includes a silane coupling agent that readily bonds with the wafer. do.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a wafer having bumps formed on a front surface thereof; A buffer layer composed of a silane coupling agent for improving adhesion to the backside of the wafer; And a protective layer formed on the buffer layer and bonded to the buffer layer to protect the wafer from the external environment, wherein the protective layer is an elastomer.

The second object of the present invention is also achieved by a method of manufacturing a semiconductor device, comprising: electrically connecting a bump to a pad of a wafer; Forming a buffer layer on the back surface of the wafer on which the bumps are formed; Forming a protective layer on the buffer layer; And curing the buffer layer and the protective layer, wherein the protective layer comprises PDMS (polydimethylsiloxane) having at least one reactor that is an elastomer, the buffer layer comprising a silane coupling And a semiconductor package including a semiconductor device and an agent.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, the same reference numerals will be used for the same constituent elements in the drawings, and redundant explanations for the same constituent elements will be omitted.

Example

Referring to FIG. 2, a buffer layer 120 and a protective layer 140 are formed on the back surface of the wafer 100 including the plurality of bumps 160.

The buffer layer 120 is formed directly on the back surface of the wafer 100 and is composed of a silane coupling agent. The buffer layer 120 is adhered to the wafer 100 and bonded to the protective layer 140. Thus, the protective layer 140 is prevented from peeling off the wafer 100.

A protective layer 140 is provided on the buffer layer 120. The protective layer 140 is made of an elastomer that is a polymer material. When an external force is applied to the elastomer, the elastomer is remarkably stretched compared with the original length, and has the characteristic of returning to the original length when the external force is removed. Therefore, even if an external force is irregularly or periodically applied to the unit chip, the semiconductor chip is protected by the protective layer 140. When an external force is applied, the protective layer 140 has a predetermined elasticity and can absorb an external force, and the external force applied to the unit chip can be minimized.

In addition, the elastomer constituting the protective layer 140 is preferably PDMS (polydimethylsiloxane). The PDMS containing silicon atoms can readily combine with the silane coupling agent forming the buffer layer 120. Therefore, the protective layer 140 is strongly bonded to the buffer layer 120, and can prevent the protective layer 140 from being peeled from the back surface of the wafer due to an external environment such as external force, moisture, or temperature change.

According to the embodiment, an outer protective layer (not shown) composed of a polyimide film may be further formed on the protective layer 140. That is, the protective layer 140 may be further strengthened by forming a polyimide film having excellent heat resistance and cold resistance, and having characteristics such as flexibility, chemical resistance, and abrasion resistance on the protective layer 140.

The buffer layer 120, the protective layer 140, or the outer protective layer are formed at the wafer level. That is, the buffer layer 120, the protection layer 140, and the outer protection layer are formed on the entire back surface of the wafer before the sawing process for dividing the wafer 100 into individual chip units is performed. The wafer 100 on which the above-described multiple layers are formed is cut along the scribing line formed between the chips through the sawing process.

Thus, each chip has a buffer layer 120, a protective layer 140, or an outer protective layer on the backside. In addition, bumps 160 are formed on a pad or a predetermined region of the chip before the various layers are formed. Therefore, the chip on which the bump 160 is formed is mounted on a printed circuit board or the like. Since the back surface of the chip mounted on the printed circuit board is provided with the buffer layer 120 and the protection layer 140, the chip is protected against changes in external force or surrounding environment.

Referring to FIG. 3, a buffer layer 120 is formed on the back surface of the wafer 100 on which the bumps 160 are formed. First, the bump 160 is formed on the front surface of the wafer 100 as described with reference to FIG. That is, bumps 160 are formed on a plurality of chips provided on the wafer 100 through a flip chip type or wafer level package method.

A buffer layer 120 is formed on the back surface of the wafer 100 on which the bumps 160 are formed. As the buffer layer 120, various silane coupling agents may be used. The buffer layer 120 may be formed by spraying a liquid silane coupling agent onto the back surface of the wafer 100 using a spray method. When the silane coupling agent is sprayed on the backside, a liquid silane coupling agent is provided as a buffer layer 120 on the backside of the wafer 100.

Continuing with reference to FIG. 4, a protective layer 140 is formed on a liquid silane coupling agent. That is, a liquid protective layer 140 is formed on the wafer 100 having the silane coupling agent. The protective layer 140 is formed by injecting a predetermined amount of solution onto the back surface of the wafer 100 and forming a protective layer 140 on the entire rear surface of the wafer 100 through spin diffusion. Also, it is preferable that the protective layer 140 is made of an elastomer having at least one reactor. The elastomer has a characteristic of returning to the original shape after external force is applied, after the external force is applied. Also, the elastomer is preferably PDMS (polydimethylsiloxane).

4, the protective layer 140 is used as an elastomer, which is a kind of polymer material, to prevent the protective layer 140 from being easily deformed by an external force. Particularly, PDMS is used to utilize the property of easily bonding with a silane coupling agent because it contains silicon. If the buffer layer 120 is not formed with the silane coupling agent and the protective layer 140 is directly formed on the wafer backside by the PDMS, the protective layer 140 is easily peeled off from the wafer 100. Therefore, the silane coupling agent functions to prevent the PDMS forming the protective layer 140 from being peeled off.

Further, according to the embodiment, a polyimide film may be attached on the protective layer 140 that has been spin-diffused on the back surface of the wafer 100. [ The polyimide film is excellent in heat resistance and cold resistance, and is also excellent in flexibility, chemical resistance and abrasion resistance. Therefore, when the outer protective layer is formed of a polyimide film, there is an advantage that the influence due to a change in the external environment can be minimized.

Referring to FIG. 5, heat is applied to the wafer 100 having the buffer layer 120 and the protective layer 140 formed on its back surface, thereby curing the buffer layer and the protective layer in a liquid state. Thus, the buffer layer 120 is strongly bonded to the back surface of the wafer, and the protective layer 140 is strongly bonded to the buffer layer 120 while being hardened. If the outer protective layer is formed of a polyimide film before curing, heat can be applied to the outer protective layer composed of the buffer layer of the liquid phase and the protective layer and the polyimide film, and the curing process can be performed.

6, a sowing process is performed on the wafer 100 on which the buffer layer 120 and the protective layer 140 are formed. The wafer 100 on which the buffer layer 120 and the protective layer 140 are formed through sawing is separated per chip. A bump 160 is formed on the front surface of the semiconductor chip 200 and a buffer layer 120 and a protective layer 140 are formed on the back surface of the semiconductor chip 200.

Subsequently, the semiconductor chips 200 individually separated by sawing are mounted on a printed circuit board or the like. The semiconductor chip 200 on which the bumps 160 are formed is mounted on the printed circuit board by placing the semiconductor chip 200 at a predetermined position on the printed circuit board and reflowing the bumps 160 by applying heat to the bumps 160 Is electrically connected to the wiring region of the printed circuit board. Also, according to the embodiment, an underfill process may be added in which the spacing space between the printed circuit board and the semiconductor chip 200 is filled with an insulating material.

According to a preferred embodiment of the present invention described above, the protective layer is composed of an elastomer. In the mounting environment, the semiconductor chip is protected by the protective layer, and degradation in progress or deterioration in characteristics caused by defects of the semiconductor chip is prevented.

According to the present invention as described above, the protective layer is composed of an elastomer. Further, a buffer layer is provided between the elastic polymer and the semiconductor chip so that the elastic polymer is bonded to the back surface of the semiconductor chip. The semiconductor chip is protected from the external environment by an elastomer that is strongly bonded by the buffer layer. Particularly, when an unexpected external force is generated in an environment in which the electronic device is mounted in a limited area such as a mobile phone terminal, the semiconductor chip is protected by the elastic polymer forming the protective layer. Therefore, the defective progress of the semiconductor chip due to the external force or the external environment is prevented.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible.

Claims

Electrically connecting the bump to the pad of the wafer;

Forming a buffer layer on the back surface of the wafer on which the bumps are formed;

Forming a protective layer on the buffer layer; And

And curing the buffer layer and the protective layer,

Wherein the protective layer comprises an elastomer and the buffer layer comprises a silane coupling agent that readily bonds with the wafer.

The semiconductor packaging method according to claim 1, wherein the forming of the buffer layer comprises forming a liquid buffer layer on the backside of the wafer by spraying.

The semiconductor packaging method according to claim 1, wherein the forming of the protective layer comprises forming a liquid elastomer by spin diffusion.

4. The method of claim 3, wherein the elastomer comprises PDMS (polydimethylsiloxane) having at least one reactor.

The semiconductor packaging method according to claim 1,

Further comprising the step of sawing the wafer after the step of curing the buffer layer and the protective layer to separate each semiconductor chip.

Claim 6 has been abandoned due to the setting registration fee.

The method of claim 1, wherein electrically connecting the bumps to the pads of the wafer comprises performing flip chip type packaging to electrically connect the bumps to the top of the pads.

Claim 7 has been abandoned due to the setting registration fee.

The semiconductor packaging method according to claim 1, wherein the step of electrically connecting the bumps to the pads of the wafer is a wafer level packaging in which bumps are formed on separate wirings electrically connected to the pads.

The method of claim 1, wherein after forming the protective layer on the buffer layer,

And forming an outer protective layer formed of a polyimide film on the protective layer.

A wafer having bumps formed on its front surface;

A buffer layer composed of a silane coupling agent for improving adhesion to the backside of the wafer;

And a protective layer formed on the buffer layer and coupled with the buffer layer to protect the wafer from the external environment,

Wherein the protective layer is an elastomer.

10. The semiconductor package of claim 9, wherein the buffer layer is formed on the wafer using a spray process and a liquid silane coupling agent is bonded to the back surface of the wafer through a curing process.

10. The semiconductor package of claim 9, wherein the elastomer comprises polydimethylsiloxane (PDMS) having at least one reactor.

12. The semiconductor package of claim 11, wherein the protective layer is formed by applying a liquid-state elastomer on the entire upper surface of the buffer layer by spin diffusion and then bonding the buffer layer through a curing process.

10. The semiconductor package of claim 9, wherein the semiconductor package further comprises an outer protection layer formed of a polyimide film on the protection layer.

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