KR100831799B1 - Semiconductor storage - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a technique for preventing high speed read while preventing read disturbance in a phase change memory using chalcogenide as a storage medium. In a phase change memory cell array consisting of a selection transistor and a chalcogenide, the potential of the substrate of the selection transistor is separated in the direction crossing the word line and operated as follows. At the time of writing, a forward current flows between the substrate and the source line to which chalcogenide is connected, and no selection transistor is used. On the other hand, at the time of reading, the cell is selected by the selection transistor. As a result, the write voltage can be made sufficiently larger than the read voltage, thereby preventing read disturb and realizing high speed operation.

Select transistor, source line, read disturb

Description

Semiconductor Memory Device {SEMICONDUCTOR STORAGE}

The present invention relates to a semiconductor memory device. In particular, it relates to a random access memory (RAM), which operates at low voltage and which has high speed and nonvolatileness.

Driven by the demand of mobile devices typified by mobile phones, the growth of the market for non volatile memory is remarkable. The representative is FLASH memory, but since it is inherently slow, it is used as a programmable ROM. On the other hand, a high speed DRAM is required as a working memory, and both FLASH and DRAM are mounted as a memory for a portable device. When the device having the characteristics of these two memories is realized, the impact is extremely large in that not only it is possible to make one chip of FLASH and DRAM, but also replace all the semiconductor memories.

As one of such memories, a memory using phase change has been proposed by lntel in 2001 IEDM (lnternational Electron Device Meeting).

 Next, the operation principle of this memory will be briefly explained. The phase change memory uses, as a storage node, a material called chalcogenide whose resistance is different depending on the crystal state. Chalcogenide is a material used for media of DVDs and CDs, and representative examples thereof include Ge-Sb-Te-based systems and Ag-In-Sb-Te-based systems containing at least antimony (Sb) and tellurium (Te). The basic memory cell is composed of a selection transistor and chalcogenide, is similar to a so-called DRAM cell, and can be considered to have replaced a capacitor with chalcogenide. The chalcogenide has a crystal state of single crystal or amorphous, and its resistance varies by 10 to 10,000 times. By using such a difference, it is set as a solid memory. In the case of MRAM (Magnetic RAM), which has attracted attention as a nonvolatile memory, the change rate of the resistance is about 40%, so that the phase change memory is much larger, and data can be easily sensed.

In order to change the chalcogenide crystal state, Joule's Heat generated by applying a voltage is used. When amorphous, chalcogenide is heated to about 600 ° C. to dissolve and quenched. When crystallizing, it is maintained at about 50 nsec at a temperature of about 400 ° C. Therefore, pulses as shown in Fig. 2 are given to data recording. At the time of reading, the word line is turned on, and two values of information ('0', '1') are determined by the current value flowing between the common ground line and the bit line.

As a phase change memory, there is disclosed a structure in which a crystal state of chalcogenide is changed by a current from a diode using a diode matrix (Patent Documents 1 and 2). There is also disclosed a structure of a phase change memory in which a transistor and a chalcogenide are cascaded to flow a current from the transistor to change the crystal state of the chalcogenide (Non-Patent Document 1).

Patent Document 1: US Patent No. 5,166,758

Patent Document 2: US Patent No. 5,536,947

[Non-Patent Document 1] M.Gill, "2002 I.S.C.C (20021sscc), 12 .4.

0vonic unified memory ”, 2002, P.202

One of the important problems of phase change memory is the prevention of read disturb. This will be described in detail below. 3 is a memory cell structure according to the present invention. From the point of view of performance and cost, the memory cell transistor uses a logic core MOS. As a result of this, when a 90 nm node is applied, for example, the bit line voltage is 1.0V. In this memory, as shown in Fig. 4, two bit line applied voltages and time are used during writing. On the other hand, when reading, it is necessary to apply a bit voltage sufficiently lower than the write voltage so as not to destroy the data (to prevent read disturb). By the way, demands for high-speed operation, including on-vehicle microcomputers, are high, and for this reason, it is necessary to raise the read bit line voltage and increase the cell current. That is, in the developing memory cell, the speed of the cell and the prevention of read disturb are in a trade-off relationship, and there is a limit to the speed of the cell.

In order to solve the above problems, a cell array method is used in which cell transistors are not used during data writing. 1 shows a memory array according to the present invention. In data writing, a bias in the forward direction is applied between the substrate and the source line to the selected cell. At that time, a voltage as shown in FIG. 1 is applied to suppress the leakage current in the unselected cell. According to the present invention, it is possible to increase the write voltage beyond the breakdown voltage of the transistor (2V in FIG. 1). As a result, the read voltage can be increased, the read disturb can be prevented and the cell current increased. In this case, the voltage between the word line and the bit line of the selected cell is greater than the withstand voltage of a 10-year guarantee, but as described in the lower right border, there is no problem when it is assumed to be used as a mixed microcomputer. .

1 is a view showing a memory array method according to the present invention.

2 is a diagram showing a method of writing a phase change memory.

3 is a diagram illustrating a conventional phase change memory cell.

4 is a diagram showing a voltage application method in the memory array of the present invention.

FIG. 5 is a view showing one upper surface of the manufacturing process in Example 1 of the present invention. FIG.

Fig. 6 is a diagram showing one cross section of the manufacturing process in Example 1 of the present invention.

Fig. 7 is a diagram showing one top surface of the manufacturing process in Example 1 of the present invention.

Fig. 8 is a diagram showing one top surface of the manufacturing process in Example 1 of the present invention.

9 is a view showing one cross section of the manufacturing process in Example 1 of the present invention.

Fig. 10 is a diagram showing one top surface of the manufacturing process in Example 1 of the present invention.

It is a figure which shows 1 cross section of a manufacturing process in the Example of this invention.

12 is a view showing one upper surface of the manufacturing process in Example 1 of the present invention.

Fig. 13 is a diagram showing one cross section of the manufacturing process in Example 1 of the present invention.

Fig. 14 is a view showing one upper surface of the manufacturing process in Example 1 of the present invention.

Fig. 15 is a diagram showing one cross section of the manufacturing process in Example 1 of the present invention.

Fig. 16 is a diagram showing an example of the read operation in the first embodiment of the present invention.

Fig. 17 is a diagram showing an example of one-bit recording operation in the first embodiment of the present invention.

18 is a diagram showing an example of a burst write operation in the first embodiment of the present invention.

Fig. 19 is a diagram showing an example of the one-bit recording operation in the first embodiment of the present invention.

20 is a diagram showing an example of a burst write operation in the first embodiment of the present invention.

21 is a diagram showing an example of a burst write operation in the first embodiment of the present invention.

Fig. 22 is a diagram showing one upper surface of the manufacturing process in Example 2 of the present invention.

Fig. 23 is a diagram showing one upper surface of the manufacturing process in Example 2 of the present invention.

Fig. 24 is a diagram showing one upper surface of the manufacturing process in Example 2 of the present invention.

Fig. 25 is a diagram showing one upper surface of the manufacturing step in Example 2 of the present invention.

Fig. 26 is a diagram showing one upper surface of the manufacturing step in Example 3 of the present invention.

Fig. 27 is a diagram showing one upper surface of the manufacturing process according to the third embodiment of the present invention.

Fig. 28 is a diagram showing one cross section of the manufacturing process in Example 3 of the present invention.

Fig. 29 is a diagram showing one upper surface of the manufacturing process according to the fourth embodiment of the present invention.

It is a figure which shows one upper surface of the manufacturing process in the Example of this invention.

Fig. 31 is a diagram showing one upper surface of the manufacturing step in Example 4 of the present invention.

32 is a diagram showing one upper surface of the manufacturing process according to the fourth embodiment of the present invention.

Fig. 33 is a diagram showing one cross section of the manufacturing process in Example 4 of the present invention.

Fig. 34 is a diagram showing one top surface of the manufacturing process according to the fifth embodiment of the present invention.

It is a figure which shows the one upper surface of the manufacturing process in the Example of this invention.

Fig. 36 is a diagram showing one cross section of the manufacturing step in Example 5 of the present invention.

Fig. 37 is a diagram showing one cross section of the manufacturing step in Example 5 of the present invention;

(Explanation of the sign)

1, 101... Chalcogenide 2... Silicon substrate

3…. Impurity diffusion layer 4,5... Conductive plug

6. Element isolation region 7. Transistor formation area

8 … p-type diffusion layer region 9. n-type diffusion layer region

10... Photoresist 11, 1101... Word line

12, 1201... Conductive plugs 13, 1301, 1302. Interlayer insulation film

14, 15, 1401... Tungsten 20... transistor

Hereinafter, it demonstrates in detail using an Example.

 Example 1

In this embodiment, the manufacturing method of the memory array shown in FIG. 1 will be described in detail while following the manufacturing process. In addition, all the figures show only the memory array part. First, the device isolation region 6, as shown in the top view of FIG. 5, is formed. For this reason, trench grooves are formed in the silicon substrate by ordinary photolithography and dry etching. Subsequently, a CMOS well is formed by a normal manufacturing method. In the memory array portion, an n-type well is formed. Further, in order to realize the memory array of FIG. 1, the substrate potential of the cell array is separated in the parallel direction with the bit lines. For this reason, only the memory array portion is opened by a normal photolithography process, and a p-type impurity diffusion layer region 8 is formed thereon by an impurity implantation method directly below the element formation region 7. 6, the cross-sectional structure along the A-A line in FIG. 5 is shown.

By making the impurity implantation region 8 shallower than the depth of the element isolation 6, it is possible to self-align the substrate potential of the array using the element isolation region 6.

Therefore, according to the present embodiment, it is not necessary to widen the interval between the bit lines in order to ensure alignment, and as a result, the memory cell area does not increase.

Next, word lines 11 and 1101 are formed by a normal CMOS process as shown in FIG. Further, for the purpose of forming the diffusion layer of the transistor, the word lines 11 and 1101 are implanted into the mask with n-type impurities by a conventional ion implantation method, and heat treatment necessary for activation is performed. It goes without saying that in the peripheral circuit area, the desired CMOS transistor is formed. Subsequently, a salicide process was performed in the same manner as the peripheral circuit region for the purpose of reducing the word line resistance and the diffusion layer resistance. Incidentally, although details will be described later, the word lines 1101 are used to electrically separate the diffusion layers of adjacent cells. In this respect, it is pointed out that the role is different from other word lines 11.

Next, a source line (SL line in Fig. 1) is formed. First, in order to form the interlayer insulating film 13, a 500 nm silicon oxide film is deposited and planarized by a normal CMP process. Furthermore, the contact hole for the SL wire connection is opened. In addition, 200 nm of tungsten was deposited for the purpose of forming the conductive plug 12, and planarized by a normal CMP process, and the top view is as shown in FIG. In addition, in FIG. 8, the interlayer insulation film is not shown in order to make it easy to see. Of course, the electric plug may be an electrode other than tungsten, such as TiN, Ti, Al, Cu, or a stacked structure thereof. 9 is a cross-sectional view taken along line BB of FIG. 8. Next, chalcogenide 101 is deposited by 50 nm, and tungsten 14 made of an SL line is deposited by 100 nm thereon.

Subsequently, the laminated film of chalcogenide 101 and tungsten 14 was processed by normal lithography and dry etching, and the top view and sectional drawing were as shown in FIGS. Of course, the SL wire material may be an electrode other than tungsten, such as TiN, Ti, Al, Cu, or a laminated structure thereof.

Next, bit lines are formed. As in the case of forming the source line, due to the formation of the interlayer insulating film 1301, a 500 nm silicon oxide film is deposited and planarized by a normal CMP process. In addition, 200 nm of tungsten was deposited for the purpose of forming the conductive plug 1201, and planarized by a normal CMP process, as shown in FIG. Of course, the electric plug may be an electrode other than tungsten, such as TiN, Ti, Al, Cu, or a stacked structure thereof. In addition, in FIG. 12, the interlayer insulation film is not shown in order to make it easy to see. FIG. 13 is a sectional view taken along line BB in FIG. 12. Next, 100 nm of tungsten 1401 made of BL lines is deposited. Subsequently, tungsten 1401 is processed by normal lithography and dry etching, and the top view and the cross sectional view are as shown in Figs. The BL wire material may be an electrode other than tungsten, such as TiN, Ti, Al, Cu, or a stacked structure thereof. Thereafter, a multilayer wiring layer was formed to obtain a desired semiconductor memory device.

16 shows an example of a read operation in the array of FIG. In this figure, an operation of reading the memory cell MC11 at the intersection of the word line WL1 and the bit line BL1 is shown. Initially, the bit line to which the memory cell to be read is connected is set to the read bit line precharge level. In this figure, it is set to 0.5V. This voltage is a voltage at which the phase state of the chalcogenide film does not change in a read operation. Thereafter, the word line WL1 corresponding to the read address is set from a voltage in the standby state, for example, 0V, to a voltage in the read select state, for example, 1V. As a result, the memory cell transistor (symbol) is turned on. At this time, when the chalcogenide film is in the low resistance state, the bit line BL1 is rapidly discharged to the ground level 0V as shown by the dotted line in the bit line BL1 in FIG. On the other hand, when the chalcogenide film is in a high resistance state, like the solid line in the bit line BL1 in FIG. 16, the bit line BL1 maintains near the precharge level. Although omitted in FIG. 1, the sense amplifier reads the state of H '/ L' of the bit line BL1 and outputs it to the outside of the array. After the sense amplifier senses the signal of the bit line, the bit line BL1 is set to the equipotential with the source line SL1 for any data. This prevents the phase state of the chalcogenide film from changing due to the current at the time of reading. Thereafter, the word line WL1 is set to the voltage in the standby state, and the read cycle ends.

Next, an example of the recording operation will be described with reference to FIG. This example shows an operation of rewriting the phase state of the chalcogenide film of the memory cell MC11 at the intersection of the word line WL1 and the bit line BL1. Initially, when a write command is input, the substrate potentials SUB1, SUB2,... The voltage in this standby state, for example, 0V, is set from a voltage when no write is selected, for example, -1V. Before and after this, the source lines SL1, SL2,... Are connected to the source node of the memory cell. The voltage in this standby state, for example, 0V, is set to a voltage at the time of no recording selection, for example, 1V. Next, the word line WL1 to which the write select cell is connected is set from a voltage in the unselected state, for example, 0V to a voltage in the write select state, for example, -1V. Next, the source line SL1 to which the write select cell is connected is set from the voltage in the write non-select state to a voltage in the write select state, for example, -1V. Thereafter, the bit line BL1 to which the write select cell MC11 is connected is set from a voltage in the standby state, for example, 0V, to a voltage in the write select state, for example, 1V. As a result, the substrate node SUB1 to which the memory cell transistors connected to the bit line BL1 are commonly connected is driven along the write data. Here, in the case where the write data makes the chalcogenide film high, the reset write voltage, for example, 1V is set from the voltage in the non-selected state, as shown by the solid line of the substrate node SUB1 waveform in FIG.

On the other hand, when the recording data causes the chalcogenide film to be in a low resistance state, as shown by the dotted line of the substrate node SUB1 waveform in FIG. . A desired voltage is applied to the substrate node SUB1 for a desired period, and a current required for writing flows through the chalcogenide film. Thereafter, the substrate node SUB1 is set to the voltage in the write non-select state. After the substrate node SUB1 is set to the non-selected state, the bit line BL1 is set to the voltage of the standby state. Next, the write select source line SL1 is set from the write select state to the voltage of the standby state, and after the source line becomes the standby state, the word line WL1 is set from the voltage of the write select state to the voltage of the standby state. do. Finally, the source line SL2 of recording non-selection is selected. From this recording non-selection state, the state is set to the standby state. Before and after the non-selective substrate node SUB2. Is set to the voltage of the standby state from the write non-selection state.

Next, a burst write operation in which memory cells on one word line are sequentially rewritten will be described with reference to FIG. The voltages in the standby state, the write selection state, and the write non-selection state of the bit line, word line, source line, and substrate node are as shown in FIG.

In the figure, the memory cells MC11 and MC21 on the word line WL1. To write to the memory cell on the word line WL2. As in the example of writing to one memory cell described above, when a write command is input, the substrate potentials SUB1, SUB2,... Source lines SL1, SL2,... Which are set from the standby voltage to the voltage at the time of non-writing selection and are connected to the source node of the memory cell. The voltage at the time of non-recording selection is set from the voltage in this standby state. Next, the write word line WL1 is set from the voltage in the standby state to the voltage in the write select state. Next, the write select source line SL1 is set from the voltage in the write non-select state to the voltage in the write select state. The bit line to which the memory cell to be written next is connected is driven. For example, in Fig. 18, the chalcogenide film of the memory cell MC11 is made to have low resistance or high resistance. First, the bit line BL1 is set from the voltage in the standby state to the voltage in the write select state. Next, along this, the substrate node SUB1 corresponding to the bit line BL1 is driven along the write data. Here, since the write data is a case where the chalcogenide film has a high resistance, it is set from the voltage in the non-selected state to the reset write voltage. A desired voltage is applied to the substrate node SUB1 for a desired period, and a current necessary for writing flows through the chalcogenide film. Thereafter, the substrate node SUB1 is set to the voltage in the write non-select state. Next, an operation of writing to the memory cell MC12 on the same word line WL1 is performed. Similarly to the bit line BL1 and the substrate node SUB1 in the above write operation to the memory cell MC11, the bit line BL2 is set from the standby voltage to the voltage of the write select state. In the figure, an example of performing a set recording operation is shown. The substrate node SUB2 corresponding to the bit line BL2 is set to the set write voltage, so that a current flows through the chalcogenide film. After passing a current for a desired period, the substrate node SUB2 is set from the write selection state to the non-selection state. Similarly to this, the write operation of the memory cells on the same word line WL1 is sequentially performed. At the time when the write operation to the word line WL1 is finished, the write select source line SL1 starts from the voltage in the write select state. , The voltage is set to the write non-select state.

Thereafter, the word line WL1 is set from the voltage in the write select state to the voltage in the standby state. Subsequently, a case where an operation of writing to a memory cell on another word line, for example, word line WL2, is described. After the word line WL1 is in the standby state, the word line WL2, which is the next write select word line, is set from the standby voltage to the voltage in the write selection state. Thereafter, the source line SL2 corresponding to the write select word line is set from the voltage in the write non-select state to the voltage in the write select state. Subsequently, similarly to the write operation to the memory cell on the word line WL1, the bit line to which the write memory cell is connected and the substrate node corresponding thereto are sequentially driven in accordance with the write data. As a result, a write operation to the memory cells on the write select word line WL2 is performed. When the write operation to the word line WL2 is finished, the write select source line SL2 is set from the voltage in the write select state to the voltage in the write non-select state as in the case of the word line WL1 described above. The word line WL2 is set from the write select state to the standby state. In the figure, the case where the recording operation ends here is shown.

After the word line WL2 is set to the standby state, all the source lines SL1, SL2,... Is set from the voltage in the write non-select state to the voltage in the standby state. At the same time, all the substrate nodes SUB1, SUB2... Is set from the voltage in the write non-select state to the voltage in the standby state. In FIG. 18, the write cycle can be shortened when the memory cells on the word lines are sequentially rewritten as compared with FIG. 17. Furthermore, the write cycle can be shortened even in an operation of sequentially rewriting the plurality of word lines. In this case, a high speed recording operation can be realized. At the same time, since the word line and the source line are not driven for every recording cell, the power consumption can be reduced.

17 and 18 show the operation of writing one memory cell in one write cycle, but it is possible to write to a plurality of memory cells by simultaneously driving a plurality of bit lines and substrate nodes corresponding thereto. In this case, there is an advantage that the writing time on one word line can be shortened, and the recording cycle can be speeded up.

Next, a modification of the above-described recording method will be described with reference to FIG. 19. In the above recording method, the write setting voltage of the substrate node is changed in accordance with the write data, but in Fig. 19, the write setting voltage of the source line is changed along with the write data.

This example shows an operation of rewriting the phase state of the chalcogenide film of the memory cell MC11 at the intersection of the word line WL1 and the bit line BL1. Initially, when a write command is input, the substrate potentials SUB1, SUB2,... The voltage in this standby state, for example, 0V, is set to a voltage at the time of no recording selection, for example, -1V. Almost simultaneously with this, the source lines SL1, SL2,... Are connected to the source node of the memory cell. The voltage in this standby state, for example, 0V, is set to a voltage at the time of no recording selection, for example, 1V. Next, the bit line BL1 to which the write select cell MC11 is connected is set from a standby voltage, for example, 0V, to a write select voltage, for example, 1V. As a result, the substrate node SUB1 to which the memory cell transistors connected to the bit line BL1 are commonly connected is driven from a voltage in the write non-select state to a voltage in the write select state, for example, 1V. Next, the word line WL1 to which the write select memory cell MC11 is connected is driven from a voltage in the standby state, for example, 0V, to a voltage in the write select state, for example, -1V. Thereafter, the source line SL1 to which the write select cell is connected is driven along the write data. Here, when the write data has a high resistance to the chalcogenide film, the reset write voltage, for example, -1V is set from the voltage in the write non-selection state as shown by the dotted line of the source line SL1 in Fig. 19. On the other hand, when the write data makes the chalcogenide film low, the set write voltage, for example, -0.5V is set from the voltage in the write non-selected state as shown by the solid line of the source line SL1 in FIG. A desired voltage is applied to the source line SL1 for a desired period, and a current required for writing flows through the chalcogenide film. Thereafter, it is set to the voltage in the recording unselected state. After the source line SL1 is set to the non-select state, the word line WL1 is set to the voltage of the standby state. Subsequently, the substrate node SUB1 is driven from the voltage in the write selection state to the voltage in the standby state. After the substrate node SUB1 is driven in the standby state, the bit line BL1 is set from the voltage in the write selection state to the voltage in the standby state.

Finally, the recording non-selection substrate node SUB2... Set to the voltage in the recording non-selection state. Is set to the standby voltage. Almost simultaneously with this, the write non-select source line SL2... Set to the voltage in the write non-select state. This voltage is set in the standby state, and the write operation is terminated.

In this operation, the timing at which the word line WL1 is the voltage in the selected state is driven earlier than the bit line BL1 is driven in the selected state, or the substrate node SUB1 is driven in the selected state. It is better than before. Similarly, the timing for bringing the word line WL1 in the write select state into the standby state may also be after the substrate node SUB1 is in the standby state or after the bit line is in the standby state.

In the present recording method, since the source line has a lighter capacity load than the substrate node as compared with Figs. 17 and 18, the controllability of the write operation is good.

Next, as a modification of the present writing method, an operation of burst writing the data of the memory cells on the bit line in sequence will be described with reference to FIG. The voltages in the standby state, write selection state, and write non-selection state of the bit line, the word line, the source line, and the substrate node are as shown in FIG. In the figure, the memory cells MC11 and MC21 on the bit line BL1. To write to the memory cell on the bit line BL2. As in the above example of writing to one memory cell of FIG. 19, when a write command is input, the substrate potentials SUB1, SUB2,... The source lines SL1 and SL2 connected to the source node of the memory cell are set from the voltage in the standby state to the voltage in the non-write state from the standby state. Is set. Next, the write bit line BL1 is set from the voltage in the standby state to the voltage in the write select state. Next, the write select substrate node SUB1 is set from the voltage in the write non-select state to the voltage in the write select state. The word line to which the memory cells to be written next are connected is driven. For example, in FIG. 20, the chalcogenide film of the memory cell MC11 is made to have a low or high resistance. First, the word line WL1 is set from the voltage in the standby state to the voltage in the write select state. Next, according to this, the source line SL1 is driven along the write data. In this case, since the write data is a case where the chalcogenide film has a high resistance, it is set from the voltage in the non-selected state to the reset write voltage. A desired voltage is applied to the substrate node SUB1 for a desired period, and a current necessary for writing flows through the chalcogenide film. Thereafter, it is set to the voltage in the write non-selection state. Next, an operation of writing to the memory cell MC21 on the same bit line BL1 is performed. Like the word line WL1 and the source line SL1 in the write operation to the memory cell MC11, the word line WL2 is set from the voltage in the standby state to the voltage in the write select state, so that the source line SL2 Along with this write data, a set write voltage or reset write voltage is set, and a current flows through the chalcogenide film. After passing a current for a desired period, the source line SL2 is set from the write select state to the non-select state. Similarly to this, the write operation of the memory cells on the same bit line BL1 is sequentially performed. At the end of the write operation to the bit line BL1, the write select substrate node SUB1 is set from the voltage in the write select state to the voltage in the write non-select state. Thereafter, the bit line BL1 is set from the voltage in the write selection state to the voltage in the standby state. Subsequently, a case where an operation of writing to a memory cell on another bit line, for example, the bit line BL2, is described. After the bit line BL1 is in the standby state, the bit line BL2, which is the next write select bit line, is set from the standby voltage to the voltage in the write selection state. Subsequently, the substrate node SUB2 corresponding to the write select bit line is set from the voltage in the write non-select state to the voltage in the write select state. Subsequently, similarly to the write operation to the memory cell on the bit line BL1, the word line to which the write memory cell is connected and the source line corresponding thereto are sequentially driven along the write data. As a result, a write operation to the memory cell on the write select bit line BL2 is performed. When the write operation to the bit line BL2 ends, the write select substrate node SUB2 is set from the voltage in the write select state to the voltage in the write non-select state as in the case of the bit line BL1 described above. Line BL2 is set from the write selection state to the standby state. In the figure, the case where the recording operation ends here is shown. After the bit line BL2 is set to the standby state, all the substrate nodes SUB1, SUB2,... Is set from the voltage in the write non-select state to the voltage in the standby state.

At the same time, all the source lines SL1, SL2,... Is set from the voltage in the write non-select state to the voltage in the standby state. In FIG. 20, the write cycle can be shortened when the memory cells on the bit lines are sequentially rewritten as compared with FIG. 19. Furthermore, the write cycle can be shortened even in the operation of sequentially rewriting the plurality of bit lines. In this case, a high speed recording operation can be realized. At the same time, since the bit line and the substrate node are not driven for every recording cell, the power consumption can be reduced.

As a modification of Fig. 20 described above, a method of writing in a burst operation while sequentially selecting bit lines in a memory cell on a word line will be described with reference to Fig. 21. The voltages in the standby state, write selection state, and write non-selection state of the bit line, word line, source line, and substrate node are the same as in FIG. In the figure, memory cells MC11 and MC12 on the word line WL1. To write to the memory cell on the word line WL2. As in the example of writing to one memory cell of Fig. 19, when a write command is input, the substrate potentials SUB1, SUB2,... Is set from a standby voltage to a voltage at write non-selection, and is connected to the source lines SL1, SL2,... Connected to the source node of the memory cell. The voltage at the time of non-recording selection is set from the voltage in this standby state. Next, the write word line WL1 is set from the voltage in the standby state to the voltage in the write select state. The bit line to which the memory cell to be written next is connected is set from the voltage in the standby state to the voltage in the write select state. Next, the substrate node SUB1 to which the memory cell transistors connected to the bit line BL1 are commonly connected is set from the voltage in the write non-selected state to the voltage in the selected state. Next, the source line SL1 to which the recording cells are connected is driven along the recording data. Here, an operation for increasing the chalcogenide film of the memory cell MC11 is performed. At this time, the source line SL1 is set from the voltage in the write non-selection state to the reset operation voltage. A desired voltage is applied to the source line SL1 for a desired period, and a current required for writing flows through the chalcogenide film. Thereafter, it is set to the voltage in the write non-selection state. Next, an operation of writing to the memory cell MC12 on the same word line WL1 is performed. In the same manner as the bit line BL1, the substrate node SUB1, and the source line SL1 in the write operation to the memory cell MC11, the bit line BL2 is set from the standby voltage to the voltage in the write select state. do. Subsequently, the substrate node SUB2 corresponding to the bit line BL2 is set to the voltage in the write select state. As a result, the source line SL1 to which the recording cells are connected is driven along the recording data. Here, an example of the operation of reducing the chalcogenide film is shown. At this time, the source line SL1 is driven from the voltage in the non-selected state to the set operating voltage to flow a current through the chalcogenide film. After the desired period and the current flows, the source line SL1 is removed from the write select state. It is set to the non-select state. Thereafter, the substrate node SUB2 is set from the voltage in the selected state to the voltage in the non-selected state, and subsequently, the bit line BL2 is set from the voltage in the write select state to the voltage in the standby state.

Similarly to this, the write operation of the memory cells on the same word line WL1 is sequentially performed. At the end of the write operation to the word line WL1, the word line WL1 is set from the voltage in the write selection state to the voltage in the standby state. Subsequently, a case where an operation of writing to a memory cell on another word line, for example, word line WL2, is described. After the word line WL1 is in the standby state, the word line WL2, which is the next write select word line, is set from the standby voltage to the voltage in the write selection state. Thereafter, similarly to the write operation to the memory cell on the word line WL1, the bit line to which the write memory cell is connected and the substrate node corresponding thereto are driven with the voltage in the write select state, thereby driving the source line, thereby driving the chalcogene. The data is recorded by flowing a current through the aged film. As a result, a write operation to the memory cells on the write select word line WL2 is performed. When the write operation to the word line WL2 ends, the word line WL2 is set from the write selection state to the standby state as in the case of the word line WL1 described above. In the figure, the case where the recording operation ends here is shown. After the word line WL2 is set to the standby state, all the source lines SL1, SL2,... Is set from the voltage in the write non-select state to the voltage in the standby state. At the same time, all the substrate nodes SUB1, SUB2,... Is set from the voltage in the write non-select state to the voltage in the standby state. In FIG. 21, the write cycle can be shortened when the memory cells on the word lines are sequentially rewritten as compared with FIG. 19. Furthermore, the write cycle can be shortened even in the operation of sequentially rewriting the plurality of word lines. In this case, a high speed recording operation can be realized. At the same time, since the word line and the source line are not driven for every recording cell, the power consumption can be reduced. Further, as compared with the method of Fig. 20, there is an advantage that data can be exchanged in the same word line unit as in reading.

In this embodiment, it should be noted that the word line 1101 is used for the purpose of device isolation. That is, by applying a potential of zero or negative to the electrode 1101, 1110 is given. The two elements pinched are electrically separated to ensure normal operation as a memory. As described above in the description of the present embodiment, this is a method adopted because the element formation region 7 has a structure connected in parallel with the bit line for the purpose of preventing an increase in the cell area.

Example 2

This embodiment relates to a method of realizing a phase change memory array excellent in noise immunity. For this purpose, a folded and overlapping bit line configuration (two-point memory array), which is usually used in DRAM, is adopted. The manufacturing process is almost the same as in Example 1. In addition, the element isolation by the gate electrode described in Example 1 is also used in this embodiment. Below, the manufacturing method of this embodiment is demonstrated using drawing. From element isolation formation to word line electrode formation and impurity diffusion layer formation thereon, that is, to FIGS. After forming and planarizing the interlayer film, the contact hole for the SL wire connection is opened. Further, tungsten is deposited to 200 nm for the purpose of forming the conductive plug 12, and planarized by a normal CMP process, as shown in FIG. As apparent from the comparison with FIG. 8, the plug position is different from that in the first embodiment.

Next, chalcogenide 101 is deposited by 50 nm, and tungsten 14 made of an SL line is further deposited by 100 nm. Subsequently, the laminated film of the chalcogenide 101 and tungsten 14 was processed by normal lithography and dry etching, and the top view was as shown in FIG.

Next, a bit line is formed. As in the case of forming the source line, due to the formation of the interlayer insulating film, the silicon oxide film is deposited at 500 nm and planarized by a normal CMP process. Further, for the purpose of forming the conductive plug 1201, contact openings are made, 200 nm of tungsten is deposited, and planarized by a normal CMP process, as shown in FIG. Next, 100 nm of tungsten 1401 made of BL lines is deposited. Subsequently, tungsten 1401 is processed by normal lithography and dry etching, and the top view is as shown in FIG. Thereafter, a multilayer wiring process was performed to obtain a desired semiconductor device. In the present embodiment, similarly to the first embodiment, word lines other than the selection line are electrically separated from adjacent cells by being fixed at 0 V or negative potential.

Example 3

In Examples 1 and 2, element separation was carried out by a combination of ordinary shallow groove element separation and device separation by wheeled plates. This embodiment uses only conventional shallow groove device isolation. According to this embodiment, as a result of not using the gate electric field for element isolation, the word system can be easily controlled. Hereinafter, it demonstrates using drawing. By using a P-type substrate, an N-type well is formed in the memory cell array portion. Subsequently, an element isolation region as shown in FIG. 26 is formed by a normal CMOS process. Next, in order to separate the substrate potential in the parallel direction with the bit lines, p-type impurity implantation is performed on the mask as shown in FIG. 27. 28 is a cross-sectional view of the AA section in FIG. 27 at this time. The diffusion layer must be formed deeper than the element isolation region 6, which is different from FIG. 6 of the first embodiment.

Thereafter, the same manufacturing process as in Example 1 is carried out. In the present embodiment, since the substrate potential cannot be separated by self-alignment, there is a drawback that the cell area is increased. However, since the control of the word is simplified, the design is easy and the yield is improved.

Example 4

In Example 1-3, the bit line was formed before chalcogenide processing. In this embodiment, the bit lines are formed before the chalcogenide processing. In this embodiment, since the bit line is shielded by a plug that is connected to chalcogenide, there is an effect that the capacity between the bit lines is reduced. Hereinafter, it demonstrates using drawing. In this embodiment, the element isolation formation using the gate electric field is adopted in the same manner as in the first embodiment. The formation of the word lines 11 and 1101 is the same as in the first embodiment. Next, a bit line is formed. For this reason, the elliptical plug shown in FIG. 29 is formed. Next, 100 nm of tungsten 1401 made of BL lines is deposited. Further, tungsten 1401 is processed by normal lithography and dry etching, and the top view is as shown in FIG. Further, after the interlayer insulating film is formed, a contact plug 12 made of tungsten is formed for the source line connection, as shown in FIG. 31. By making the bit line plug 1201 elliptical and shifting the arrangement of the bit line 1401, the contact plug 12 for the source line can be formed. Subsequently, 50 nm of chalcogenide 101 is deposited, and 100 nm of tungsten 14 made of an SL line is deposited thereon. Subsequently, the laminated film of chalcogenide 101 and tungsten 14 was processed by normal lithography and dry etching, and the top view was as shown in FIG. 33 is a sectional view of a portion BB in FIG. 32. As is apparent here, the bit line 1401 has a structure that is shielded by the plug electrode 12. This is effective for reducing the bit line capacity. Thereafter, a multilayer wiring process was performed to obtain a desired semiconductor device.

Example 5

In Example 1-4, chalcogenide was laminated | stacked with the source line and continued in the word line direction. In this embodiment, chalcogenide is separated for each cell to prevent disturbance caused by heat between adjacent cells. Hereinafter, it demonstrates using drawing.

Until the plug formation (FIG. 9) for source line connection, it goes through the same manufacturing process as Example 1. FIG. Subsequently, 50 nm of chalcogenide 101 is deposited, and 100 nm of tungsten 14 made of SL lines is further deposited. Subsequently, the laminated film of chalcogenide 101 and tungsten 14 was processed so that it may separate for every cell by normal lithography and dry etching, and the top view became like FIG. Next, a 200 nm silicon oxide film is deposited as the interlayer insulating film 1302, and the planarization is performed by the CMP method to expose the tungsten electrode 14. Subsequently, tungsten 15 having a thickness of 200 nm is deposited and processed by normal lithography and dry etching, and the top view thereof is as shown in FIG. Next, a bit line is formed. As in the case of forming the source line, due to the formation of the interlayer insulating film, the silicon oxide film is deposited at 500 nm and planarized by a normal CMP process. Further, contact opening is made for the purpose of forming the conductive plug 1201, 200 nm of tungsten is deposited, and planarized by a normal CMP process. Next, 100 nm of tungsten 1401 made of bit lines are deposited. Subsequently, tungsten 1401 is processed by normal lithography and dry etching, and the sectional view is as shown in FIG. Thereafter, a multilayer wiring process was performed to obtain a desired semiconductor device.

 According to the present invention, in the phase change memory composed of the selection transistor and the chalcogenide, the maximum voltage of the breakdown voltage limit can be applied to the selection transistor at the time of reading, thereby enabling high-speed reading. Further, as a result of performing the write voltage larger than the breakdown voltage of the selection transistor, a sufficient margin can be secured between the read voltage and the write voltage, and read disturb can be prevented. As a result, a highly reliable and high performance nonvolatile memory is realized. The present invention is particularly suitable for a system LSl in which a nonvolatile memory is mixed.

It is possible to realize a high-speed non-volatile mixed memory in which read disturb is prevented, and to be applied to microcomputers or IC cards, including in-vehicle use.

Claims (31)

A plurality of word lines and a plurality of first and second wirings at least one of which crosses the word lines through an insulating layer; In a semiconductor memory device having a plurality of memory cells provided at the intersection of the word line and the wiring, The memory cell includes a transistor and a storage unit connected to one of a source or a drain of the transistor, And a substrate on which a source or a drain of the transistor is formed adjacent to each other in a direction crossing the word line. The semiconductor memory device is electrically connected. The method of claim 1, And the storage section is made of a material containing at least Te (tellurium). A semiconductor memory device having a plurality of word lines formed on a semiconductor substrate, a plurality of first and second wirings at least one of which intersects the word lines via an insulating layer, and a plurality of memory cells provided at intersections of the word lines and the wirings; To The memory cell includes a memory portion formed of a transistor formed on the semiconductor substrate and a material disposed on an upper side of the transistor, the resistance of which is connected to one of a source or a drain of the transistor to be electrically variable. , The transistor provided adjacent to the word line in a direction intersecting the word line has a source and a drain formed of a diffusion layer formed on the semiconductor substrate, and the source and drain are formed in a conductive layer electrically connected. Device. The method according to claim 1 or 3, The plurality of first wirings are arranged in a direction crossing the word line and are electrically connected to the other side of the source or drain of the transistor, and the plurality of second wirings are arranged in parallel with the word line, and the A semiconductor memory device, which is electrically connected to one of a source or a drain of the transistor via a storage unit. The method of claim 4, wherein When writing data to the memory cell, the cell is selected to write data between the second wiring and the substrate on which the source or drain of the selected transistor is formed, and during reading, the cell is selected to select the word line and A data storage device for reading data between the first wirings. The method of claim 5, When writing data to the memory cell, the substrate and the second substrate are applied such that a forward voltage is applied to a junction formed between the diffusion layer where the source or the drain of the transistor is formed and the substrate. A semiconductor memory device, characterized in that a voltage is applied between wirings. The method of claim 1, When writing data to the memory cell, writing data by flowing a current from the diffusion layer of either the source or the drain of the transistor to the storage portion without flowing a current between the source and the drain of the transistor. A semiconductor memory device characterized in that. The method of claim 3, wherein When writing data to the memory cell, writing data by flowing a current from the diffusion layer of either the source or the drain of the transistor to the storage unit without passing a current between the source and the drain of the transistor. A semiconductor memory device characterized in that. The method according to claim 1 or 3, A semiconductor comprising an element isolation region for forming the transistor on the semiconductor substrate and an element isolation region for electrically separating between the transistors extending in a direction crossing the word lines, and each region being alternately arranged Memory. The method of claim 9, The depth of the conductive layer in which the diffusion layer of the source and the drain of the transistor is formed is formed shallower than the depth of the device isolation region. The method of claim 9, And the transistor formed adjacent to the element formation region is electrically separated from each other by using a word line provided between the memory cells adjacent to and parallel to the word line. The method according to any one of claims 1, 3, 7, or 8, And the memory cells are arranged in a folded overlapping bit line formed by plural sets of bit line pairs connected in parallel to one sense amplifier. Word line, bit line, A transistor disposed at an intersection of the word line and the bit line; In a semiconductor device having a memory cell consisting of a storage unit connected to the transistor, In the standby, the word line is set to the first voltage, When writing to the memory cell, the word line is set to the second voltage, When reading the memory cell, the word line is set to a third voltage, And the first voltage is higher than the second voltage and lower than the third voltage. Word line, bit line, A transistor disposed at an intersection of the word line and the bit line; In a semiconductor device having a memory cell consisting of a storage unit connected to the transistor, In the standby, the word line is set to the first voltage, When writing to the memory cell, the word line is set to the second voltage, When reading the memory cell, the word line is set to a third voltage, And the second voltage is higher than the first voltage and lower than the third voltage. A plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, A plurality of transistors each having a gate connected to the plurality of word lines; A substrate node line connected to the bit line and connected to one of a diffusion layer of a source or a drain of the plurality of transistors, A plurality of memory cells arranged at predetermined intersections of the word line and the bit line and including a storage unit connected to the transistor; In standby, the substrate node line is set to a first voltage, and when the memory cell is selected in a write operation, the substrate node line is set to a second voltage, In the writing operation, when the memory cell is not selected, the substrate node is set to a third voltage. And the first voltage is higher than the second voltage and lower than the third voltage. A plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, A memory cell disposed at a predetermined intersection of the plurality of word lines and the plurality of bit lines, the memory cell including a transistor and a storage unit connected to the transistor; A gate of the transistor is connected to one of the word lines, one of a source or a drain of the transistor is connected to one of the plurality of bit lines, Disposed in parallel to the word line, the common source line being connected to the other side of the source or the drain of the transistor, In the standby, the common source line is set to the first voltage, When the memory cell is selected in the write operation, the common source line is set to the second voltage, and when the memory cell is not selected in the write operation, the common source line is set to the third voltage and the first And the voltage is higher than the second voltage and lower than the third voltage. The method according to any one of claims 13 to 15, And the storage section comprises a material having an electrically variable resistance value. A semiconductor memory device having a plurality of word lines, a plurality of bit lines crossing the plurality of word lines, and a plurality of memory cells provided at intersections of the word lines and the bit lines.  In the read operation, data is read from a plurality of memory cells connected to one selected word line, In a write operation, data is written into a plurality of memory cells connected to one selected bit line. The method of claim 18, The substrate on which the transistors constituting the memory cell are formed are electrically connected in a direction crossing the word line. A first word line and a second word line; A first source line and a second source line, A first bit line and a second bit line crossing the first word line, the second word line, the first source line, and the second source line; A first MISFET having a gate connected to the first word line, one of the source or the drain connected to the first bit line, and one end of the gate connected to the other of the source or drain of the first MISFET; A first memory cell having a first variable resistance element whose other end is connected to the first source line; A second MISFET having a gate connected to the first word line, one of the source or the drain connected to the second bit line, and one end of the gate connected to the other of the source or drain of the second MISFET; A second memory cell having a second variable resistance element connected to one source; A third MISFET having a gate connected to the second word line, one of the source or the drain connected to the first bit line, and one end of the gate connected to the other of the source or drain of the third MISFET; A third memory cell having a third variable resistance element connected to the second source line, A fourth MISFET having a gate connected to the second word line, one of the source or the drain connected to the second bit line, and one end of the gate connected to the other of the source or drain of the fourth MISFET; A fourth memory cell having a fourth variable resistance element connected to the first source line, A first substrate node connected to the source and the drain of the first MISFET and the source and the drain of the third MISFET; Having a source and a drain of the second MISFET and a second substrate node connected to the source and the drain of the fourth MISFET, When data is written to the first memory cell, current flows through the first substrate node, the first variable resistance element, and the first source line. And a current flows in the first bit line, the first MISFET, the first variable resistance element, and the first source line when reading data from the first memory cell. The method of claim 20, In the standby of the semiconductor device, the first word line, the second word line, the first source line, the second source line, the first bit line, the second bit line, the first substrate node, and the second. A first potential is applied to the substrate node, When reading data from the first memory cell, a second potential higher than the first potential is applied to the first bit line, and a third potential higher than the first potential is then applied to the first word line. A semiconductor device, characterized in that. The method of claim 20, In the standby of the semiconductor device, the first word line, the second word line, the first source line, the second source line, the first bit line, the second bit line, the first substrate node, and the second. A first potential is applied to the substrate node, In writing to the first memory cell, a fourth potential lower than the first potential is applied to the first source line, and a fifth potential higher than the first potential is applied to the first substrate node. A semiconductor device. The method of claim 22, And a sixth potential greater than or equal to the fifth potential to the first bit line. The method of claim 22, And a seventh potential equal to or less than the fourth potential is applied to the second substrate node. The method of claim 22, And the fourth potential is applied to the first source line after the eighth potential smaller than the first potential is applied to the first word line. The method of claim 22, When the first variable resistance element is brought into a high resistance state, the fifth potential is applied to the first substrate node in a first period, When the first variable resistance element is brought into a low resistance state, a second period in which the ninth potential lower than the fifth potential and higher than the first potential is given to the first substrate node is longer than the first period. A semiconductor device. The method of claim 22, When the first variable resistance element is brought into a high resistance state, the fourth potential is applied to the first source line for a first period, And a ninth potential higher than the fourth potential and lower than the first potential is given a second period longer than the first period when the first variable resistance element is brought into a low resistance state. The method of claim 26, After writing to the first memory cell is finished, writing to the second memory cell is performed with the fourth level applied to the first source line. When the second variable resistance element is brought into a high resistance state, the fifth potential is provided to the second substrate node, in the first period, And the ninth potential is applied to the second substrate node in the second period when the second variable resistance element is brought into a low resistance state. The method of claim 27, After writing to the first memory cell is finished, writing to the third memory cell is performed with the fifth potential applied to the first substrate node. When the third variable resistance element is set to a high resistance state, the fourth potential is applied to the first source line during the first period. And the ninth potential is applied to the first source line in the second period when the third variable resistance element is brought into a low resistance state. The method of claim 22, When the first variable resistance element is set to a high resistance state, the fourth potential is applied to the first source line for a first period. When the first variable resistance element is brought into a low resistance state, a second period in which a ninth potential higher than the fourth potential is provided to the first source line is longer than the first period, When the second variable resistor is brought into a high resistance state, the fourth potential is applied to the second source line, and the fifth potential is applied to the second substrate node. When the second variable resistor is brought into a low resistance state, the ninth potential is applied to the second source line for the second period, and the fifth potential is applied to the second substrate node. Device. The method of claim 30, When writing to the second memory cell after writing to the first memory cell, an eighth potential smaller than the first potential is applied to the first word line. .

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