KR100829979B1 - System On Chip having Low Power Mode and Operating Method thereof - Google Patents

Abstract

The present invention relates to an SOC having a low power mode and a driving method thereof, comprising: a first regulator for supplying a first power source that is a main power source of the SOC, the SOC including a CPU, a DMA, a peripheral unit, and a modem; A first clock generator configured to generate a first clock which is a basic clock for driving the SOC; A first memory configured to store data input and output from the CPU, the DMA, a peripheral device, and a modem; A mode controller for operating the SOC in one of an active mode, a standby mode, and a stop mode according to the state of the SOC; And a low power mode controller configured to operate with a second clock having a lower frequency than the first clock and a second power having a voltage lower than the first power to operate the SOC in a low power mode according to the state of the SOC.

SOC, active mode, standby mode, stop mode. Low power mode

Description

SOC with low power mode and its driving method {System On Chip having Low Power Mode and Operating Method

1 is a block diagram showing a SOC according to the prior art.

Figure 2 is a block diagram schematically showing a SOC equipped with a low power mode according to the present invention.

3 is a flowchart sequentially showing a method of driving a SOC equipped with a low power mode according to the present invention.

FIG. 4 is a flowchart sequentially illustrating an operation process of each operation mode of the flowchart. FIG.

Figure 5 is a flow chart illustrating in detail the operation of the low power mode according to the present invention.

<Description of Symbols for Major Parts of Drawings>

100: SOC 110: first regulator

120: first clock generator 130: CPU

140: DMA 150: first memory

160: peripheral unit 170: modem

180: mode control unit 190: low power mode control unit

191: second regulator 192: second memory

193: operation controller 194: second clock generator

The present invention relates to an SOC having a low power mode and a driving method thereof, and more particularly, a low power mode using a clock and a power source having a lower frequency than a main clock and a main power source to further reduce the consumption of dynamic power and static power. An SOC and a driving method thereof can be reduced.

Recently, due to the development of ubiquitous, SOC (System On), which is a system that performs independent functions on one semiconductor chip such as Wireless Personal Area Network (WPAN), Ultra Wideband (UWB), or Radio Frequency Identification (RFID), etc. A chip is being researched.

The SOC includes a modem for communicating with the outside, a memory for storing data, a central processing unit (CPU) and a peripheral block (SOC), which are the main processing units of the SOC. In order to reduce power consumption, it is increasingly important to reduce power consumption.

The SOC according to the prior art will now be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a SOC according to the prior art.

First, as shown in FIG. 1, the SOC 10 according to the prior art includes a regulator 11, a clock generator 12, a CPU 13, a DMA 14, a memory 15, and a peripheral device. (16), the modem 17, the mode control unit 18 and a plurality of AND gates AND1 to AND4.

Here, the regulator 11 is connected to all the components of the SOC 10, and generates a power supply Vin for driving the SOC 10 to supply all the components of the SOC 10.

The clock generator 12 generates a clock clock for driving all the components of the SOC 10 together with the power Vin supplied from the regulator 11. Supply to the component.

The CPU 13 is a main processor for controlling the SOC 10, and a direct memory access (DMA) 14 is connected to all components of the SOC 10 to control their inputs and outputs. In addition, the peripheral device unit 16 is connected to the peripheral device of the SOC 10 and the modem 17 performs wireless communication with an external device.

At this time, the mode control unit 18, in order to reduce power consumption of the SOC 10 according to the current operating state of the SOC 10, the active mode, the standby mode (Idle Mode) and the stop mode (Stop) Mode of operation reduces power consumption.

For example, if an SOC component such as the CPU 13, the peripheral unit 16, or the modem 17 is in operation, the CPU 13 currently operates the SOC 10 in an active mode. The mode control unit 18 is selected as the active mode.

The mode controller 18 receiving the active mode selection command from the CPU 13 supplies the clock clock generated from the clock generator 12 to each component so that the SOC 10 operates in the active mode. To control.

At this time, when the CPU 13 determines that only the peripheral device unit 16 performs a certain operation and other components do not operate, the mode controller 18 selects the mode controller 18 as a standby mode.

The mode controller 18, in which the standby mode is selected, controls the first to fourth AND gates AND1 to AND4 to supply the clock only to the peripheral device unit 16. The power consumption can be reduced by shutting off the clock.

In addition, when the CPU 13 determines that all components including the peripheral device unit 16 do not operate, the mode control unit 18 selects the stop mode.

The mode controller 18 in which the stop mode is selected controls the first to fourth AND gates AND1 to AND4 to block the supply of the clock to all components of the SOC 10, and the regulator Power consumption can be reduced by supplying only the power Vin supplied from (11).

On the other hand, in the standby mode and the stop mode for reducing the power consumption, the supply of the clock (Clock) by blocking the current flowing when a plurality of switches (not shown) is switched and the current flowing at the same time they are turned on at the same time Dynamic power consumption may be reduced, but as static power is consumed due to leakage current of power Vin continuously supplied to the component, there is a problem in that the total power of the SOC 10 is consumed.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to further include a low power mode using a clock and a power supply having a lower frequency than the main clock and the main power supply to reduce the consumption of dynamic power and static power. The present invention provides an SOC and a driving method thereof.

SOC equipped with a low power mode according to the present invention for achieving the above object, the SOC including a CPU, DMA, peripheral unit and modem, the first regulator for supplying a first power source that is the main power source of the SOC; A first clock generator configured to generate a first clock which is a basic clock for driving the SOC; A first memory configured to store data input and output from the CPU, the DMA, a peripheral device, and a modem; A mode controller for operating the SOC in one of an active mode, a standby mode, and a stop mode according to the state of the SOC; And a low power mode controller configured to operate with a second clock having a lower frequency than the first clock and a second power having a voltage lower than the first power to operate the SOC in a low power mode according to the state of the SOC.

Further, in the SOC according to the present invention, the low power mode control unit, the second regulator for supplying a second power of a voltage lower than the first power supply; An operation control unit operating by receiving a second power from the second regulator, and terminating the low power mode when a predetermined time elapses or when an interrupt occurs at the time of operation of the modem; A second memory for storing respective data at the time of stopping operation of the CPU and the modem during a low power mode operation; And a second clock generator configured to generate a second clock having a frequency lower than that of the first clock.

In the SOC according to the present invention, the active mode includes a first active mode in which all of the components of the SOC are supplied by the first clock and the first power source, and the modem is the first clock and the first. And a second active mode for supplying power and supplying and operating the second clock to all components except for the modem.

In the SOC according to the present invention, the standby mode cuts off the supply of the first and second clocks to components other than the peripheral unit and the modem, and supplies only the first power, and the stop mode includes the peripheral mode. The first clock and the first power are supplied only to the timer provided in the device, and only the first power is supplied to the components other than the timer and the supply of the first and second clocks is cut off.

In particular, in the SOC according to the present invention, in the low power mode, the CPU and the modem stop operation, and the DMA operates in the low power mode after storing the data at the point of time when the CPU and modem stops operation in the second memory. Characterized in that.

In addition, a method of driving an SOC equipped with a low power mode according to the present invention for achieving the above object, in the SOC including a CPU, DMA, peripheral unit, modem, a) the SOC is active mode, standby mode, Confirming whether the operation mode is one of a stop mode and a low power mode; b) controlling the supply of the first clock which is the basic clock of the SOC, the second clock having a lower frequency than the first clock, and the first power which is the main power of the SOC in step a) to execute the mode identified in step a). Doing; And c) canceling the current operation mode and resetting the operation mode of the SOC when the mode release signal is generated.

In addition, in the SOC driving method according to the present invention, if the operation mode of the SOC identified in step a) is the active mode, checking whether the active mode is the first active mode; When the identified mode is a first active mode, executing a first active mode by supplying the first clock and the first power to all components; And canceling a current first active mode when a mode conversion signal is generated during the execution of the first active mode.

In addition, in the SOC driving method according to the present invention, if the identified mode is not the first active mode, selecting a second active mode; After the selection of the second active mode, supplying a first clock only to the modem and supplying the first power and the second clock to components other than the modem to execute a second active mode; And canceling the current second active mode when an interrupt is generated from outside or a timeout signal is generated.

In the SOC driving method according to the present invention, when the operation mode of the SOC identified in the step a) is a standby mode, the first clock and the first power are supplied only to the peripheral unit and the modem, and the peripheral Interrupting the supply of the first clock and supplying only the first power to components other than an apparatus unit and a modem to execute a standby mode; And terminating the current standby mode when an interrupt is generated from outside or a timeout signal is generated.

In addition, in the SOC driving method according to the present invention, in the stop mode of the SOC identified in step a), the first clock and the first power are supplied only to the peripheral unit, and the components except the peripheral unit are excluded. Interrupting the supply of the first clock and supplying only the first power to execute the stop mode; And when the timeout signal is generated, canceling the current standby mode.

In addition, in the method of driving an SOC according to the present invention, when the operation mode of the SOC identified in the step a) is a low power mode, the first and second components of the SOC except for the low power mode control unit for driving the SOC to the low power mode. Executing a low power mode by cutting off the second clock and the first power supply; And terminating the current low power mode when an interrupt is generated from outside or a timeout signal is generated.

Particularly, in the SOC driving method according to the present invention, when the low power mode is selected, the SOC is configured to stop the operation of the SOC and to provide the low power mode controller with data at the time of stopping the operation of the CPU and the modem. 2 storing in memory; Stopping the operation of the first regulator for outputting the first power after storing the data in a second memory; After the operation of the first regulator is stopped, a second clock and a second power having a lower voltage than the first power supply are supplied to the low power mode controller, and the first and second clocks are provided to components other than the low power mode controller. Executing a low power mode by shutting off the first power; Stopping an operation of the CPU when an interrupt or timeout signal is generated from the outside during execution of the low power mode; Re-operating the first regulator, transferring the data at the time when operation of the modem and the CPU are stopped in the second memory to the modem and the CPU, and then operating the CPU; And terminating the low power mode.

The above objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, whereby those skilled in the art may easily implement the technical idea of the present invention. There will be.

In addition, in describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

Next, the SOC with the low power mode according to the present invention will be described in more detail with reference to the accompanying drawings.

2 is a block diagram schematically illustrating an SOC equipped with a low power mode according to the present invention.

First, as shown in FIG. 2, the SOC 100 according to the present invention includes a first regulator 110, a first clock generator 120, a CPU 130, a DMA 140, and a first memory ( 150, the peripheral device 160, the modem 170, the mode controller 180, and the low power mode controller 190.

Here, the first regulator 110 generates the first power source Vin1, which is a main power source for driving the SOC 100 fmf, and supplies the first power source Vin1 to all components of the SOC 100, thereby supplying the SOC 100. Drive it.

The first clock generator 120 generates the first clock Clock1 for driving the SOC 100 together with the first power source Vin1 supplied from the first regulator 110 to generate the SOC ( Supply to all components of 100). In this case, the first clock Clock1 has a frequency of several tens of MHz to drive the SOC 100.

The CPU 130 is a main processor for controlling the SOC 100, and the DMA 140 is connected to all components of the SOC 100 to control their inputs and outputs. In addition, the peripheral unit 160 is connected to the peripheral device of the SOC 100, the modem 170 is in wireless communication with an external device, the first memory 150 is the data of these components each designated Save to the area.

In this case, the mode controller 180 may select one of an operation mode of an active mode, a standby mode, or a stop mode in order to reduce power consumption of the SOC 100 according to a current operating state of the SOC 100. By selecting and controlling the component, power consumption can be reduced.

In addition, the low power mode controller 190 includes a second regulator 191, a second memory 192, an operation controller 193, and a second clock generator 194, and controls power of the SOC 100. The SOC is operated in a low power mode to minimize the consumption.

The second regulator 191 of the low power mode controller 190 generates a second power source Vin2 having a voltage lower than that of the first power source Vin1 supplied from the first regulator 110 to operate in the low power mode operation. The second memory 192, the operation controller 193, and the second clock generator 194, which are components of the low power mode controller 190, are supplied to the second memory 192. In this case, the reason why the second regulator 191 generates the second power source Vin2 having a voltage lower than that of the first power source Vin1 is that the SOC 100 is static when the SOC 100 operates in a low power mode. In order to reduce power consumption as much as possible, by generating and supplying a second power source Vin2 having a lower voltage than the first power source, there is an advantage that the dynamic power consumption can be reduced to a minimum.

When the SOC 100 operates in the low power mode, the second memory 192 stores data when the CPU 130 and the modem 170 stop operating, and stores the capacity of the second memory 192. Since only the data of the CPU 130 and the modem 170 is stored, has a smaller capacity than the first memory 150.

When the SOC 100 operates in the low power mode, the operation control unit 193 has a timer (not shown) internally, and when the predetermined time passes, the operation controller 193 terminates the low power mode.

When the SOC 100 operates in the second active mode among the active modes, the second clock generator 194 has a second frequency having a lower frequency than that of the first clock Clock1 in a non-operating component. The clock Clock2 is generated and supplied. In this case, the second clock (Clock2) generates a frequency of several KHz lower than the frequency of several tens of MHz, thereby reducing the dynamic power consumption of the SOC (100) than when supplying a high frequency of the first clock (Clock1). There is an advantage.

Here, the MUX (Multiplexer) illustrated in FIG. 2 is selected from among the first clock Clock1 supplied from the first clock generator 120 and the second clock Clock2 supplied from the second clock generator 194. Select and supply either clock.

Hereinafter, an operation process of each operation mode of the SOC 100 having the above configuration will be described.

First, the CPU 130 executes an active mode when it is determined that the SOC 100 is in normal operation. The first and second active modes may be used to reduce the dynamic power consumption generated when the active mode is executed. The mode controller 180 and the low power mode controller 190 are controlled to operate in a divided mode.

At this time, when the operation mode is selected as the first active mode in order to operate the SOC 100 normally, the CPU 130 transmits the first active mode to the mode controller 180 through the BUS connected to the component. Pass the action command.

The mode controller 180 which has received the first active mode operation command supplies the first clock and the first power Vin1 to the components of the SOC 100 through the BUS to supply the SOC 100. Control to perform this normal operation.

If the operation mode of the SOC 100 is selected as the second active mode, the CPU 130 supplies the first power Vin1 to all components of the SOC 100 through the BUS, The modem 170 which operates at a high speed by controlling the second clock Clock2 generated by the first clock Clock1 and the second clock generator 194 of the low power mode controller 190 through the MUX is provided. The second active mode is performed by supplying one clock Clock1 and supplying a second clock Clock2 to other components.

In this case, by performing the second active mode using the second clock Clock2 having the low frequency, there is an advantage of reducing the dynamic power consumption than the first active mode using the first clock Clock1. .

When the operation mode of the SOC 100 is selected as the standby mode, the CPU 130 transmits a first clock (a clock) to the peripheral unit 160 and the modem 170 among the components of the SOC 100 through the BUS. Supplying the clock1 and the first power (Vin1), and supplies only the first power (Vin1) to the components other than this and cut off the supply of the first clock (Clock1) to reduce the consumption of the dynamic power consumed by them There is an advantage to this.

In addition, when the operation mode of the SOC 100 is selected as the stop mode, the CPU 130 is a timer (not shown) of the peripheral unit 160 among the components of the SOC 100 through the BUS. Only the first clock (Clock1) and the first power (Vin1) is supplied to, except for the components other than this by supplying only the first power (Vin1) and the supply of the first clock (Clock1) more easier than the standby mode It is possible to reduce the consumption of dynamic power generated in the SOC.

In particular, when the operation mode of the SOC 100 is selected as the low power mode, the CPU 130 applies all components except the low power mode controller 190 among the components of the SOC 100 through the BUS. The supply of the first clock Clock1 and the first power source Vin1 is cut off to completely stop their operation.

At this time, during the low power mode operation, all components except for the DMA 140 stop operation, and the DMA 140 backs up all data at the operation stop point of the CPU 130 and the modem 170 (Back- up) to store in the second memory 192 of the low power mode controller 190.

The first clock (Clock1) and the first power supplied to all components including the DMA 140 after storing the data at the operation stop time of the CPU 130 and the modem 170 in the second memory 192 By blocking Vin1, their operation is stopped.

Then, when the second memory 192, the operation controller 193, and the second clock generator 194 are operated through the second power source Vin2 of the low voltage supplied from the second regulator 191, the The operation control unit 193 includes a timer (not shown) therein, so that a time-out or interrupt occurs when a predetermined time in the low power mode passes or when the modem 170 operates. Generated to terminate the low power mode.

When the timeout or interrupt occurs, the CPU 130 and the modem 170 are stopped and the first regulator 110 is operated to allow all components to operate. In this case, the DMA 140 transfers data of the operation stop point of the CPU 130 and the modem 170 stored in the second memory 192 to them, and after completion of the transfer, the CPU 130 and the modem. The operation stop of 170 is terminated so that they can operate from the time of operation.

Accordingly, the SOC 100 according to the present invention cuts off the supply of the first clock Clock1 and the first power Vin that are supplied to the components of the SOC 100 except for the low power mode controller 190. In addition, since the low voltage and low frequency are driven using the second power source Vin2 and the second clock clock2, there is an advantage of reducing static power consumption in which leakage current is generated.

Next, a method of driving an SOC equipped with a low power mode according to the present invention will be described in detail with reference to FIGS. 3 to 5.

3 is a flowchart showing a method of driving an SOC with a low power mode according to the present invention in sequence, FIG. 4 is a flowchart showing an operation process of each operation mode in the flowchart in sequence, and FIG. 5 is according to the present invention. A flowchart illustrating the operation of the low power mode in detail.

First, as shown in FIG. 3, the SOC driving method according to the present invention checks whether the SOC operates in any one of an active mode, a standby mode, a stop mode, and a low power mode (S201).

According to the operation mode identified in step S201, the supply of the first clock, which is the basic clock of the SOC, the second clock having a lower frequency than the first clock, and the first power, which is the main power supply of the SOC, is executed to execute the checked mode. (S202).

When the mode cancel signal is generated during the mode execution, the current mode is canceled and the operation mode of the SOC is reset (S203).

Hereinafter, an SOC operating in the same manner as described above will be described in more detail with reference to FIGS. 3 and 4.

First, as shown in FIG. 4, the current operation mode of the SOC is checked to determine whether the current operation mode corresponds to an operation mode among an active mode, a standby mode, a stop mode, and a low power mode (S310).

If the operation mode identified in step S310 is the active mode, it is checked whether the operation mode of the SOC is the first active mode or the second active mode (S320, S321).

In this case, when the mode identified in step S321 is the first active mode, the first active mode is executed by supplying a first clock and a first power source to the components of the SOC (S321 and S322).

When a signal for changing the mode is applied during the execution of the first active mode, the current mode is canceled and the operation mode of the SOC is reset (S323 and S360).

When the mode identified in step S321 is the second active mode, the first clock and the first power are supplied only to the modems among the components of the SOC, and the second frequency having a lower frequency than the first clock is provided to the components except the modem. The clock and the first power supply are supplied to execute the second active mode (S325 and S326).

In the step S326, when an interrupt occurs or a timeout occurs during the execution of the second active mode, the second active mode which is the current operation mode is canceled and the operation modes of the SOC are reset (S327 and S360).

In operation S310, when the current operation mode of the SOC is a standby mode, the first clock and the first power are supplied only to the peripheral unit and the modem among the components of the SOC, and only the first power is supplied to the other components. Operation of the standby mode is cut off by supplying one clock to reduce dynamic power consumption of the SOC (S330, S331, and S332).

When a signal for mode conversion is generated during operation in the standby mode, the current mode is canceled and the operation mode of the SOC is reset (S333 and S360).

In addition, when the current operation mode of the SOC is the stop mode in operation S310, the first clock and the first power are supplied only to the timer of the peripheral device among the components of the SOC, and the first power is supplied to all components except the SOC. As only the first component is supplied and operated in the stop mode, the unused component receives only the first power, thereby reducing dynamic power consumption according to the first clock (S340, S341, and S342).

When a timeout signal is generated from the timer of the peripheral device unit during operation in the stop mode, the stop mode is canceled and the operation modes of the SOC are reset (S343 and S360).

However, since the first power is supplied even during the stop mode operation, static power consumption due to leakage current of the SOC is generated. Therefore, in order to prevent this, when the stop mode continues, the operation mode of the SOC is selected as the low power mode (S350).

The low power mode stops the operation of the first regulator and the first clock generator of the SOC to block their supply, and operates only the low power mode controller by operating the second regulator and the second clock generator of the low power mode controller. In this case, since the second regulator generates a lower voltage than the first power generated from the first regulator, static power consumption due to leakage current can be reduced, and the second clock generator has a lower frequency than that of the first clock generator. Since the second clock is generated, the dynamic power consumption due to the switching current consumption may be reduced.

If an interruption or timeout occurs during the operation in the low power mode, the low power mode is canceled and the operation mode of the SOC is reset (S353 and S360).

The operation of the low power mode will be described in more detail with reference to FIG. 5. First, when the operation mode of the SOC is selected as the low power mode, the operation of the SOC is stopped (S401).

When the operation of the SOC is stopped, data at the time of stopping operation of the CPU and the modem among the components of the SOC is stored in the second memory of the low power mode (S402. S403). In this case, the reason for storing the data at the operation stop time of the CPU and modem is that, when the low power mode is terminated and reactivates, the data at the operation stop time is temporarily stored in order to operate them from the time after the operation stops. will be.

Then, the operation of the first regulator for generating the first power is stopped to execute the low power mode (S404 and S405).

If an interruption or timeout occurs during execution of the low power mode, the operation of the CPU and modem is stopped (S406 and S407). The reason for this is that if they operate immediately after the low-power mode is terminated, their operation is stopped because they do not operate after the data stored in the second memory but perform other operations.

After stopping the operation of the CPU and the modem, the first regulator is operated to supply first power to all components of the SOC (S408).

Subsequently, data at the time when operation stops of the CPU and the modem stored in the second memory are transferred back to the CPU and the modem (S409 and S410).

When the CPU and the modem are operated after transferring data, the CPU and the modem operate after the operation time through the data at the operation stop time, and thus may operate in the same manner as the operation after the time when the low power mode is executed ( S411).

Then, when all the components of the SOC is operated to terminate the low power mode (S412).

Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and various substitutions, modifications, and changes within the scope without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It will be appreciated that such substitutions, changes, and the like should be considered to be within the scope of the following claims.

As described above, the SOC equipped with a low power mode and a driving method thereof according to the present invention cut off the supply of the first clock, the main clock, and the first power, the main power, and the lower frequency and lower than the first clock and the first power. A low power mode using the second clock and the second power source of the power supply is further provided, thereby reducing the consumption of dynamic power and static power.

Claims (13)

In an SOC including a CPU, a DMA, a peripheral unit and a modem, A first regulator for supplying a first power source that is a main power source of the SOC; A first clock generator configured to generate a first clock which is a basic clock for driving the SOC; A first memory configured to store data input and output from the CPU, the DMA, a peripheral device, and a modem; A mode controller for operating the SOC in one of an active mode, a standby mode, and a stop mode according to the state of the SOC; And And a low power mode controller configured to operate with a second clock having a lower frequency than the first clock and a second power having a voltage lower than the first power to operate the SOC in a low power mode according to the state of the SOC. The low power mode control unit, A second regulator for supplying a second power supply having a lower voltage than the first power supply; An operation control unit operating by receiving a second power from the second regulator, and terminating the low power mode when a predetermined time elapses or when an interrupt occurs at the time of operation of the modem; A second memory for storing respective data at the time of stopping operation of the CPU and the modem during a low power mode operation; And A second clock generator configured to generate a second clock having a frequency lower than that of the first clock; SOC equipped with a low power mode, characterized in that it comprises a. delete The method of claim 1, The active mode is, A first active mode configured to supply and operate the first clock and the first power to all components of the SOC; And a second active mode for supplying the first clock and the first power only to the modem, and supplying and operating the second clock to all components except the modem. The method of claim 1, The standby mode is a SOC having a low power mode, characterized in that the supply of the first power and the first clock and the second clock block to the components except the peripheral unit and the modem. The method of claim 1, In the stop mode, the first clock and the first power are supplied only to a timer provided in the peripheral device, and only the first power is supplied to the components except for the above, and the supply of the first and second clocks is blocked. SOC equipped with a low power mode. The method of claim 1, In the low power mode, the CPU and the modem stop operation, and the DMA operates in a low power mode after storing the data at the operation stop time of the CPU and the modem in a second memory. SOC. In an SOC including a CPU, a DMA, a peripheral unit, and a modem, a) checking whether the SOC operates in one of an active mode, a standby mode, a stop mode, or a low power mode; b) controlling the supply of the first clock which is the basic clock of the SOC, the second clock having a lower frequency than the first clock, and the first power which is the main power of the SOC in step a) to execute the mode identified in step a). Doing; And c) canceling the current operation mode and resetting the operation mode of the SOC when the mode release signal is generated; Selecting a second active mode if the mode identified in step a) is not the first active mode; Executing a second active mode by supplying a first clock only to the modem after selecting the second active mode and supplying the first power and the second clock to components other than the modem; And Canceling the current second active mode when an interrupt is generated from outside or a timeout signal is generated; SOC driving method provided with a low power mode, characterized in that it comprises a. delete delete The method of claim 7, wherein When the operation mode of the SOC identified in step a) is a standby mode, the first clock and the first power supply are supplied only to the peripheral device and the modem, and the first clock is supplied to components other than the peripheral device and the modem. Interrupting the supply of power and supplying only the first power to execute a standby mode; And Canceling the current standby mode when an interrupt is generated from outside or a timeout signal is generated; SOC driving method provided with a low power mode, characterized in that it comprises a. The method of claim 7, wherein In the stop mode of the SOC identified in step a), the first clock and the first power supply are supplied only to the peripheral device, and the supply of the first clock is cut off to the components except the peripheral device and the first clock is blocked. Executing a stop mode by supplying only power; And When the timeout signal is generated, canceling the current standby mode; SOC driving method provided with a low power mode, characterized in that it comprises a. The method of claim 7, wherein When the operation mode of the SOC identified in the step a) is a low power mode, the first and second clocks and the first power supply are cut off to components except for the low power mode controller for driving the SOC to the low power mode. Executing; And Canceling the current low power mode when an interrupt is generated externally or a timeout signal is generated; SOC driving method provided with a low power mode, characterized in that it comprises a. The method of claim 12, The SOC, when the low power mode is selected, after stopping the operation of the SOC, storing the data at the time point at which the CPU and the modem are stopped in a second memory provided in the low power mode controller; Stopping the operation of the first regulator for outputting the first power after storing the data in a second memory; After the operation of the first regulator is stopped, a second clock and a second power having a lower voltage than the first power supply are supplied to the low power mode controller, and the first and second clocks are provided to components other than the low power mode controller. Executing a low power mode by shutting off the first power; Stopping an operation of the CPU when an interrupt or timeout signal is generated from the outside during execution of the low power mode; Re-operating the first regulator, transferring the data at the time when operation of the modem and the CPU are stopped in the second memory to the modem and the CPU, and then operating the CPU; And Terminating the low power mode; SOC driving method provided with a low power mode, characterized in that it comprises a.

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