KR100828890B1 - Method for fabricating microstructure - Google Patents

Abstract

The method for manufacturing the microstructures having the thin portions T1 to T3 includes the first conductor layer 11 and the second conductor layer 12 having a thickness corresponding to the thickness of the thin portions T1 to T3. In-plane direction of the said 2nd conductor layer 12 in the 2nd conductor layer 12 by performing a 1st etching process with respect to the material board | substrate which consists of a laminated structure formed in the 1st conductor layer 11 side. By the process for forming the free thin parts T1'-T3 'which have a pair of side surface spaced apart and contacting the 1st conductor layer 11, and the 2nd etching process by the side of the 1st conductor layer 11, In the 1st conductor layer 11, the process of removing the part which contact | connects the free thin parts T1'-T3 ', and forming a thin part is included.

Microstructures, Thin Sections, Conductor Layers, Laminated Structures, Micromachining

Description

Method for producing a microstructure {METHOD FOR FABRICATING MICROSTRUCTURE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing microstructures and microstructures such as micromirror elements, acceleration sensor elements, angular velocity sensor elements, and vibration elements produced by micromachining techniques.

Recently, in various technical fields, the application of devices having a microstructure formed by micromachining technology has been planned. For example, in the field of optical communication technology, minute micromirror elements having a light reflection function have attracted attention.

In optical communication, an optical signal is transmitted using an optical fiber as a medium, and so-called optical switching devices are generally used in order to switch the transmission path of the optical signal from one fiber to another. Examples of the characteristics required for the optical switching device in achieving good optical communication include high capacity, high speed, high reliability, and the like in the switching operation. From these viewpoints, the expectation that the optical switching device incorporates the micromirror element manufactured by the micromachining technique is increasing. According to the micromirror element, a switching process can be performed as it is without converting an optical signal into an electrical signal between the optical transmission path on the input side and the optical transmission path on the output side in the optical switching device, thereby obtaining the above characteristics. Because it is suitable.

The micromirror element has a mirror surface for reflecting light, and can change the reflection direction of light by fluctuation of the mirror surface. BACKGROUND OF THE INVENTION An electrostatically driven micro-mirror element that uses electrostatic force to swing a mirror surface has been adopted in many optical devices. The electrostatically driven micromirror elements can be broadly classified into two types: micromirror elements produced by so-called surface micromachining techniques and micromirror elements produced by so-called bulk micromachining techniques.

In the surface micromachining technique, a material thin film corresponding to each component part on a substrate is processed into a desired pattern, and the patterns are sequentially stacked to remove each part constituting an element such as a support, a mirror surface, and an electrode part or later. Form a sacrificial layer.

On the other hand, in a bulk micromachining technique, a support body, a mirror part, etc. are shape | molded to a desired shape by etching a material substrate itself, and a mirror surface or an electrode is thin-film-formed as needed. About a bulk micromachining technique, it is disclosed by Unexamined-Japanese-Patent No. 10-190007, Unexamined-Japanese-Patent No. 10-270714, and Unexamined-Japanese-Patent No. 2000-31502, for example.

One of the technical matters required for the micromirror element is one having a high plan view of the mirror surface responsible for light reflection. However, according to the surface micromachining technique, since the mirror surface finally formed is thin, it is easy to bend the mirror surface, and it is limited that the length of one side is about 50 micrometers in the size of a mirror surface.

On the other hand, according to the bulk micromachining technique, since a relatively thick material substrate itself is etched by an etching technique to form a mirror portion, and a mirror surface is provided on this mirror portion, even if the mirror surface of a larger area is used, the rigidity is high. It can be secured. As a result, it is possible to form a mirror surface having a sufficiently high optical plan view. Therefore, bulk micromachining techniques are widely employed in the manufacture of micromirror elements in which a mirror surface having a length of one side of 100 mu m or more is required.

32 is a partially omitted exploded perspective view of the micromirror element 400 as an example of a conventional electrostatically driven micromirror element produced by a bulk micromachining technique. The micro mirror device 400 has a structure in which a mirror substrate 410 and a base substrate 420 are stacked through spacers (not shown). The mirror substrate 410 has a mirror portion 411, an inner frame 412, and an outer frame 413. The mirror portion 411 and the inner frame 412 are connected by a pair of torsion bars 414. The inner frame 412 and the outer frame 413 are connected by a pair of torsion bars 415. The pair of torsion bars 414 define the axis of rotation of the mirror portion 411 relative to the inner frame 412. The pair of torsion bars 415 define the center of rotation of the inner frame 412 relative to the outer frame 413 and the accompanying mirror portion 411.

A pair of flat plate electrodes 411a and 411b are provided on the rear surface of the mirror portion 411, and a mirror surface (not shown) for reflecting light is provided on the surface thereof. In addition, a pair of flat plate electrodes 412a and 412b is provided on the rear surface of the inner frame 412.

The base substrate 420 is provided with the flat plate electrodes 420a and 420b so as to face the flat plate electrodes 411a and 411b of the mirror portion 411, and the flat plate electrodes 412a and 412b of the inner frame 412. The flat plate electrodes 420c and 420d are provided. In a conventional micromirror element, as a driving method, a method of generating a constant power using such a flat plate electrode is often adopted.

In such a configuration, for example, when the plate electrode 420a of the base substrate 420 is negatively charged while the plate electrode 411a of the mirror portion 411 is positively charged, Electrostatic attraction is generated between the plate electrode 411a and the plate electrode 420a, and the mirror part 411 swings in the direction of arrow M1, twisting a pair of torsion bar 414. FIG.

On the other hand, for example, when the plate electrode 420c of the base substrate 420 is negatively charged while the plate electrode 412a of the inner frame 412 is positively charged, the plate electrode 412a and the plate electrode An electrostatic attraction occurs between 420c and the inner frame 412 swings in the direction of arrow M2 while twisting a pair of torsion bars 415 with the mirror portion 411. FIG. 33 shows a state in which the inner frame 412 and the mirror portion 411 accompanying it are displaced to the inclination angle θ with respect to the outer frame 413 by this rotational drive.

In the flat electrode structure employed in the micromirror element 400, the mirror part provided with the flat plate electrodes 411a and 411b by the flat plate electrodes 420a, 420b, 420c, and 420d provided in the base substrate 420 ( Since driving is performed such that the inner frame 412 including the 411 or the flat plate electrodes 412a and 412b is drawn in, a pull-in voltage exists with respect to the voltage applied between the electrodes. . When a voltage equal to or greater than the pulling voltage is applied between the predetermined electrodes, a phenomenon in which the approach speed of the mirror portion 411 or the inner frame 412 to the base substrate 420 increases rapidly during rotational driving, causes the mirror portion ( There arises a problem that the inclination angle of 411 cannot be properly controlled. This problem is especially noticeable when a large inclination angle (more than about 5 °) is achieved, i.e., the degree of warp of the torsion bar is large.

In order to solve this problem, instead of the flat electrode structure, a method of driving the micromirror element by a comb-shaped electrode structure has been proposed. 34 is a partially omitted perspective view of a conventional micromirror element 500 employing a comb-shaped electrode structure.

The micromirror element 500 has a mirror portion 510 provided with a mirror surface (not shown) on an upper surface or a lower surface, an inner frame 520, and an outer frame 530 (some of which are omitted). It is formed integrally. Specifically, the mirror portion 510 is provided with a pair of comb-shaped electrodes 510a and 510b extending outward from the pair of parallel side surfaces. The inner frame 520 has a pair of comb-shaped electrodes 520a, 520b extending inwardly corresponding to the comb-shaped electrodes 510a, 510b, and a pair of comb-shaped electrodes 520c, 520d. It extends outward and is formed. In the outer frame 530, a pair of comb-shaped electrodes 530a and 530b extend inwardly to correspond to the comb-shaped electrodes 520c and 520d. In addition, the mirror unit 510 and the inner frame 520 are connected by a pair of torsion bars 540, and the inner frame 520 and the outer frame 530 are connected by a pair of torsion bars 550. It is connected. The pair of torsion bars 540 define the axis of rotation of the mirror portion 510 relative to the inner frame 520, and the pair of torsion bars 550 have the inner frame 520 relative to the outer frame 530. ) And the associated axis of rotation of the mirror unit 510 is defined.

In the micro-mirror element 500 of such a structure, when a set of comb-shaped electrodes, for example, the comb-shaped electrode 510a and the comb-shaped electrode 520a, which are provided in close proximity to generate electrostatic power are not applied, As shown to FIG. 35A, it is in the state isolate | separated into two stages of top and bottom. At the time of voltage application, as shown in FIG. 35B, the comb-shaped electrode 520a draws in the comb-shaped electrode 510a, and the mirror part 510 is driven by this. More specifically, in FIG. 34, when the comb-shaped electrode 510a is positively charged and the comb-shaped electrode 520a is negatively charged, for example, the mirror unit 510 has a pair of torsions. Twist the bar 540 in the direction of M3. On the other hand, when the comb-shaped electrode 520c is positively charged and the comb-shaped electrode 530a is negatively charged, the inner frame 520 swings in the direction of M4 while twisting a pair of torsion bars 550. do.

According to the comb-shaped electrode structure, the direction of action of the electrostatic force generated between the electrodes is set to be substantially orthogonal to the swinging direction of the mirror portion 510. Therefore, at the time of driving of the mirror part 510, the distance between electrodes in the electrostatic force action direction is substantially constant, and the contact of the comb-tooth-shaped electrode by pulling in hardly arises. Therefore, it becomes possible to achieve a large inclination angle with respect to the mirror part 510 suitably.

In the micro-mirror element 500, since the comb-shaped (electrode) is displaced with the rotation operation of the mirror part 510 and the internal frame 520, the inclination angles of the mirror part 510 and the internal frame 520 are inclined. It is necessary to form a comb-shaped electrode having a sufficient thickness to fit. For example, when the length D of the fuselage 511 of the mirror part 510 is 1 mm, the shaft center defined by the pair of torsion bars 540 with respect to the inner frame 520 is used for the mirror part 510. When inclined around 5 °, one side of the fuselage end 511 'sinks 44 占 퐉. Therefore, the thickness T of the comb-shaped electrodes 510a and 510b formed in the mirror part 510 needs to be at least 44 micrometers or more.

On the other hand, from the viewpoint of obtaining a large inclination angle by a small applied voltage, the torsion bars 540 and 550 having torsional resistance are preferably formed thinly. However, in the conventional micromirror device 500, the torsion bars 540 and 550 are formed to have the same thickness as that of the material substrate constituting the mirror 510, the inner frame 520, and the outer frame 530. For example, as described above, when the thickness T of the comb-shaped electrodes 510a and 510b is designed to be 44 μm or more, the thickness of the torsion bars 540 and 550 is also 44 μm or more together with the mirror portion 510. Throw it away. With such thick torsion bars 540 and 550, the electrostatic force which must be generated between the comb-shaped electrodes in order to twist them becomes large, and as a result, the driving voltage also becomes large. In the related art, the torsion resistance of the torsion bars 540 and 550 is adjusted by changing the width dimensions of the torsion bars 540 and 550. However, only the design change in the width direction is sufficient to set an appropriate torsion resistance. Many times you do not.

As described above, in the microstructure produced by the bulk micromachining technique, different thicknesses or heights may be required in various structural portions etched in the material substrate. However, in the conventional bulk micromachining technique, it is difficult to form a thin structure, that is, a thin portion, which is integrally connected to a thick structure, that is, a thick portion, with high precision with respect to the thickness dimension.

An object of the present invention is to provide a method for producing a microstructure having a thin portion formed with high precision with respect to a thickness dimension, and a microstructure manufactured accordingly.

According to a first aspect of the present invention, a method for manufacturing a microstructure having thin parts is provided. This manufacturing method performs a 1st etching process from the side of a 1st conductor layer with respect to the material substrate containing the laminated structure which consists of a 2nd conductor layer which has a thickness corresponded to the thickness of a 1st conductor layer and a thin part, In the second conductor layer, a step for forming a free thin portion having a pair of side surfaces spaced apart in the in-plane direction of the second conductor layer and in contact with the first conductor layer, and a second etching from the side of the first conductor layer. The process includes a step of forming a thin portion by removing a portion of the first conductor layer in contact with the pre-thin parts.

In the first aspect, preferably, the first etching treatment is anisotropic reactive ion etching that exhibits a higher etching rate in the thickness direction than the in-plane direction in the first conductor layer and the second conductor layer.

Preferably, the second etching treatment is a wet etching showing a higher etching rate in the first conductor layer than the second conductor layer. In this case, preferably, the first conductor layer and the second conductor layer are made of a conductive silicon material, and the dopant concentration in the second conductor layer is higher than the dopant concentration in the first conductor layer.

Preferably, the first conductor layer is made of a silicon material having a (110) plane extending in the in-plane direction of the first conductor layer and a crystal structure having two (111) planes orthogonal to the (110) plane. .

Preferably, the first conductor layer is made of a silicon material having a crystal structure having a (110) or (100) plane extending in the in-plane direction of the first conductor layer.

According to a second aspect of the present invention, another method for producing a microstructure having a thin portion is provided. The manufacturing method includes a first conductor layer, a second conductor layer having a thickness corresponding to the thickness of the thin portion, and contacting the first conductor layer, a third conductor layer, and the second conductor layer and the third conductor layer. A material substrate including a laminated structure composed of an insulating layer corresponds to a portion of the first mask pattern having a portion for masking a portion to be processed into a thick portion in the material substrate and a portion processed into a thin portion in the second conductor layer. After performing the 1st etching process from the side of a 1st conductor layer through the 2nd mask pattern for masking a part of 1st conductor layer, and removing a 2nd mask pattern, it is a 1st thing with respect to a material substrate By performing a second etching process from the side of the first conductor layer through the mask pattern, the first conductor layer and the insulating layer have a pair of side surfaces spaced apart in the in-plane direction of the second conductor layer in the second conductor layer. Free to touch The insulating layer by a process for forming a meat part, the process of removing the site | part contacting a free thin part in a 1st conductor layer by the 3rd etching process from the side of a 1st conductor layer, and a 4th etching process And a step for removing the portion in contact with the free thin portion to form the thin portion.

In the second aspect of the present invention, preferably, the second etching treatment is anisotropic reactive ion etching which exhibits a higher etching rate in the thickness direction than the in-plane direction in the first conductor layer and the second conductor layer.

Preferably, the third etching treatment is a wet etching showing a higher etching rate in the first conductor layer than the second conductor layer. In this case, preferably, the first conductor layer and the second conductor layer are made of a conductive silicon material, and the dopant concentration in the second conductor layer is higher than the dopant concentration in the first conductor layer.

Preferably, the first conductor layer has a crystal structure having (110) planes extending in the in-plane direction of the first conductor layer and two (111) planes perpendicular to and intersecting with the (110) planes. It is made of a silicon material, and at least part of the contour of the first mask pattern is along the two (111) planes.

Preferably, the third conductor layer has two (110) planes extending in the in-plane direction of the third conductor layer and two parallel to and intersecting with either one of the two (111) planes in the first conductor layer. It is made of a silicon material having a crystal structure having four (111) planes.

Preferably, the process of forming the hole which penetrates a 1st conductor layer, a 2nd conductor layer, and an insulating layer and reaches a 3rd conductor layer by the etching process from the side of a 1st conductor layer, and conducts the said hole The method further includes forming a conductive contact by filling the material.

According to a third aspect of the present invention, a method for manufacturing a microstructure having a first thin portion and a second thin portion is provided. This manufacturing method includes a first conductor layer, a second conductor layer having a thickness corresponding to the thickness of the first thin portion, and a third conductor layer contacting the first conductor layer, and a third conductor having a thickness corresponding to the thickness of the second thin portion. A thick substrate is formed on the material substrate with respect to the material substrate including a layer, a laminated structure including a fourth conductor layer in contact with the third conductor layer, and an insulating layer between the second conductor layer and the third conductor layer. Through a first mask pattern having a portion for masking a part to be processed into a part and a second mask pattern for masking a part of the first conductor layer corresponding to a part to be processed into a first thin part in the second conductor layer. In the third mask pattern and the third conductor layer having a step for performing a first etching treatment from the side of the first conductor layer, and a portion for masking a portion to be processed into a thick portion in the material substrate with respect to the material substrate. Processing into the second thin part After the process of performing a 2nd etching process from the side of a 4th conductor layer through the 4th mask pattern for masking a part of 4th conductor layer corresponding to a location, and removing a 2nd mask pattern, a material By performing a 3rd etching process with respect to a board | substrate from the side of a 1st conductor layer through a 1st mask pattern, in a 2nd conductor layer, a 1st conductor has a pair of side surface spaced apart in the in-plane direction of the said 2nd conductor layer. By removing the fourth mask pattern and removing the fourth mask pattern from the side of the fourth conductor layer from the side of the fourth conductor layer through the third mask pattern on the material substrate. In the third conductor layer, having a pair of side surfaces spaced apart in the in-plane direction of the third conductor layer, and forming a second free thin portion in contact with the fourth conductor layer and the insulating layer; By the first conductor layer The first free thin portion is removed from the insulating layer by a step for removing the portion in contact with the first free thin portion and removing the portion in contact with the second free thin portion in the fourth conductor layer and the sixth etching treatment. And removing a portion in contact with the second thin portion by removing the portion in contact with the second thin layer portion from the insulating layer.

In the third aspect of the present invention, preferably, the third etching treatment is anisotropic reactive ion etching showing an etching rate higher in the thickness direction than the in-plane direction in the first conductor layer and the second conductor layer, and the fourth etching treatment is It is anisotropic reactive ion etching which shows the etching rate higher in thickness direction than in-plane direction in a 4th conductor layer and a 3rd conductor layer.

Preferably, the fifth etching treatment is a wet etching showing a higher etching rate in the first conductor layer than the second conductor layer and a higher etching rate in the fourth conductor layer than the third conductor layer. In this case, preferably, the first conductor layer, the second conductor layer, the third conductor layer and the fourth conductor layer are made of a conductive silicon material, and the dopant concentration in the second conductor layer is in the first conductor layer. It is higher than the dopant concentration and the dopant concentration in the third conductor layer is higher than the dopant concentration in the fourth conductor layer.

Preferably, the first conductor layer has a crystal structure having (110) planes extending in the in-plane direction of the first conductor layer and two (111) planes perpendicular to and intersecting with the (110) planes. It is made of a silicon material, and at least part of the contour of the first mask pattern is along the two (111) planes.

Preferably, the fourth conductor layer has two (110) planes extending in the in-plane direction of the fourth conductor layer and two parallel to and intersecting with either one of the two (111) planes in the first conductor layer. A silicon material having a crystal structure having four (111) planes, and at least a part of the contour of the third mask pattern follows the two (111) planes in the fourth conductor layer.

According to a fourth aspect of the present invention, another method for producing a microstructure having a thin portion is provided. This manufacturing method is for masking the part processed into the thin part in a 1st conductor layer with respect to the material substrate containing the laminated structure which consists of a 1st conductor layer and a 2nd conductor layer which have a thickness corresponded to the thickness of a thin part. By performing a 1st etching process from the side of a 1st conductor layer through a mask pattern, the free thin part which has a pair of side surface spaced apart in the in-plane direction of the said 1st conductor layer in a 1st conductor layer, and contact | connects a 2nd conductor layer. And a step for removing a portion in contact with the free thin portion in the second conductor layer by the second etching treatment from the side of the first conductor layer.

In the fourth aspect of the present invention, preferably, the second etching treatment is a wet etching showing a higher etching rate in the second conductor layer than in the first conductor layer. In this case, preferably, the first conductor layer and the second conductor layer are made of a conductive silicon material, and the dopant concentration in the first conductor layer is higher than the dopant concentration in the second conductor layer.

Preferably, the second conductor layer is made of a silicon material having a crystal structure having a (111) plane extending in the in-plane direction of the second conductor layer.

Preferably, the material substrate further comprises an insulating layer in contact with the second conductor layer on the side opposite to the first conductor layer, and a third conductor layer in contact with the insulating layer on the side opposite to the second conductor layer. It has a laminated structure.

Preferably, the process of forming the hole which penetrates a 1st conductor layer, a 2nd conductor layer, and an insulating layer and reaches a 3rd conductor layer by the etching process from the side of a 1st conductor layer, and conducts the said hole The method further includes forming a conductive contact by filling the material.

According to a fifth aspect of the present invention, another method for producing a microstructure having a thin portion is provided. This manufacturing method is processed from a first conductor layer to a thin portion with respect to a material substrate having a laminated structure consisting of a first conductor layer, a second conductor layer, and an insulating layer between the first conductor layer and the second conductor layer. By performing a 1st etching process from the side of a 1st conductor layer to the middle of an insulating layer through the 1st mask pattern which has a site | part for masking a part to become, in the in-plane direction of the said 1st conductor layer in a 1st conductor layer. A pre-thin portion by a step for forming a free thin portion having a pair of side surfaces spaced apart, a step for forming a wet etching stop film on the surface of the first conductor layer including the free thin portion, and dry etching Performing a second etching treatment from the side of the first conductor layer to the insulating layer through the second mask pattern having a portion for masking the film; and pre-baking the first conductor layer by wet etching. And a step for removing the portion interposed between the part and the insulating layer.

In the fifth aspect of the present invention, preferably, the first conductor layer and the wet etch stop film are made of a conductive silicon material, and the dopant concentration in the wet etch stop film is higher than the dopant concentration in the first conductor layer.

Preferably, the method of producing a microstructure according to claim 25, wherein the first conductor layer is made of a silicon material having a crystal structure having a (111) plane extending in the in-plane direction of the first conductor layer.

Preferably, the process of forming the hole which penetrates a 1st conductor layer and an insulating layer, and reaches a 2nd conductor layer by the etching process from the side of a 1st conductor layer, and electroconducts by filling a conductive material in this hole. The method further includes a process for forming a contact portion.

According to a sixth aspect of the invention, a microstructure is provided. This microstructure comprises a first conductor layer made of a conductive silicon material having a (110) plane extending in the in-plane direction and a crystal structure having two (111) planes perpendicular to and intersecting with the (110) plane, and the It is formed of a material substrate including a laminated structure composed of a second conductor layer made of a conductive silicon material having a higher dopant concentration than the first conductor layer. The microstructure includes a first portion formed in the first conductor layer and a second portion formed in the second conductor layer and also in contact with the first portion, each having an outline along the (110) plane and two (111) planes. And a plurality of thick portions to be formed in the second conductor layer and exposed, and a thin portion connecting two selected thick portions.

In a sixth aspect of the invention, preferably, the material substrate is in contact with the second conductor layer on the side opposite to the first conductor layer and in contact with the insulation layer on the side opposite to the second conductor layer. It has a laminated structure which further contains a 3rd conductor layer, The said 3rd conductor layer is parallel with either one of the (110) surface extended in an in-plane direction, and the two (111) surfaces in a 1st conductor layer, and A silicon material having a crystal structure having two (111) planes intersecting with each other, wherein at least one thick portion has an outline along the (110) plane and two (111) planes in the third conductor layer; It further comprises a third portion formed in the three conductor layer.

Preferably, a conductive contact portion for electrically connecting the first portion, the second portion, and the third portion through the insulating layer is further provided.

Preferably, the material substrate includes an insulating layer in contact with the second conductor layer on the side opposite to the first conductor layer, a third conductor layer in contact with the insulating layer on the side opposite to the second conductor layer, and an insulating layer. It has a laminated structure which further contains the 4th conductor layer which contact | connects the said 3rd conductor layer on the opposite side, and this 4th conductor layer has the (110) surface extended in an in-plane direction, and the 2nd in a 1st conductor layer. A conductive silicon material having a crystal structure having two (111) planes parallel to and intersecting with any one of the (111) planes, wherein the third conductor layer has a higher dopant concentration than the fourth conductor layer. The at least one thick portion is formed of a conductive silicone material and has a third portion formed in the third conductor layer and an outline along the (110) plane and the two (111) planes of the fourth conductor layer and in the fourth conductor layer. It further comprises a fourth site formed.

1 is a perspective view of a micromirror element as an example of a microstructure that can be produced by the present invention.

FIG. 2 is a plan view of the micromirror element shown in FIG. 1.

3A to 3D show some steps in the method for manufacturing a micromirror element according to the first embodiment of the present invention.

4A-4D show the process that follows after FIG. 3D.

5A-5D show the process that follows after FIG. 4D.

6A-6D show the process that follows after FIG. 5D.

7A-7D show the process that follows after FIG. 6D.

8 is a plan view of a micromirror element as another example of a microstructure that can be produced by the present invention.

9A to 9D show a part of the steps in the method of manufacturing the micromirror element according to the second embodiment of the present invention.

10A-10D show the process that follows after FIG. 9D.

11A-11C show the process that follows after FIG. 10D.

12A-12C show the process that follows after FIG. 11C.

13A to 13D show a part of the steps in the micromirror device manufacturing method according to the third embodiment of the present invention.

14A-14D show the process that follows after FIG. 13D.

15A-15C show the process that follows after FIG. 14D.

16A-16C show the process that follows after FIG. 15C.

17A-17C show the process that follows after FIG. 16C.

18A to 18D show some steps in the method of manufacturing a micromirror element according to a fourth embodiment of the present invention.

19A-19C show the process that follows after FIG. 18D.

20A-20C show the process that follows after FIG. 19C.

21A-21C show the process that follows after FIG. 20C.

22A to 22D show a part of the steps in the method of manufacturing the micromirror element according to the fifth embodiment of the present invention.

Figures 23A-23D show the process that follows after Figure 22D.

24A-24D show the process that follows after FIG. 23D.

25A-25D show the process that follows after FIG. 24D.

26A-26C show the process that follows after FIG. 25D.

27A to 27D show some steps in the method for manufacturing a micromirror element according to the sixth embodiment of the present invention.

Figures 28A-28D show the process that follows after Figure 27D.

29A-29C show the process that follows after FIG. 28D.

30A to 30C show the process that follows after FIG. 29C.

31A-31C show the process that follows after FIG. 30C.

32 is an exploded perspective view of a conventional flat electrode micromirror element.

33 shows an example of the inclined aspect of the micromirror element shown in FIG. 32.

34 is a partially cutaway perspective view of a conventional comb-shaped electrode type micromirror element.

35A and 35B show the orientation of a set of comb-shaped electrodes.

1 and 2 show a micro mirror element X1 as an example of a microstructure that can be produced by the present invention.

The micromirror element X1 is formed by a micromachining technique from a material substrate having a predetermined laminated structure including a conductive silicon material layer, and includes a mirror portion 110, an inner frame 120 surrounding the same, and an inner frame 120. ) And a pair of connecting portions 140 for connecting the mirror frame 110 and the inner frame 120, and a pair for connecting the inner frame 120 and the outer frame 130 The connecting portion 150 is provided. In Fig. 1, the laminated structure of the material substrate is not shown. The separation distance between the mirror portion 110 and the inner frame 120 and the separation distance between the inner frame 110 and the outer frame 120 are, for example, 10 to 200 μm. The pair of connection portions 140 define the axis of rotation of the mirror portion 110 relative to the inner frame 120. The pair of connecting portions 150 define an axis of rotation of the inner frame 120 and the accompanying mirror portion 110 relative to the outer frame 130. These connecting parts 140 and 150 are provided so that both shaft centers may orthogonally cross. In FIG. 2, the part (except the mirror surface 111 mentioned later) which protrudes in the front direction of the paper rather than the connection parts 140 and 150 is hatched.

The pair of comb-shaped electrodes 110a and 110b which protrude outward from the pair of parallel side surfaces is integrally formed in the mirror part 110. As shown in FIG. In addition, a mirror surface 111 is provided on the upper surface of the mirror unit 110.

The internal frame 120 is integrally molded with the comb-shaped electrodes 121a and 121b extending outwardly, and the comb-shaped electrodes 122a and 122b extending inwardly are integrally molded. have. The comb-shaped electrode 122a is formed so that the projection of the comb-shaped electrode 110a does not come into contact with the protrusion of the comb-shaped electrode 122a during the rotation operation of the mirror 110 with respect to the inner frame 120. It is arrange | positioned below 110a). Similarly, the comb-shaped electrode 122b is disposed below the comb-shaped electrode 110b so that the projection of the comb-shaped electrode 110b does not come into contact with the projection of the comb-shaped electrode 122b during the rotation operation of the mirror part 110. It is.

The external frame 130 is integrally molded with comb-shaped electrodes 132a and 132b extending inwardly and protruding. The comb-shaped electrode 132a is a comb-shaped electrode such that the projection of the comb-shaped electrode 121a does not come into contact with the projection of the comb-shaped electrode 132a during the rotation operation of the inner frame 120 with respect to the outer frame 130. It is arrange | positioned below 121a. Similarly, the comb-shaped electrode 132b is positioned below the comb-shaped electrode 121b so that the projection of the comb-shaped electrode 121b and the projection of the comb-shaped electrode 132b do not contact each other when the internal frame 120 is rotated. It is arranged.

Each connecting portion 140 is composed of two torsion bars 141 spaced apart from each other. Each torsion bar 141 is connected to the mirror part 110 and the internal frame 120, and is thinner than these. In addition, the distance between the two torsion bars 141 gradually extends from the side of the inner frame 120 to the side of the mirror portion 110.

Each connecting portion 150 is composed of two torsion bars 151 spaced apart from each other. Each torsion bar 151 is connected to the inner frame 120 and the outer frame 130, and is thinner than these. The interval between the two torsion bars 151 gradually extends from the side of the outer frame 130 to the side of the inner frame 120.

The forming positions of the connecting portions 140 and 150 and the shapes of the torsion bars 141 and 151 included therein are appropriately selected depending on the mechanical properties required for the connecting portions 140 and 150, the driving mode of the device, and the manufacturing method of the device. Is designed.

As such, the micromirror element X1 is thinner than the mirror unit 110 and the inner frame 120, and may have a connection portion 140 to torsion bar that may serve as a conductive path between the mirror unit 110 and the inner frame 120. A connection portion 150 to torsion bar having a 141 and thinner than the inner frame 120 and the outer frame 130 and capable of conducting a conductive path between the inner frame 120 and the outer frame 130. Has 151.

3A to 7D show a series of steps in the method for producing a microstructure according to the first embodiment of the present invention. This method is one technique for manufacturing the aforementioned micro mirror element X1 by micromachining technology.

3A to 7D show the process of forming the mirror portions M, the torsion bars T1 to T3, the inner frames F1 and F2, the set of comb-shaped electrodes El, E2 and the outer frame F3 shown in FIG. 7D by one cross section. . This one cross section models a cross section of a plurality of predetermined points included in a single micromirror element formation section in a material substrate (a wafer having a multi-layer structure) subjected to micromachining and is expressed as a continuous cross section.

In FIG. 7D, the mirror portion M corresponds to one portion of the mirror portion 110. The torsion bar T1 is corresponded to the torsion bar 141, and is represented by the cross section along the extending direction. The inner frame F1 corresponds to a portion of the inner frame 120 to which the torsion bar 141 is connected. The comb-shaped electrode E1 corresponds to a part of comb-shaped electrodes 110a, 110b, 121a, 121b. The comb-shaped electrode E2 corresponds to a part of comb-shaped electrodes 122a, 122b, 132a, and 132b. The torsion bar T2 corresponds to the torsion bars 141 and 151 and is indicated by a cross section perpendicular to the extension direction. The inner frame F2 corresponds to one portion of the inner frame 120 to which the torsion bar 151 is connected. The torsion bar T3 corresponds to the torsion bar 151 and is indicated by the cross section along the extending direction. The outer frame F3 corresponds to a part of the degree that the torsion bar 151 is connected in the outer frame 130.

In the microstructure manufacturing method according to the first embodiment, a material substrate S1 as shown in FIG. 3A is first produced. The material substrate S1 has a laminated structure composed of the silicon layer 11 and the silicon layer 12.

The silicon layer 11 is made of a silicon material imparted with conductivity by doping a p-type impurity such as B or the like. The concentration of B dopant in the silicon layer 11 is 1 * 10 <^17> -1 * 10 <^18> atom / cm <^3>, for example. In addition, the silicon layer 11 has a crystal structure in which the (110) plane or the (100) plane extends in the in-plane direction of the layer.

The silicon layer 12 is made of a silicon material imparted with conductivity by doping p-type impurities such as B, and has a thickness of, for example, 1 to 5 µm. This thickness corresponds to the thickness of the torsion bars T1 to T3. The concentration of B dopant in the silicon layer 12 is higher than that of the silicon layer 11, for example, 1 × 10 ¹⁹ atom / cm ^3. That's it. Preferably, the dopant concentration in the silicon layer 12 is at least 100 times that of the silicon layer 11.

In order to impart conductivity to the silicon layers 11 and 12, P or Sb may be employed instead of B as the dopant. P and Sb can be used instead of B as conductivity providing means described later for the silicon material.

In the production of the material substrate S1, first, a first silicon wafer for the silicon layer 11 having the same thickness as the silicon layer 11 and a second silicon wafer for the silicon layer 12 thicker than the silicon layer 12 are formed. Join directly. In the bonding, both wafers are bonded to each other while physically or chemically activating the bonding surfaces of the respective wafers and then heating as necessary. After bonding, the second silicon wafer is polished by chemical mechanical polishing (CMP) to form a silicon layer 12 having a desired thickness. According to the CMP method, a highly accurate thickness dimension can be realized with respect to the silicon layer 12. As the polishing method described later for the silicon material, the CMP method can be adopted. In this way, the material substrate S1 shown in FIG. 3A is produced.

In the present embodiment, as shown in FIG. 3B, an oxide film 14 ′ is formed on the surface of the silicon layer 12. The oxide film 14 'can be formed by forming silicon dioxide on the silicon layer 12 by CVD. Alternatively, the oxide film 14 'can be formed by oxidizing the surface of the silicon layer 12 by a thermal oxidation method (heating temperature: for example, 900 占 폚). The oxide film 14 'may be polished as necessary. The thickness of the oxide film 14 'is 0.1-1 micrometer, for example.

Next, as shown in FIGS. 3C and 3D, the material substrate S1 and the separately produced material substrate S2 are bonded. The material substrate S2 consists of a silicon layer 13 and an oxide film 14 '' made of silicon dioxide, and on one surface of the silicon wafer, a CVD method or a thermal oxidation method (heating temperature: for example, 900 ° C). Can be produced by forming the oxide film 14 ''. The oxide film 14 '' may be polished as necessary. According to the silicon wafer, the silicon layer 13 is made of a silicon material to which conductivity is imparted by doping p-type impurities such as B or the like. The thickness of the oxide film 14 '' is, for example, 0.1 to 1 mu m. Bonding of the material substrate S1 and the material substrate S2 is achieved by a predetermined direct bonding through the oxide film 14 'and the oxide film 14' '. The oxide film 14 'and the oxide film 14' 'are integrally formed as the insulating layer 14 as shown in Fig. 3D. The thickness of the insulating layer 14 is 0.2-2 micrometers, for example.

Next, as shown in FIG. 4A, the silicon layer 11 and the silicon layer 13 are polished to a desired thickness. In this way, a material substrate S3 having a laminated structure composed of the conductive silicon layers 11, 12, 13 and the insulating layer 14 is produced. In the material substrate S3, the thickness of the silicon layer 11 is, for example, 50 to 100 µm, and the thickness of the silicon layer 12 is, for example, 1 to 5 µm, as described above, and the thickness of the silicon layer 13. Is 50-100 micrometers, for example, and the thickness of the insulating layer 14 is 0.2-2 micrometers as mentioned above, for example.

Next, as shown in FIG. 4B, holes H 'penetrating the silicon layers 11 and 12 are formed at predetermined positions of the material substrate S3. In the formation of the holes H ', first, a predetermined resist pattern is formed on the silicon layer 11. This resist pattern has an opening corresponding to the formation position of the hole H '. Next, using this resist pattern as a mask, etching treatment is performed from the side of the silicon layer 11 to the insulating layer 14 by DRIE (Deep Reactive Ion Etching). As the mask in the etching process, an oxide film pattern or a nitride film pattern may be used instead of the resist pattern.

In the DRIE, a good etching process can be performed in a Bosch process in which etching and sidewall protection are alternately performed. This Bosch process can also be employed for the DRIE described later.

Next, as shown in FIG. 4C, the hole H penetrating the insulating layer 14 in addition to the silicon layers 11 and 12 is formed by removing the portion exposed to the hole H 'in the insulating layer 14. . As the removal method, wet etching or dry etching can be employed. When wet etching is employed, a buffered hydrofluoric acid (BHF) consisting of hydrofluoric acid and ammonium fluoride can be used as the etching solution. In the case of employing dry etching, for example, hydrogen fluoride or the like can be employed as the etching gas. Such wet etching or dry etching can also be employed as the removal method described later for an oxide film, an oxide film pattern, or an insulating layer made of silicon dioxide.

Next, as shown in FIG. 4D, for example, the conductive material P 'is deposited on the inside of the hole H and on the silicon layer 11 by the CVD method. As the conductive material P ', polysilicon doped with predetermined impurities or metal such as Cu or W can be used.

Next, as shown in FIG. 5A, the conductive material P 'deposited on the silicon layer 11 is polished and removed by the CMP method. In this way, the plugs P1 and P2 embedded in the material substrate S3 are formed.

Next, as shown in FIG. 5B, the mirror surface 111 is formed on the silicon layer 11, and the electrode pad 15 for external connection is shown on the silicon layer 13 (shown in FIGS. 1 and 2). Not).

In the formation of the mirror surface 111, first, for example, Cr (50 nm) and subsequently Au (200 nm) are formed on the silicon layer 11 by the sputtering method. Next, the mirror surface 111 is pattern-formed by performing an etching process with respect to these metal films sequentially through a predetermined mask. As the etching solution for Au, for example, a potassium iodide hydrophobic solution can be used. As the etching solution for Cr, for example, an aqueous solution of dicerium ammonium nitrate can be used.

The formation method of the electrode pad 15 which has a predetermined pattern shape is the same as the formation method of the mirror surface 111. FIG.

Next, as shown in FIG. 5C, the oxide film pattern 16a is formed on the silicon layer 11, and the oxide film 16b is formed on the silicon layer 13. In the formation of the oxide film pattern 16a, first, silicon dioxide is formed on the surfaces of the silicon layers 11 and 13 by CVD until the thickness becomes, for example, 1 m. As a result, an oxide film 16b is formed on the silicon layer 13. Next, the oxide film on the silicon layer 11 is patterned by etching using a predetermined resist pattern as a mask. As etching liquid in this patterning, the buffered hydrofluoric acid (BHF) which consists of hydrofluoric acid and ammonium fluoride can be used, for example. The oxide film pattern described later is also formed through formation of a resist pattern on the oxide film and subsequent etching treatment. The oxide film pattern 16a is a part of the mirror portion M, the inner frame F1, the comb-shaped electrode E1, the part of the inner frame F2, and the part of the outer frame F3 in the material substrate S3 in the step shown in FIGS. 6A to 6C described later. It is for masking the part to be processed.

Next, as shown in FIG. 5D, a resist pattern 16 c is formed on the silicon layer 11. In the formation of the resist pattern 16c, first, a liquid photoresist is formed on the silicon layer 11 by spin coating. Next, the photoresist film is patterned through exposure and subsequent development. As a photoresist, AZP4210 (made by Clariant Japan) and AZ1500 (made by Clariant Japan) can be used, for example. The resist pattern described later is also formed through the film formation of such photoresist and subsequent exposure and development processes. The resist pattern 16c is for masking a part of the silicon layer 11 corresponding to the part processed by the torsion bars T1 to T3 in the silicon layer 12 in the step shown in FIG. 6A.

Next, as shown in FIG. 6A, the silicon film 11 is etched to a predetermined depth by DRIE using the oxide film pattern 16a and the resist pattern 16c as masks. The predetermined depth is appropriately determined according to the thickness of the torsion bars T1 to T3, that is, the thickness of the silicon layer 12. This etching is anisotropic ion etching which shows the etching rate higher in the thickness direction than the in-plane direction in the silicon layer 11. After the etching process, the resist pattern 16c is peeled off. As a peeling liquid for peeling the resist pattern 16c, AZ remover 700 (made by Clariant Japan) can be used. Also in peeling of the resist pattern mentioned later, this peeling liquid can be used.

Next, as shown in FIG. 6B, the etching process is performed from the side of the silicon layer 11 to the insulating layer 14 by DRIE, using the oxide film pattern 16a as a mask. This etching is anisotropic ion etching which shows the etching rate higher in the thickness direction than in-plane direction in the silicon layers 11 and 12. FIG. Thereby, the pre-torsion bar Tl 'which has a pair of side surface spaced apart in the in-plane direction of the silicon layer 12, and is in contact with the silicon material 11a derived from the silicon layer 11, and the insulating layer 14. T3 'is formed. The pre-torsion bars Tl 'to T3' are derived from the silicon layer 12. In addition, a part of the mirror portion M, the inner frame F1, the inner frame F2 and the outer frame F3 are also formed by the present etching process.

6C, the silicon material 11a is removed by the wet etching method using the oxide film pattern 16a and the oxide film 16b as a mask. As the etchant, ethylenamine, pyrocatechol and water (EPW), tetramethyl ammonium hydroxide (TMAH) or aqueous potassium hydroxide solution may be used.

As for the etching rate by the wet etching, since the silicon layers 12 to pretorsion bars Tl 'to T3' are much slower than the silicon layers 11 to silicon material 11a, the pre-torsion bar Tl is used in this etching process. The silicon material 11a can be appropriately removed leaving '-T3'. The difference in etching rate is due to the difference in dopant concentration in the silicon material. As described above, the dopant concentration in the silicon layer 12 is preferably 100 times or more of the dopant concentration in the silicon layer 11.

Next, as shown in Fig. 6D, the oxide film 16d is formed by forming silicon dioxide from the upper portion of the oxide film pattern 16a on the material substrate S3 by the CVD method or the spin-on-glass coating method. The oxide film 16d is responsible for protecting the surface of the structure formed above in the figure of the insulating layer 14.

Next, as shown in Fig. 7A, an oxide film pattern 16e is formed in a part of the oxide film 16d, and an oxide film pattern 16f is formed in the oxide film 16b. The oxide film pattern 16e is for masking the part processed by the comb-tooth-shaped electrode E1 in the material substrate S3 in the process shown to FIG. 7B mentioned later. The oxide film pattern 16f is for masking the locations processed by the comb-shaped electrode E2, part of the inner frame F2 and part of the outer frame F3 in the material substrate S3 in the step shown in FIG. 7C described later.

Next, as shown in FIG. 7B, the etching process is performed from the side of the silicon layer 11 to the insulating layer 14 by DRIE using the oxide film 16d and the oxide film pattern 16e as a mask. . Thereby, the comb-tooth shaped electrode E1 is shape | molded.

Next, as shown in FIG. 7C, the etching process is performed from the side of the silicon layer 13 to the insulating layer 14 by DRIE using the oxide film pattern 16f as a mask. Thereby, the comb-tooth shaped electrode E2, a part of inner frame F2, and a part of outer frame F3 are shape | molded.

Next, as shown in FIG. 7D, the portions exposed in the oxide film 16d, the oxide film pattern 16e, the oxide film pattern 16f, and the insulating layer 14 are etched and removed. By this etching, the portions of the insulating layer 14 in contact with the free torsion bars Tl 'to T3' are removed to form the torsion bars T1 to T3.

Through the above series of steps, the mirror portions M, the torsion bars T1 to T3, the inner frames Fl, F2, the comb-shaped electrodes E1, E2 and the outer frame F3 are formed. That is, the micromirror element X1 shown to FIG. 1 and FIG. 2 is manufactured.

In this embodiment, in the manufacturing process of the material substrate S1 mentioned above with reference to FIG. 3A, the silicon layer 12 which has a high precision thickness dimension can be formed. The torsion bars T1 to T3, which are thin parts of the micromirror element X1, are molded from the silicon layer 12 to the same thickness as the silicon layer 12, and thus have a high precision thickness dimension.

The mirror part M formed in this embodiment has the site | part derived from the silicon layer 11, and the site | part which originates in the silicon layer 12 and is continuous to torsion bar T1, and these two site | parts have electroconductivity. The inner frame F1 has a portion derived from the silicon layer 11 and a portion derived from the silicon layer 12 and continuous to the torsion bar T1, and these two portions have conductivity. Therefore, the mirror portion M (mirror portion) 110 and the inner frame Fl (inner frame) 120 are electrically connected through the torsion bar Tl (torsion bar) 141.

In addition, the internal frame F2 has a portion derived from the silicon layer 11, a portion derived from the silicon layer 12 and continuous to the torsion bar T3, and a portion derived from the silicon layer 13. These three sites have conductivity and are electrically connected through the plug P1. The outer frame F3 has a portion derived from the silicon layer 11, a portion derived from the silicon layer 12 and continuous to the torsion bar T3, and a portion derived from the silicon layer 13. These three sites have conductivity and are electrically connected through the plug P2. Therefore, the portion derived from the silicon layer 13 in the inner frame F2 (inner frame) 120 and the portion derived from the silicon layer 13 in the outer frame F3 (outer frame) 130 are separated from the torsion bar T3 ( It is electrically connected via a torsion bar 151.

In this embodiment, another aspect can also be comprised by not providing plug P1 or plug P2 about the electrical connection between inner frame F2 and outer frame F3. For example, when the plug P1 is not provided, a portion derived from the silicon layer 13 in the inner frame F2 and a portion derived from the silicon layer 13 in the outer frame F3 can be electrically separated.

In the micro-mirror element X1 manufactured by the method of this embodiment, the electrical connection mode by each torsion bar 151 contained in the connection part 150 is selected suitably, and each torsion bar 151 is improperly selected. By forming a conductive path inside the inner frame 120 and the outer frame 130 so as not to be shorted, a plurality of potentials through the plurality of torsion bars 151 from the outer frame 130 to the inner frame 120. Delivery is possible. Therefore, it becomes possible to individually control the magnitude of the potential to be applied to each comb-shaped electrode.

8 shows a micromirror element X2 as an example of a microstructure which can be produced by the present invention.

The micro mirror element X2 is formed by a micromachining technique from a material substrate having a predetermined laminated structure including a conductive silicon material layer, and includes a mirror portion 210, an inner frame 220, an outer frame 230, A pair of connection part 240 and a pair of connection part 250 are provided. The pair of connecting portions 240 connect the mirror portion 210 and the inner frame 220 to define the axis A1 of the rotational operation of the mirror portion 210 with respect to the inner frame 220. The pair of connecting portions 250 connects the inner frame 220 and the outer frame 230 to form an axis of rotation of the inner frame 220 with respect to the outer frame 230 and the mirror portion 210 accompanying the same. It specifies A2. The connection parts 240 and 250 are provided so that the crossing angle which the axial center A1 and the axial center A2 make may be set to 70.5 degrees. In FIG. 8, the part (except the mirror surface 211 which is mentioned later) which protrudes toward the front surface of the paper rather than the connection parts 240 and 250 is hatched.

The pair of comb-shaped electrodes 210a and 210b in which the pair extends outward from the parallel side surface is integrally formed. In addition, a mirror surface 211 is provided on the upper surface of the mirror portion 210.

The internal frame 220 is integrally molded with the comb-shaped electrodes 221a and 221b extending outwardly, and the comb-shaped electrodes 222a and 222b extending inwardly are integrally molded. have. The comb-shaped electrode 222a is disposed so that the projection of the comb-shaped electrode 210a does not come into contact with the projection of the comb-shaped electrode 222a during the rotation operation of the mirror unit 210 with respect to the inner frame 220. Similarly, the comb-shaped electrode 222b is arranged so that the projection of the comb-shaped electrode 210b and the projection of the comb-shaped electrode 222b do not come into contact with each other during the rotation operation of the mirror portion 210.

The external frame 230 is integrally molded with comb-shaped electrodes 232a and 232b that extend inwardly and protrude. The comb-shaped electrode 232a is arrange | positioned so that the protrusion of the comb-shaped electrode 221a may not contact the protrusion of the comb-shaped electrode 232a at the time of the rotation operation of the inner frame 220 with respect to the outer frame 230. As shown in FIG. Similarly, the comb-shaped electrode 232b is arrange | positioned so that the protrusion of the comb-shaped electrode 221b and the protrusion of the comb-shaped electrode 232b may not contact at the time of the rotation operation of the internal frame 220. FIG.

Each connecting portion 240 is composed of two torsion bars 241 spaced apart from each other. Each torsion bar 241 is connected to the mirror part 210 and the internal frame 220, and is thinner than these. In addition, the distance between the two torsion bars 241 gradually extends from the side of the inner frame 220 to the side of the mirror portion 210.

One of the pair of connecting portions 240 is connected to a position closer to the comb-shaped electrode 210a than the comb-shaped electrode 210b with respect to the mirror portion 210, and the other connecting portion 240 is a mirror. The part 210 is connected to a location closer to the comb-shaped electrode 210b than to the comb-shaped electrode 210a. The side surface to which the connection part 240 connects in the mirror part 210 and the side surface to which the connection part 240 connects in the inner frame 220 are orthogonal to the axial center Al defined by the pair of connection part 240.

Each connection part 250 is composed of two torsion bars 251 spaced apart from each other. Each torsion bar 251 is connected to the inner frame 220 and the outer frame 230, and is thinner than these. In addition, the spacing of the two torsion bars 251 gradually extends from the side of the outer frame 230 to the side of the inner frame 220.

One of the pair of connecting portions 250 is connected to a position closer to the comb-shaped electrode 221a than the comb-shaped electrode 221b with respect to the inner frame 220, and the other connecting portion 250 is the inner frame. It connects to the location 220 closer to the comb-shaped electrode 221b rather than the comb-shaped electrode 221a. The side to which the connection part 250 connects in the inner frame 220 and the side to which the connection part 250 connects in the outer frame 230 are orthogonal to the axis A2 defined by the pair of connection parts 250.

The position at which the connectors 240 and 250 are formed and the shapes of the torsion bars 241 and 251 included therein are appropriately selected depending on the mechanical properties required for the connectors 240 and 250, the driving mode of the device, and the method of manufacturing the device. Is designed.

As such, the micromirror element X2 is thinner than the mirror unit 210 and the inner frame 220, and may have a connection portion 240 to torsion bar that may serve as a conductive path between the mirror unit 210 and the inner frame 220. A connection portion 250 to torsion bar having a 241 and thinner than the inner frame 220 and the outer frame 230 and capable of conducting a conductive path between the inner frame 220 and the outer frame 230. Has 251.

9A to 12C show a series of steps in the method for manufacturing a microstructure according to the second embodiment of the present invention. This method is one technique for fabricating the aforementioned micro mirror element X2 by micromachining technology. In Figs. 9A to 12C, mirror sections M, torsion bars T1 to T3, internal frames Fl and F2, a set of comb-shaped electrodes El, E2 and external frames are formed by one cross section modeled as in Figs. 3A to 7D. The formation process of F3 is shown.

In the microstructure manufacturing method according to the second embodiment, a material substrate S4 as shown in FIG. 9A is first produced. The material substrate S4 has a laminated structure composed of the silicon layer 21 and the silicon layer 22.

The silicon layer 21 is made of a silicon material imparted with conductivity by doping a p-type impurity such as B or the like. The concentration of B dopant in the silicon layer 21 is 1 * 10 <^17> -1 * 10 <^18> atom / cm <^3>, for example. In addition, the silicon layer 21 has a crystal structure in which the (110) plane extends in the in-plane direction of the layer and has two (111) planes orthogonal to the (110) plane.

The silicon layer 22 is made of a silicon material imparted with conductivity by doping p-type impurities such as B, and has a thickness of, for example, 1 to 5 mu m. This thickness corresponds to the thickness of the torsion bars T1 to T3. The concentration of the B dopant in the silicon layer 22 is higher than that of the silicon layer 21, for example, 1 × 10 ¹⁹ atoms / cm ³ or more. Preferably, the dopant concentration in the silicon layer 22 is 100 times or more of that in the silicon layer 21.

The material substrate S4 is produced similarly to the material substrate S1 in the first embodiment. Therefore, the silicon layer 22 of the material substrate S4 is formed by polishing the silicon wafer until the desired thickness by the CMP method, and has a high precision thickness dimension.

In this embodiment, an oxide film 24 'is formed next on the surface of the silicon layer 22, as shown in FIG. 9B. The oxide film 24 'can be formed by forming silicon dioxide on the silicon layer 22 by the CVD method. Alternatively, the oxide film 24 'can be formed by oxidizing the surface of the silicon layer 22 by a thermal oxidation method (heating temperature: for example, 900 占 폚).

Next, as shown in FIGS. 9C and 9D, the material substrate S4 and the separately produced material substrate S5 are bonded. The material substrate S5 is composed of a silicon layer 23 and an oxide film 24 '' made of silicon dioxide, and on one surface of the silicon wafer, a CVD method or a thermal oxidation method (heating temperature: for example, 900 ° C). By forming the oxide film 24 ''. The thickness of the oxide film 24 '' is, for example, 0.1 to 1 mu m. The oxide film 24 'and the oxide film 24' 'are integrally formed as the insulating layer 24 as shown in Fig. 9D. The thickness of the insulating layer 24 is 0.2-2 micrometers, for example. According to the silicon wafer, the silicon layer 23 is made of a silicon material to which conductivity is imparted by doping p-type impurities such as B and the like. In addition, the silicon layer 23 has a crystal structure in which the (110) plane extends in the in-plane direction of the layer and has two (111) planes orthogonal to the (110) plane. The material substrate S4 and the material substrate S5 are joined so that the directions of the two (111) surfaces in the silicon layer 21 and the directions of the two (111) surfaces in the silicon layer 24 coincide. Bonding of the material substrate S1 and the material substrate S2 is achieved by a predetermined direct bonding through the oxide film 14 'and the oxide film 14' '.

Next, as shown in FIG. 10A, the silicon layer 21 and the silicon layer 23 are polished to a desired thickness. In this way, a material substrate S6 having a laminated structure composed of the conductive silicon layers 21, 22, and 23 and the insulating layer 24 is produced. The thickness of the silicon layer 21 in the material substrate S6 is, for example, 50 to 100 m, the thickness of the silicon layer 22 is, for example, 1 to 5 m, as described above, and the thickness of the silicon layer 23 is For example, it is 50-100 micrometers, and the thickness of the insulating layer 24 is 0.2-2 micrometers as mentioned above, for example.

Next, as shown in FIG. 10B, the plug P3 penetrates the silicon layer 21, the silicon layer 22, and the insulating layer 24 to the silicon layer 23 at a predetermined position of the material substrate S6, Forms P4. The formation method of plug P3, P4 is the same as that of the formation method mentioned above with reference to FIGS. 4B-5A about plug P1, P2 in 1st Embodiment.

Next, as shown in FIG. 10C, a mirror surface 211 is formed on the silicon layer 21, and an electrode pad 25 for external connection (not shown in FIG. 8) is formed on the silicon layer 23. To form. The formation method of the mirror surface 211 and the electrode pad 25 is the same as the formation method of the mirror surface 111 and the electrode pad 15 in 1st Embodiment, respectively.

Next, as shown in FIG. 10D, an oxide film pattern 26a is formed on the silicon layer 21, and an oxide film pattern 26b is formed on the silicon layer 23. The oxide film pattern 26a is a part of the mirror portion M, the inner frame F1, the comb-shaped electrode E1, the inner frame F2 and the outer frame F3 in the material substrate S6 in the steps shown in FIGS. 11B, 11C, and 12B described later. It is for masking the part processed into a part of. The contour of the oxide film pattern 26a follows two kinds of (111) planes in the silicon crystal material constituting the silicon layer 21. The oxide film pattern 26b is for masking the part processed by the comb-tooth-shaped electrode E2, a part of inner frame F2, and a part of outer frame F3 in the material substrate S6 in the process shown to FIG. 12A and 12B mentioned later. The contour of the oxide film pattern 26b follows two kinds of (111) planes in the silicon crystal material constituting the silicon layer 23.

Next, as shown in FIG. 11A, a resist pattern 26c is formed on the silicon layer 21. The resist pattern 26c is for masking a part of the silicon layer 21 corresponding to the part processed by the torsion bars T1 to T3 in the silicon layer 22 in the following step shown in FIG. 11B.

Next, as shown in FIG. 11B, the silicon film 21 is etched to a predetermined depth by DRIE using the oxide film pattern 26a and the resist pattern 26c as masks. The predetermined depth is appropriately determined according to the thickness of the torsion bars T1 to T3, that is, the thickness of the silicon layer 22.

This etching is anisotropic ion etching which shows the etching rate higher in the thickness direction than the in-plane direction in the silicon layer 21. FIG. After the etching process, the resist pattern 26c is peeled off.

Next, as shown in FIG. 11C, the etching process is performed from the side of the silicon layer 21 to the insulating layer 24 by DRIE, using the oxide film pattern 26a as a mask. This etching is anisotropic ion etching which shows the etching rate higher in the thickness direction than in-plane direction in the silicon layers 21 and 22. FIG. Thereby, the silicon layer 21 has a pair of side surfaces spaced apart in the in-plane direction, and the silicon material 21a derived from the silicon layer 21 and the pre-torsion bars Tl 'to T3' contacting the insulating layer 24 are formed. Will be. The free torsion bars Tl 'to T3' are derived from the silicon layer 22. Moreover, by this etching process, the mirror part M, the internal frame F1, the comb-shaped electrode E1, the part of internal frame F2, and the part of external frame F3 are also shape | molded.

Next, as shown in FIG. 12A, using the oxide film pattern 26b as a mask, an etching process is performed from the side of the silicon layer 23 to the insulating layer 24 by DRIE. Thereby, the comb-tooth shaped electrode E2, a part of inner frame F2, and a part of outer frame F3 are shape | molded.

Next, as shown in FIG. 12B, the silicon material 21a is removed by the wet etching method using the oxide film pattern 26a and the oxide film pattern 26b as a mask. As etching liquid, said etching liquid for removing the silicon material 11a in 1st Embodiment can be used.

As for the etching rate by the wet etching, since the silicon layers 22 to pretorsion bars Tl 'to T3' are much slower than the silicon layers 21 to silicon material 21a, in the present etching treatment, the pretorsion bar Tl The silicon material 21a can be appropriately removed leaving '-T3'.

In addition, since the side surfaces of the mirror portion M, the inner frames F1, F2, the comb-shaped electrodes E1, E2, and the outer frame F3 are (111) planes of silicon crystals, the etching rate in the direction perpendicular to the plane in this etching process is Very slow and unreasonably eroded.

Next, as shown in FIG. 12C, the portions exposed in the oxide film pattern 26a, the oxide film pattern 26b, and the insulating layer 24 are etched and removed. By this etching, the portions of the insulating layer 14 in contact with the free torsion bars T1 'to T3' are removed to form the torsion bars T1 to T3.

Through the above series of steps, the mirror portions M, the torsion bars T1 to T3, the inner frames Fl, F2, the comb-shaped electrodes E1, E2 and the outer frame F3 are formed. That is, the micro mirror element X2 shown in FIG. 8 is manufactured.

In this embodiment, in the manufacturing process of the material substrate S4 mentioned above with reference to FIG. 9A, the silicon layer 22 which has a high precision thickness dimension can be formed. The torsion bars T1 to T3, which are thin parts of the micromirror element X2, are molded from the silicon layer 22 to the same thickness as the silicon layer 22, and thus have a high precision thickness dimension.

The mirror part M formed in this embodiment has the site | part derived from the silicon layer 21, and the site | part which originates in the silicon layer 22 and is continuous to torsion bar T1, and these two site | parts have electroconductivity. The inner frame F1 has a portion derived from the silicon layer 21 and a portion derived from the silicon layer 22 and continuous to the torsion bar T1, and these two portions have conductivity. Therefore, the mirror portion M (mirror portion) 210 and the inner frame Fl (inner frame) 220 are electrically connected through the torsion bar Tl (torsion bar) 241.

In addition, the internal frame F2 has a portion derived from the silicon layer 21, a portion derived from the silicon layer 22 and continuous to the torsion bar T3, and a portion derived from the silicon layer 23. These three sites have conductivity and are electrically connected through the plug P3. When the outer frame F3 originates in the silicon layer 21, it has the site | part which originates in the silicon layer 22, and continues to torsion bar T3, and the site | part which originates in the silicon layer 23. As shown in FIG. These three sites have conductivity and are electrically connected through the plug P4. Therefore, the portion derived from the silicon layer 23 in the inner frame F2 (inner frame) 220 and the portion derived from the silicon layer 23 in the outer frame F3 (outer frame; 230) are separated from the torsion bar T3 ( Electrically connected via a torsion bar 251.

In this embodiment, another aspect can also be comprised by not providing plug P3 or plug P4 about the electrical connection between inner frame F2 and outer frame F3. For example, when the plug P3 is not provided, a portion derived from the silicon layer 23 in the inner frame F2 and a portion derived from the silicon layer 23 in the outer frame F3 can be electrically separated.

In the micro-mirror element X2 manufactured by the method of this embodiment, the electrical connection mode by each torsion bar 251 included in the connection part 250 is selected suitably, and each torsion bar 251 is improperly selected. By forming a conductive path inside the inner frame 220 and the outer frame 230 so as not to be shorted, a plurality of potentials through the plurality of torsion bars 251 from the outer frame 230 to the inner frame 220. Delivery is possible. Therefore, it becomes possible to individually control the magnitude of the potential to be applied to each comb-shaped electrode.

In the present embodiment, the contours of the oxide film patterns 26a and 26b for masking the locations processed by the mirror portions M, the inner frames F1 and F2, the comb-shaped electrodes El and E2, and the outer frame F3 in the material substrate S6 are the material. Two types of (111) planes present in the crystal structure of the silicon material constituting the substrate S6 are followed. Therefore, the mirror portion M, the inner frame F1, F2, the comb-shaped electrodes El, E2 and the outer frame F3, that is, the mirror portion 210, whose outer shape is formed by the etching process performed using the oxide film patterns 26a and 26b as a mask, are made. ), The inner frame 220, the comb-shaped electrodes 210a, 210b, 221a, 221b, 222a, 222b, 232a, 232b, and the side surfaces of the outer frame 230 are (111) faces in the crystal structure of the silicon material. Corresponds to The two types of (111) planes intersect at 70.5 ° as described above. Therefore, according to this embodiment, it is possible to manufacture micro mirror element X2 which has a shape as shown in FIG.

13A to 17C show a series of steps in the method for manufacturing a microstructure according to the third embodiment of the present invention. This method is one technique for manufacturing the aforementioned micro mirror element X1 by micromachining technology. In FIGS. 13A to 17C, the mirrored portion M, the torsion bars T1 to T4, the inner frames F1 and F2, the set of comb-shaped electrodes El, E2 and the outer frame F3 shown in FIG. The formation process is shown. The torsion bar T4 is corresponded to the torsion bar 151, and is represented by the cross section along the extending direction.

In the microstructure manufacturing method according to the first embodiment, first, material substrates S7 and S8 as shown in FIG. 13A are produced. The material substrate S7 has a laminated structure composed of the silicon layer 31, the silicon layer 32, and the oxide film 35 '. The material substrate S8 has a laminated structure composed of the silicon layer 33, the silicon layer 34, and the oxide film 35 ″.

The silicon layers 31 and 34 are made of a silicon material imparted with conductivity by doping a p-type impurity such as B or the like. The concentration of the B dopant in the silicon layers 31 and 34 is, for example, 1 × 10 ^{17 to} 1 × 10 ¹⁸ atom / cm ³ . Further, the silicon layers 31 and 34 have a crystal structure in which the (110) plane or the (100) plane extends in the in-plane direction of the layer.

The silicon layers 32 and 33 are made of a silicon material imparted with conductivity by doping a p-type impurity such as B or the like. The silicon layer 32 has thickness of 1-5 micrometers, for example, and this thickness is corresponded to the thickness of torsion bar T1-T3. The silicon layer 33 has a thickness of, for example, 1 to 5 mu m, and this thickness corresponds to the thickness of the torsion bar T4. The concentration of B dopant in the silicon layers 32 and 33 is higher than that of the silicon layers 31 and 34, for example, 1 × 10 ¹⁹ atom / cm ³ or more. Preferably, the dopant concentration in the silicon layers 32 and 33 is at least 100 times that of the silicon layers 31 and 34.

Material substrates S7 and S8 are produced as described above with reference to FIGS. 3A and 3B with respect to the first embodiment. Accordingly, the silicon layer 32 of the material substrate S7 and the silicon layer 33 of the material substrate S8 are formed by polishing the silicon wafer until the desired thickness is obtained by the CMP method, and have a high precision thickness dimension.

In this embodiment, next, as shown in FIG. 13B, the material substrate S7 and the material substrate S8 are bonded. Bonding of the material substrate S7 and the material substrate S8 is achieved by a predetermined direct bonding through the oxide film 35 'and the oxide film 35' '. The oxide film 35 'and the oxide film 35' 'are integrated into the insulating layer 35. The thickness of the insulating layer 35 is 0.2-2 micrometers, for example.

Next, as shown in FIG. 13C, the silicon layer 31 and the silicon layer 34 are polished to a desired thickness. In this manner, a material substrate S9 having a laminated structure composed of the conductive silicon layers 31, 32, 33, and 34 and the insulating layer 35 is produced. In the material substrate S9, the thickness of the silicon layer 31 is, for example, 50 to 100 µm, and the thickness of the silicon layers 32 and 33 is, for example, 1 to 5 µm, as described above, and the silicon layer 34 The thickness of is 50-100 micrometer, for example, and the thickness of the insulating layer 35 is 0.2-2 micrometer, for example as mentioned above.

Next, as shown in FIG. 13D, the mirror surface 111 is formed on the silicon layer 31, and the electrode pads 36 for external connection on the silicon layer 34 are shown in FIGS. 1 and 2. Not shown). The formation method of the mirror surface 111 and the electrode pad 36 is the same as the formation method of the mirror surface 111 and the electrode pad 15 in 1st Embodiment, respectively.

Next, as shown in FIG. 14A, an oxide film pattern 37a is formed on the silicon layer 31, and an oxide film pattern 37b is formed on the silicon layer 34. The oxide film pattern 37a is formed of the mirror portion M, the inner frame F1, the comb-shaped electrode E1, a part of the inner frame F2 and the outer frame F3 in the material substrate S9 in the steps shown in FIGS. 14C, 15A and 15C described later. It is for masking the part processed into a part. The oxide film pattern 37b has an opening corresponding to the interval between the inner frame F2 and the outer frame F3.

Next, as shown in FIG. 14B, a resist pattern 37c is formed on the silicon layer 31. The resist pattern 37c is for masking a part of the silicon layer 31 corresponding to the part processed by the torsion bars T1 to T3 in the silicon layer 32 in the step shown in Fig. 14C below.

Next, as shown in FIG. 14C, the silicon film 31 is etched to a predetermined depth by DRIE using the oxide film pattern 37a and the resist pattern 37c as masks. The predetermined depth is appropriately determined according to the thickness of the torsion bars T1 to T3, that is, the thickness of the silicon layer 32.

This etching is anisotropic ion etching which shows the etching rate higher in the thickness direction than the in-plane direction in the silicon layer 31. FIG. After the etching process, the resist pattern 37c is peeled off.

Next, as shown in FIG. 14D, a resist pattern 37d is formed on the silicon layer 34. The resist pattern 37d is for masking a part of the silicon layer 34 corresponding to the part processed by the torsion bar T4 in the silicon layer 33 in the following step.

After the resist pattern 37d is formed, the silicon film 34 is etched to a predetermined depth by DRIE using the oxide film pattern 37b and the resist pattern 37d as masks. By this etching, the portion corresponding to the gap to be formed between the inner frame F2 (inner frame) 120 and the outer frame F3 (outer frame) 130 is removed to a predetermined depth. The predetermined depth is appropriately determined according to the thickness of the torsion bar T4, that is, the thickness of the silicon layer 33. After the etching process, the resist pattern 37d is peeled off.

Next, as shown in FIG. 15A, the etching process is performed from the side of the silicon layer 31 to the insulating layer 35 by DRIE, using the oxide film pattern 37a as a mask. This etching is anisotropic ion etching which shows the etching rate higher in the thickness direction than in-plane direction in the silicon layers 31 and 32. FIG. Thereby, there is a pair of side surfaces spaced apart in the in-plane direction of the silicon layer 32, and the pre-torsion bars Tl 'to contact with the silicon material 31a and the insulating layer 35 derived from the silicon layer 31 are provided. T3 'is formed. The pre-torsion bars T1 'to T3' are derived from the silicon layer 32. In addition, a part of the mirror portion M, the inner frame F1, the inner frame F2 and the outer frame F3 are also formed by the present etching process.

Next, as shown in FIG. 15B, the etching process is performed from the side of the silicon layer 34 to the insulating layer 35 by DRIE, using the oxide film pattern 37b as a mask. This etching is anisotropic ion etching which shows the etching rate higher in the thickness direction than the in-plane direction in the silicon layer 34. FIG. Thereby, the pre-torsion bar T4 'which has a pair of side surfaces spaced apart in the in-plane direction of the silicon layer 33, and contacts the silicon material 34a derived from the silicon layer 34, and the insulating layer 35 is formed. do. The free torsion bar T4 'is derived from the silicon layer 33. Moreover, a part of outer frame F3 is shape | molded by this etching process.

Next, as shown in FIG. 15C, the silicon materials 31a and 34a are removed by the wet etching method using the oxide film patterns 37a and 37b as masks. As etching liquid, said etching liquid for removing the silicon material 11a in 1st Embodiment can be used. As to the etching rate by the wet etching, the silicon layers 32 and 33 to the pretorsion bars Tl 'to T4' are much slower than the silicon layers 31 and 34 to the silicon materials 31a and 34a. In this case, the silicon materials 31a and 34a can be appropriately removed leaving the torsion bars T1 'to T4'.

Next, as shown in FIG. 16A, oxide films 37e and 37f are formed by forming silicon dioxide from above the oxide film patterns 37a and 37b with respect to the material substrate S9 by the CVD method. The oxide film 37e is responsible for protecting the surface of the structure formed above the figure of the insulating layer 35, and the oxide film 37f is protecting the surface of the structure formed below the figure of the insulating layer 35. In charge of.

Next, as shown in Fig. 16B, an oxide film pattern 37g is formed from a part of the oxide film 37e. The oxide film pattern 37g is for masking the part processed by the comb-tooth-shaped electrode E1 in the material substrate S9 in the process shown to FIG. 17A mentioned later.

Next, as shown in Fig. 16C, an oxide film pattern 37h is formed from a part of the oxide film 37f. The oxide film pattern 37h is for masking the part processed by the comb-tooth-shaped electrode E2 in the material substrate S9 in the process shown to FIG. 17B mentioned later.

Next, as shown in FIG. 17A, the etching process is performed from the side of the silicon layer 31 to the insulating layer 35 by DRIE using the oxide film 37e and the oxide film pattern 37g as a mask. Thereby, the comb-tooth shaped electrode E1 is shape | molded.

Next, as shown in FIG. 17B, the etching process is performed from the side of the silicon layer 34 to the insulating layer 35 by DRIE using the oxide film 37f and the oxide film pattern 37h as a mask. . Thereby, a part of comb-shaped electrode E2 and internal frame F2 are shape | molded.

Next, as shown in FIG. 17C, the portions exposed in the oxide films 37e and 37f, the oxide film patterns 37g and 37h, and the insulating layer 35 are etched and removed. By this etching, the portions of the insulating layer 35 in contact with the free torsion bars Tl 'to T4' are removed to form the torsion bars T1 to T4.

Through the above series of steps, the mirror portions M, the torsion bars T1 to T4, the inner frames Fl and F2, the comb teeth E1 and E2 and the outer frame F3 are formed. That is, the micromirror element X1 shown to FIG. 1 and FIG. 2 is manufactured.

In this embodiment, in the manufacturing process of the material substrate S7 described above with reference to FIG. 13A, the silicon layer 32 having a high precision thickness dimension can be formed. The torsion bars T1 to T3, which are thin parts of the micromirror element X1, are molded from the silicon layer 32 to the same thickness as the silicon layer 32, and thus have a high precision thickness dimension. In addition, in the manufacturing process of the material substrate S8 described above with reference to FIG. 13A, a silicon layer 33 having a high precision thickness dimension can be formed. The torsion bar T4, which is the thin part of the micromirror element X1, is molded from the silicon layer 33 to the same thickness as the silicon layer 33, and thus has a high precision thickness dimension.

The torsion bar T3 and the torsion bar T4 are formed from another conductive silicon layer which is electrically separated by the insulating layer 35. Therefore, according to this embodiment, in the micromirror element X1, the electrical connection mode by each torsion bar 151 contained in the connection part 150 is selected suitably, and each torsion bar 151 is inappropriately short-circuited. By forming a conductive path in the interior of the inner frame 120 and the outer frame 130 so as not to transfer, a plurality of potential transfers from the outer frame 130 to the inner frame 120 through the plurality of torsion bars 151. This becomes possible. Therefore, it becomes possible to individually control the magnitude of the potential to be applied to each comb-shaped electrode.

The two torsion bars 151 included in the connecting portion 150 are moved in the in-plane direction of the material substrate in the micro mirror X1 shown in FIGS. 1 and 2. The two torsion bars 151 formed by the method of the present embodiment are also moved in the thickness direction of the material substrate while being moved in the in-plane direction of the material substrate in the micromirror X1. In the present invention, the two torsion bars 151 may instead be moved only in the thickness direction of the material substrate without shifting in the in-plane direction of the material substrate in the micromirror X1.

18A to 21C show a series of steps in the method for manufacturing a microstructure according to the fourth embodiment of the present invention. This method is one technique for fabricating the aforementioned micro mirror element X2 by micromachining technology. In FIGS. 18A to 21C, the mirrored portion M, the torsion bars T1 to T4, the inner frames F1 and F2, the set of comb-shaped electrodes El, E2 and the outer frame F3 shown in FIG. The formation process is shown. As described above, the torsion bar T4 corresponds to the torsion bar 15l and is indicated by a cross section along the extending direction thereof.

In the microstructure manufacturing method according to the fourth embodiment, material substrates S10 and S11 as shown in FIG. 18A are first produced. The material substrate S10 has a laminated structure composed of the silicon layer 41, the silicon layer 42, and the oxide film 45 '. The material substrate S11 has a laminated structure composed of the silicon layer 43, the silicon layer 44, and the oxide film 45 ″.

The silicon layers 41 and 44 are made of a silicon material imparted with conductivity by doping a p-type impurity such as B or the like. The concentration of B dopant in the silicon layers 41 and 44 is, for example, 1 × 10 ^{17 to} 1 × 10 ¹⁸ atom / cm ³ . In addition, the silicon layers 41 and 44 have a crystal structure in which the (110) plane extends in the in-plane direction of the layer and has two (111) planes orthogonal to the (110) plane.

The silicon layers 42 and 43 are made of a silicon material imparted with conductivity by doping a p-type impurity such as B or the like. The silicon layer 42 has a thickness of, for example, 1 to 5 mu m, and this thickness corresponds to the thickness of the torsion bars T1 to T3. The silicon layer 43 has a thickness of, for example, 1 to 5 mu m, and this thickness corresponds to the thickness of the torsion bar T4. The concentration of the B dopant in the silicon layers 42 and 43 is higher than that of the silicon layer 21, for example, 1 × 10 ¹⁹ atom / cm ³ or more. Preferably, the dopant concentration in the silicon layers 41 and 44 is at least 100 times that of the silicon layers 41 and 44.

Material substrates S10 and S11 are produced as described above with reference to FIGS. 3A and 3B with respect to the first embodiment. Therefore, the silicon layer 42 of the material substrate S10 and the silicon layer 43 of the material substrate S11 are formed by polishing the silicon wafer until the desired thickness is obtained by the CMP method, and have a high precision thickness dimension.

In this embodiment, next, as shown in FIG. 18B, the material substrate S10 and the material substrate S11 are bonded. The material substrate S10 and the material substrate S11 are joined so that the directions of the two types of (111) surfaces in the silicon layer 41 and the directions of the two types of (111) surfaces in the silicon layer 44 coincide. Bonding of the material substrate S10 and the material substrate S11 is achieved by predetermined direct bonding through the oxide film 45 'and the oxide film 45' '. The oxide film 45 'and the oxide film 45' 'are integrated into the insulating layer 45. As shown in FIG. The thickness of the insulating layer 45 is 0.2-2 micrometers, for example.

Next, as shown in FIG. 18C, the silicon layer 41 and the silicon layer 44 are polished to a desired thickness. In this manner, a material substrate S12 having a laminated structure composed of the conductive silicon layers 41, 42, 43, and 44 and the insulating layer 45 is produced. In the material substrate S12, the thickness of the silicon layer 41 is, for example, 50 to 100 µm, and the thickness of the silicon layers 42 and 43 is, for example, 1 to 5 µm, as described above, and the silicon layer 44 Is, for example, 50 to 100 m, and the thickness of the insulating layer 45 is, for example, 0.2 to 2 m.

Next, as shown in FIG. 18D, the mirror surface 211 is formed on the silicon layer 41, and the electrode pad 46 for external connection on the silicon layer 44 (not shown in FIG. 8). Not formed). The formation method of the mirror surface 211 and the electrode pad 46 is the same as the formation method of the mirror surface 111 and the electrode pad 15 in 1st Embodiment, respectively.

Next, as shown in FIG. 19A, the oxide film pattern 47a is formed on the silicon layer 41, and the oxide film pattern 47b is formed on the silicon layer 44. Next, as shown in FIG. The oxide film pattern 47a is formed of the mirror portion M, the inner frame F1, the comb-shaped electrode E1, a part of the inner frame F2 and the outer frame F3 in the material substrate S12 in the steps shown in FIGS. 19C, 20C, and 21B described later. It is for masking the part processed into a part. The contour of the oxide film pattern 47a follows two kinds of (111) planes in the silicon crystal material constituting the silicon layer 41. The oxide film pattern 47b is used for masking locations processed by the comb-shaped electrode E2, part of the inner frame F2 and part of the outer frame F3 in the material substrate S12 in the steps shown in FIGS. 20B, 21A, and 21B described later. will be. The contour of the oxide film pattern 47b follows two kinds of (111) planes in the silicon crystal material constituting the silicon layer 44.

Next, as shown in FIG. 19B, a resist pattern 47 c is formed on the silicon layer 41. The resist pattern 47c is for masking a part of the silicon layer 41 corresponding to the part processed by the torsion bars T1 to T3 in the silicon layer 42 in the following step shown in FIG. 19C.

Next, as shown in FIG. 19C, the silicon film 41 is etched to a predetermined depth by DRIE using the oxide film pattern 47a and the resist pattern 47c as masks. This etching is anisotropic ion etching which shows the etching rate higher in the thickness direction than in-plane direction in the silicon layer 41. FIG. The predetermined depth is appropriately determined according to the thickness of the torsion bars T1 to T3, that is, the thickness of the silicon layer 42. After the etching process, the resist pattern 47c is peeled off.

Next, as shown in FIG. 20A, a resist pattern 47d is formed on the silicon layer 44. The resist pattern 47d is for masking a part of the silicon layer 44 corresponding to the portion to be processed by the torsion bar T4 in the silicon layer 43 in the next step shown in FIG. 20B.

Next, as shown in FIG. 20B, the silicon film 44 is etched to a predetermined depth by DRIE using the oxide film pattern 47b and the resist pattern 47d as a mask. This etching is anisotropic ion etching which shows the etching rate higher in the thickness direction than the in-plane direction in the silicon layer 44. FIG. The predetermined depth is appropriately determined according to the thickness of the torsion bar T4, that is, the thickness of the silicon layer 43. After the etching process, the resist pattern 47d is peeled off.

Next, as shown in FIG. 20C, the etching process is performed from the side of the silicon layer 41 to the insulating layer 45 by DRIE, using the oxide film pattern 47a as a mask. This etching is anisotropic ion etching which shows the etching rate higher in the thickness direction than in-plane direction in the silicon layers 41 and 42. FIG. Thereby, there is a pair of side surfaces spaced apart in the in-plane direction of the silicon layer 42, and the pre-torsion bars T1 'to contact the silicon material 41a derived from the silicon layer 41 and the insulating layer 45 are present. T3 'is formed. The pre-torsion bars Tl 'to T3' are derived from the silicon layer 42. Moreover, by this etching process, the mirror part M, the internal frame F1, the comb-shaped electrode E1, the part of internal frame F2, and the part of external frame F3 are also shape | molded.

Next, as shown in FIG. 21A, using the oxide film pattern 47b as a mask, an etching process is performed from the side of the silicon layer 44 to the insulating layer 45 by DRIE. This etching is anisotropic ion etching which shows the etching rate higher in thickness direction than in-plane direction in the silicon layers 43 and 44. FIG. Thereby, the pre-torsion bar T4 'having a pair of side surfaces spaced apart in the in-plane direction of the silicon layer 43, and in contact with the silicon material 44a and the insulating layer 45 derived from the silicon layer 44 is formed. Will be formed. The free torsion bar T4 'is derived from the silicon layer 43. By this etching process, comb-shaped electrode E2, a part of inner frame F2, and a part of outer frame F3 are shape | molded.

Next, as shown in FIG. 21B, the silicon materials 41a and 44a are removed by the wet etching method using the oxide film patterns 47a and 47b as masks. As etching liquid, said etching liquid for removing the silicon material 11a in 1st Embodiment can be used.

As for the etching rate by the wet etching, since the silicon layers 42 to pretorsion bars T1 'to T3' are much slower than the silicon layers 41 to silicon material 41a, the pre-torsion bar Tl 'is used in this etching process. The silicon material 21a can be appropriately removed leaving ˜T3 ′.

Similarly, with respect to the etching rate by the wet etching, since the silicon layer 43 to the pre-torsion bar T4 'are much slower than the silicon layer 44 to the silicon material 44a, the etching process leaves the pre-torsion bar T4'. The silicon material 44a can be appropriately removed.

In addition, since the side surfaces of the mirror portion M, the inner frames Fl, F2, the comb-shaped electrodes E1, E2, and the outer frame F3 are the (111) planes of silicon crystals, the etching rate in this etching process is perpendicular to the plane. Is very slow and does not unfairly erode.

Next, as shown in FIG. 21C, the portions exposed in the oxide film patterns 47a and 47b and the insulating layer 45 are etched and removed. By this etching, the portions of the insulating layer 45 in contact with the free torsion bars T1 'to T4' are removed to form the torsion bars T1 to T4.

Through the above series of steps, the mirror portions M, the torsion bars T1 to T4, the inner frames F1 and F2, the comb-shaped electrodes E1 and E2 and the outer frame F3 are formed. That is, the micro mirror element X2 shown in FIG. 8 is manufactured.

In this embodiment, in the manufacturing process of the material substrate S10 described above with reference to FIG. 18A, the silicon layer 42 having a high precision thickness dimension can be formed. The torsion bars T1 to T3, which are thin parts of the micromirror element X2, are molded from the silicon layer 42 to the same thickness as the silicon layer 42, and thus have a high precision thickness dimension. In addition, in the manufacturing process of the material substrate S11 described above with reference to FIG. 18A, a silicon layer 43 having a high precision thickness dimension can be formed. The torsion bar T4, which is the thin part of the micromirror element X2, is molded from the silicon layer 43 to the same thickness as the silicon layer 43, and thus has a high precision thickness dimension.

The torsion bar T3 and the torsion bar T4 are formed from another conductive silicon layer in which electrical separation is appropriately achieved by the insulating layer 45. Therefore, according to this embodiment, in the micromirror element X2, the electrical connection mode by each torsion bar 151 contained in the connection part 150 is selected suitably, and each torsion bar 151 is inappropriately short-circuited. By forming a conductive path in the interior of the inner frame 220 and the outer frame 230 so as not to be, thereby transferring a plurality of potentials from the outer frame 230 to the inner frame 220 through the plurality of torsion bars 151. This becomes possible. Therefore, it becomes possible to individually control the magnitude of the potential to be applied to each comb-shaped electrode.

The two torsion bars 251 included in the connecting portion 150 are moved in the in-plane direction of the material substrate in the micromirror X2 shown in FIG. 8. The two torsion bars 251 formed by the method of the present embodiment are also moved in the thickness direction of the material substrate while being moved in the in-plane direction of the material substrate in the micromirror X2. In the present invention, the two torsion bars 251 may instead be moved only in the thickness direction of the material substrate without shifting in the in-plane direction of the material substrate in the micromirror X2.

In the present embodiment, the contours of the oxide film patterns 47a and 47b for masking the locations processed by the mirror portions M, the inner frames Fl, F2, the comb-shaped electrodes El, E2, and the outer frame F3 in the material substrate S12 are the material. Two types of (111) planes present in the crystal structure of the silicon material constituting the substrate S12 are followed. Therefore, the mirror portion M, the inner frame Fl, F2, the comb-shaped electrodes E1, E2, and the outer frame F3, that is, the mirror portion (2), whose outer shape is formed by the etching process performed using the oxide film patterns 47a and 47b as masks, are formed. 210, the inner frame 220, the comb-shaped electrodes 210a, 210b, 221a, 221b, 222a, 222b, 232a, 232b, and the side of the outer frame 230 are (111) in the crystal structure of the silicon material. It is equivalent to cotton. Therefore, according to this embodiment, the micromirror element X2 which has a shape as shown in FIG. 8 can be manufactured.

22A to 26C show a series of steps in the method for manufacturing a microstructure according to the fifth embodiment of the present invention. This method is one technique for manufacturing the aforementioned micro mirror element X1 by micromachining technology.

In FIGS. 22A to 26C, mirror sections M, torsion bars T1 to T3, inner frames Fl, F2, a set of comb-shaped electrodes E1, E2, and outer frame F3 are modeled as shown in FIGS. 3A to 7D. It shows the formation process of.

In the microstructure manufacturing method according to the fifth embodiment, a material substrate S13 as shown in FIG. 22A is first produced. The material substrate S13 has a laminated structure composed of the silicon layer 51 and the silicon layer 52.

The silicon layer 51 is made of a silicon material to which conductivity is imparted by doping p-type impurities such as B, and has a thickness of, for example, 1 to 5 mu m. This thickness corresponds to the thickness of the torsion bars T1 to T3.

The silicon layer 52 is made of a silicon material imparted with conductivity by doping a p-type impurity such as B or the like. The concentration of B dopant in the silicon layer 52 is, for example, 1 × 10 ^{17 to} 1 × 10 ¹⁸ atom / cm ³ . In addition, the silicon layer 52 has a crystal structure in which the (111) plane extends in the in-plane direction of the layer.

The concentration of the B dopant in the silicon layer 51 is higher than that of the silicon layer 52, for example, 1 × 10 ¹⁹ atoms / cm ³ or more. Preferably, the dopant concentration in the silicon layer 51 is at least 100 times that of the silicon layer 52.

In the production of the material substrate S13, first, a first silicon wafer for the silicon layer 51 thicker than the silicon layer 51 and a second silicon wafer for the silicon layer 52 having the same thickness as the silicon layer 52 are formed. Join directly. In the bonding, both wafers are bonded together while physically or chemically activating the bonding surface of each wafer and continuing heating as necessary. After bonding, the first silicon wafer is polished by chemical mechanical polishing (CMP) to form a silicon layer 51 having a desired thickness. According to the CMP method, a highly accurate thickness dimension can be realized with respect to the silicon layer 51. In this way, the material substrate S13 shown in FIG. 22A is produced.

In this embodiment, next, as shown in FIG. 22B, an oxide film 54 ′ is formed on the surface of the silicon layer 52. The oxide film 54 'can be formed by forming silicon dioxide on the silicon layer 52 by CVD. Alternatively, the oxide film 54 'can be formed by oxidizing the surface of the silicon layer 52 by a thermal oxidation method (heating temperature: for example, 900 占 폚).

Next, as shown to FIG. 22C and FIG. 22D, the material substrate S13 and the separately produced material substrate S14 are bonded. The material substrate S14 is composed of a silicon layer 53 and an oxide film 54 '' made of silicon dioxide, and on one surface of the silicon wafer, a CVD method or a thermal oxidation method (heating temperature: 900 ° C, for example). Can be produced by forming the oxide film 54 ''. The thickness of the oxide film 54 '' is, for example, 0.1 to 1 mu m. The oxide film 54 'and the oxide film 54' 'are integrally formed as the insulating layer 54 as shown in Fig. 22D. The thickness of the insulating layer 54 is 0.2-2 micrometers, for example.

Next, as shown in FIG. 23A, the silicon layer 53 is polished to a desired thickness. In this way, a material substrate S15 having a laminated structure composed of the conductive silicon layers 51, 52, and 53 and the insulating layer 54 is produced. In the material substrate S15, the thickness of the silicon layer 51 is 1 to 5 mu m, for example, as described above, and the thickness of the silicon layer 52 is 50 to 100 mu m, for example, and the thickness of the silicon layer 53 The thickness is 50-100 micrometers, for example, and the thickness of the insulating layer 54 is 0.2-2 micrometers as mentioned above, for example.

Next, as shown in FIG. 23B, the protective film 53a is formed on the surface of the silicon layer 53 of the material substrate S15. The protective film 53a is made of a silicon material imparted with conductivity by doping a p-type impurity such as B, and has a thickness of 0.1 to 1 mu m, for example. The concentration of the dopant in the protective film 53a is higher than that of the silicon layer 53, for example, 1 × 10 ¹⁹ atoms / cm ³ or more. The passivation layer 53a may be formed by impurity ion implantation or impurity thermal diffusion on the surface of the silicon layer 53.

Next, as shown in FIG. 23C, holes H 'penetrating the silicon layers 51 and 52 are formed at predetermined positions of the material substrate S15. In the formation of the holes H ', a predetermined resist pattern is first formed on the silicon layer 51. This resist pattern has an opening corresponding to the formation position of the hole H '. Next, using this resist pattern as a mask, the etching process is performed from the side of the silicon layer 51 to the insulating layer 54 by DRIE.

Next, as shown in FIG. 23D, the hole H 'penetrating the insulating layer 54 in addition to the silicon layers 51 and 52 is formed by removing the portion exposed to the hole H' in the insulating layer 54. . As the removal method, wet etching or dry etching can be employed.

Next, as shown in FIG. 24A, for example, the conductive material P 'is deposited on the inside of the hole H and on the silicon layer 51 by the CVD method. As the conductive material P ', polysilicon doped with a predetermined impurity or metal such as Cu or W can be used.

Next, as shown in FIG. 24B, the conductive material P 'deposited on the silicon layer 51 is polished and removed by the CMP method. In this way, the plugs P5 and P6 embedded in the material substrate S15 are formed.

Next, as shown in FIG. 24C, the mirror surface 111 is formed on the silicon layer 51, and the electrode pad 55 for external connection (shown in FIGS. 1 and 2) on the protective film 53a. Not). The formation method of the mirror surface 111 and the electrode pad 55 is the same as the formation method of the mirror surface 111 and the electrode pad 15 in 1st Embodiment, respectively.

Next, as shown in FIG. 24D, the oxide film pattern 56a is formed on the silicon layer 51, and the oxide film pattern 56b is formed on the protective film 53a. The oxide film pattern 56a masks locations processed by the mirror portion M, the inner frame F1, the comb-shaped electrode E1, a part of the inner frame F2, and a part of the outer frame F3 in the material substrate S15 in the step shown in FIG. 26A to be described later. It is to. The oxide film pattern 56b is for masking the locations processed by the comb-shaped electrode E2, part of the inner frame F2 and part of the outer frame F3 in the material substrate S15 in the step shown in FIG. 26B described later.

Next, as shown in FIG. 25A, a resist pattern 56c is formed from above the oxide film pattern 56a with respect to the material substrate S15. The resist pattern 56c is for masking the location processed by the torsion bars T1 to T3 in the silicon layer 51 in the following step shown in FIG. 25B.

Next, as shown in FIG. 25B, the etching process is performed from the side of the silicon layer 51 to the insulating layer 54 by DRIE using the resist pattern 56c as a mask. This etching is anisotropic ion etching which shows the etching rate higher in the thickness direction than the in-plane direction in the silicon layers 51 and 52. FIG. As a result, pre-torsion bars T1 'to T3' having a pair of side surfaces spaced apart in the in-plane direction of the silicon layer 51 and in contact with the silicon layer 52 are formed. Pre-torsion bars T1'-T3 'originate in the silicon layer 51. As shown in FIG. In addition, a part of the mirror portion M, the inner frame F1, the inner frame F2 and the outer frame F3 are also formed by the present etching process. After the etching process, the resist pattern 56c is removed.

Next, as shown in FIG. 25C, the silicon layer 52 is etched by the wet etching method. As etching liquid, said etching liquid for removing the silicon material 11a in 1st Embodiment can be used. By this etching, the portions in contact with the free torsion bars T1 'to T3' in the silicon layer 52 are removed to form the torsion bars T1 to T3.

In this etching process, the etching rate for the silicon layers 51 to pretorsion bars T1 'to T3' is higher than the etching rate for the orientation other than the (111) orientation of the silicon crystal material constituting the silicon layer 52. Very slow The (111) plane of the silicon layer 52 extends in the in-plane direction. Therefore, while the pre-torsion bars Tl 'to T3' remain, the silicon layer 52 between the pre-torsion bars T1 'to T3' and the insulating layer 54 can be properly removed by etching in the lateral direction of the drawing. Can be.

The rate of etching with respect to the protective film 53a is much slower than the rate of etching with respect to the orientation other than the (111) orientation of the silicon crystal material constituting the silicon layer 52. Therefore, in this etching process, the protective film 53a can prevent the silicon layer 53 from being eroded.

Next, as shown in FIG. 25D, a protective film 56d is formed. The protective film 56d is mainly formed to protect the torsion bars T1 to T3 in the step shown in Fig. 26A, and is formed by forming silicon dioxide by the CVD method.

Next, as shown in FIG. 26A, using the oxide film pattern 56a as a mask, an etching process is performed from the side of the silicon layer 51 to the insulating layer 54 by DRIE. Thereby, the comb-tooth shaped electrode E1 is shape | molded.

Next, as shown in FIG. 26B, the etching process is performed from the side of the silicon layer 53 to the insulating layer 54 by DRIE using the oxide film pattern 56b as a mask. Thereby, the comb-tooth shaped electrode E2, a part of inner frame F2, and a part of outer frame F3 are shape | molded.

Next, as shown in FIG. 26C, the portions exposed in the oxide film patterns 56a and 56b and the insulating layer 54 are etched and removed.

Through the above series of steps, the mirror portions M, the torsion bars T1 to T3, the inner frames Fl, F2, the comb-shaped electrodes E1, E2 and the outer frame F3 are formed. That is, the micro mirror element X1 is manufactured. In this embodiment, in the manufacturing process of the material substrate S13 described above with reference to FIG. 22A, the silicon layer 51 having a high precision thickness dimension can be formed. The torsion bars T1 to T3, which are thin parts of the micromirror element X1, are molded from the silicon layer 51 to the same thickness as the silicon layer 51, and thus have a high precision thickness dimension.

The mirror part M formed in this embodiment has the site | part which originates in the silicon layer 51, and continues to the torsion bar T1, and the site | part which originates in the silicon layer 52, These two site | parts have electroconductivity. The inner frame F1 has a portion derived from the silicon layer 51 and continuous to the torsion bar T1, and a portion derived from the silicon layer 52, and these two portions have conductivity. Therefore, the mirror portion M (mirror portion) 110 and the inner frame F1 (inner frame) 120 are electrically connected through the torsion bar Tl (torsion bar) 1141.

In addition, the inner frame F2 has a portion derived from the silicon layer 11 and continuous to the torsion bar T3, a portion derived from the silicon layer 52, and a portion derived from the silicon layer 53. These three sites have conductivity and are electrically connected through the plug P5. The outer frame F3 has a portion derived from the silicon layer 51 and continuous to the torsion bar T3, a portion derived from the silicon layer 52, and a portion derived from the silicon layer 53. These three sites have conductivity and are electrically connected through the plug P6. Therefore, the portion derived from the silicon layer 53 in the inner frame F2 (inner frame) 120 and the portion derived from the silicon layer 53 in the outer frame F3 (outer frame; 130) have a torsion bar T3 ( It is electrically connected via a torsion bar 151.

In this embodiment, another aspect can also be comprised by not providing plug P5 or plug P6 about the electrical connection between inner frame F2 and outer frame F3. For example, when plug P5 is not provided, the portion derived from the silicon layer 53 in the inner frame F2 and the portion derived from the silicon layer 53 in the outer frame F3 can be electrically separated.

In the micro-mirror element Xl manufactured by the method of this embodiment, the electrical connection mode by each torsion bar 151 included in the connection part 150 is selected suitably, and each torsion bar 151 is improperly selected. By forming a conductive path inside the inner frame 120 and the outer frame 130 so as not to be shorted, a plurality of potentials through the plurality of torsion bars 151 from the outer frame 130 to the inner frame 120. Delivery is possible. Therefore, it becomes possible to individually control the magnitude of the potential to be applied to each comb-shaped electrode.

27A to 31C show a series of steps in the method for manufacturing a microstructure according to the sixth embodiment of the present invention. This method is one technique for manufacturing the aforementioned micro mirror element X1 by micromachining technology.

In Figs. 27A to 31C, as shown in Figs. 3A to 7D, the mirror section M, the torsion bars T1 to T3, the internal frames Fl and F2, a set of comb-shaped electrodes El, E2, and the like are modeled in one cross section. The formation process of the outer frame F3 is shown.

In the microstructure manufacturing method according to the sixth embodiment, a material substrate S16 as shown in FIG. 27A is first prepared. The material substrate S16 has a laminated structure composed of the silicon layer 6l, the silicon layer 62, and the insulating layer 63.

The silicon layers 61 and 62 are made of a silicon material imparted with conductivity by doping p-type impurities such as B, and have a thickness of, for example, 50 to 100 µm. The concentration of B dopant in the silicon layers 61 and 62 is, for example, 1 × 10 ^{17 to} 1 × 10 ¹⁸ atom / cm ³ . In addition, the silicon layer 61 has a crystal structure in which the (111) plane extends in the in-plane direction of the layer.

Next, as shown in FIG. 27B, a hole H 'penetrating the silicon layer 61 is formed at a predetermined position of the material substrate S16. In the formation of the holes H ', first, a predetermined resist pattern is formed on the silicon layer 61. This resist pattern has an opening corresponding to the formation position of the hole H '. Next, using this resist pattern as a mask, the etching process is performed from the side of the silicon layer 61 to the insulating layer 63 by DRIE.

Next, as shown in FIG. 27C, the hole H penetrating the insulating layer 63 in addition to the silicon layer 61 is formed by removing the portion exposed to the hole H 'in the insulating layer 63. As the removal method, wet etching or dry etching can be employed.

Next, as shown in Fig. 27D, for example, the conductive material P 'is deposited on the inside of the hole H and on the silicon layer 61 by the CVD method. As the conductive material P ', polysilicon doped with predetermined impurities or a metal such as Cu or W can be used.

Next, as shown in FIG. 28A, the conductive material P 'deposited on the silicon layer 61 is polished and removed by the CMP method. In this manner, plugs P7 and P8 embedded in the material substrate S16 are formed.

Next, as shown in FIG. 28B, an oxide film pattern 66a is formed on the silicon layer 6l. The oxide film pattern 66a is processed at the material substrate S16 by the mirror portion M, the torsion bars T1 to T3, the inner frame F1, a part of the inner frame F2 and a part of the outer frame F3 in the step shown in FIG. 28C. To mask.

Next, as shown in FIG. 28C, the silicon film 61 is etched to a predetermined depth by DRIE using the oxide film pattern 66a as a mask. The predetermined depth is appropriately determined according to the thicknesses of the torsion bars T1 to T3 to be formed. This etching is anisotropic ion etching which shows the etching rate higher in the thickness direction than the in-plane direction in the silicon layer 61. FIG. After the etching treatment, the oxide film pattern 66a is removed.

Next, as shown in FIG. 28D, the protective films 61a and 62a are formed on the surfaces of the silicon layers 61 and 62. The protective films 61a and 62a are made of a silicon material imparted with conductivity by doping p-type impurities such as B, and have a thickness of, for example, 0.1 to 1 mu m. The concentration of the dopant in the protective films 61a and 62a is higher than that of the silicon layers 61 and 62, for example, 1 × 10 ¹⁹ atom / cm ³ or more. The protective layers 61a and 62a may be formed by impurity thermal diffusion on the surfaces of the silicon layers 61 and 62.

Next, as shown in FIG. 29A, the mirror surface 111 is formed on the protective film 61a, and the electrode pad 65 (not shown in FIG. 1 and FIG. 2) for external connection is formed on the protective film 62a. To form. The formation method of the mirror surface 111 and the electrode pad 65 is the same as the formation method of the mirror surface 111 and the electrode pad 15 in 1st Embodiment, respectively.

Next, as shown in FIG. 29B, the oxide film pattern 66b is formed from above the mirror portion 111 with respect to the material substrate S16, and the oxide film pattern 66c is formed from above the electrode pad 65. The oxide film pattern 66b masks locations processed by the mirror portion M, the inner frame F1, the comb-shaped electrode E1, a part of the inner frame F2, and a part of the outer frame F3 in the material substrate S16 in the step shown in FIG. 30C to be described later. It is to. The oxide film pattern 66c is for masking the part processed by the comb-tooth-shaped electrode E2, a part of the inner frame F2, and a part of the outer frame F3 in the material substrate S16 in the process shown to FIG. 31B mentioned later.

Next, as shown in FIG. 29C, the resist pattern 66d is formed from above the oxide film pattern 66b with respect to the material substrate S16. The resist pattern 66d is for masking the locations processed by the torsion bars T1 to T3 in the silicon layer 61 in the following steps shown in FIG. 30A.

Next, as shown in FIG. 30A, using the resist pattern 66d as a mask, an etching process is performed from the side of the silicon layer 61 to the insulating layer 63 by DRIE. This etching is anisotropic ion etching which shows the etching rate higher in the thickness direction than the in-plane direction in the silicon layer 61. FIG. As a result, side surfaces of the torsion bars T1 to T3 are formed. In addition, a part of the mirror portion M, the inner frame F1, the inner frame F2 and a portion of the outer frame F3 are also formed by this etching process. After the etching process, the resist pattern 66d is removed.

Next, as shown in FIG. 30B, an etching process is performed on the silicon layer 61 by the wet etching method. As etching liquid, said etching liquid for removing the silicon material 11a in 1st Embodiment can be used.

In this etching process, the etching rate to the protective film 61a is much slower than the etching rate to the orientation other than the (111) orientation of the silicon crystal material constituting the silicon layer 61. The (111) plane of the silicon layer 61 extends in the in-plane direction. Therefore, the protective film 61a functions as a wet etching stop film, and the etching liquid erodes the silicon material between the portion to be processed by the torsion bars Tl to T3 in the silicon layer 61 and the insulating layer 63 in the horizontal direction in the drawing. By appropriately removing them. The (111) surface of the silicon crystal material constituting the silicon layer 61 has an etching stop function in a direction perpendicular thereto. As a result, in this etching process, torsion bars T1 to T3 are appropriately formed.

In addition, the etching rate with respect to the protective film 62a is much slower than the etching rate with respect to orientation other than the (111) orientation of the silicon crystal material which comprises the silicon layer 61. FIG. Therefore, in the present etching process, the protective film 62a can prevent the silicon layer 62 from eroding.

Next, as shown in FIG. 30C, a protective film 66e is formed. The protective film 66e is mainly for protecting the torsion bars T1 to T3 in the following step shown in Fig. 31A, and is formed by forming silicon dioxide by the CVD method.

Next, as shown in FIG. 31A, using the oxide film pattern 66b as a mask, an etching process is performed from the side of the silicon layer 61 to the insulating layer 63 by DRIE. Thereby, the comb-tooth shaped electrode E1 is shape | molded.

Next, as shown in FIG. 31B, the etching process is performed from the side of the silicon layer 62 to the insulating layer 63 by DRIE, using the oxide film pattern 66c as a mask. Thereby, the comb-tooth shaped electrode E2, a part of inner frame F2, and a part of outer frame F3 are shape | molded.

Next, as shown in FIG. 31C, the portions exposed in the oxide film patterns 66b and 66c, the protective film 66e, and the insulating layer 63 are etched and removed.

In this embodiment, the silicon material can be etched out with high precision to a depth corresponding to the thickness of the torsion bars T1 to T3 to be formed in the etching process for the silicon layer 61 described above with reference to FIG. 28C. This is because the etching depth in the etching treatment is relatively shallow. The torsion bars T1 to T3, which are the thin parts of the micromirror element X1, are defined by etching with high precision with respect to the depth dimension, and therefore have a high precision thickness dimension.

The mirror part M formed in this embodiment has the site | part which originates in the silicon layer 61, and is continuous to torsion bar T1, and the inner frame F1 is the site | part which originates in the silicon layer 61 and is continuous to torsion bar T1 These two sites have conductivity. Therefore, the mirror portion M (mirror portion) 110 and the inner frame Fl (inner frame) 120 are electrically connected through the torsion bar Tl (torsion bar) 141.

In addition, the inner frame F2 has a portion derived from the silicon layer 61 and continuous to the torsion bar T3 and a portion derived from the silicon layer 62. These two sites have conductivity and are electrically connected through the plug P7. The outer frame F3 has a portion derived from the silicon layer 61 and continuous to the torsion bar T3 and a portion derived from the silicon layer 62. These two sites have conductivity and are electrically connected through the plug P8. Therefore, the inner frame F2 (inner frame) 120 and the outer frame F3 (outer frame) 130 are electrically connected through the torsion bar T3 (torsion bar) 151.

In this embodiment, another aspect can also be comprised by not providing plug P7 or plug P8 about the electrical connection between inner frame F2 and outer frame F3. For example, when plug P7 is not provided, the portion derived from the silicon layer 62 in the inner frame F2 and the portion derived from the silicon layer 62 in the outer frame F3 can be electrically separated.

In the micro-mirror element X1 manufactured by the method of this embodiment, the electrical connection mode by each torsion bar 151 contained in the connection part 150 is selected suitably, and each torsion bar 151 is improperly selected. By forming a conductive path inside the inner frame 120 and the outer frame 130 so as not to be shorted, a plurality of potentials through the plurality of torsion bars 151 from the outer frame 130 to the inner frame 120. Delivery is possible. In other words, it is possible to individually control the magnitude of the potential to be applied to each comb-shaped electrode.

Claims (32)

A method for producing a microstructure having thin parts, A material substrate comprising a laminated structure comprising a first conductor layer and a second conductor layer having a thickness corresponding to the thickness of the thin portion and being in contact with the first conductor layer and having a lower etching speed than the first conductor layer. In the second conductor layer, a first etching process is performed from the side of the first conductor layer, and the first conductor layer is etched so that a part of the first conductor layer remains in a portion corresponding to the thin portion. And a step for forming pre-thin parts having a pair of side surfaces spaced apart in the in-plane direction of the second conductor layer and in contact with the first conductor layer, A step for forming a thin portion by removing a portion remaining in the free thin portion in the first conductor layer by a second etching treatment from the side of the first conductor layer. Method for producing a microstructure comprising a. The method of manufacturing a microstructure according to claim 1, wherein the first etching treatment is anisotropic reactive ion etching that exhibits an etching rate faster in the thickness direction than the in-plane direction in the first conductor layer and the second conductor layer. The method for producing a microstructure according to claim 1, wherein the second etching treatment is wet etching that exhibits an etching rate faster in the first conductor layer than the second conductor layer. The microstructure of claim 3, wherein the first conductor layer and the second conductor layer are made of a conductive silicon material, and the dopant concentration in the second conductor layer is higher than the dopant concentration in the first conductor layer. Way. The silicon of claim 1, wherein the first conductor layer has a (110) plane extending in the in-plane direction of the first conductor layer and two (111) planes orthogonal to the (110) plane. A method for producing a microstructure made of a material. As a method for manufacturing a microstructure having a thin portion, A second conductor layer, a third conductor layer having a thickness corresponding to a thickness of the first conductor layer, the thin portion, and in contact with the first conductor layer, and having a lower etching speed than the first conductor layer; 1st mask pattern which has a site | part for masking the location processed into the thick part in the said material board | substrate with respect to the material substrate containing the laminated structure which consists of an insulating layer between a 2nd conductor layer and a 3rd conductor layer, and said 2nd The said 1st conductor layer by performing a 1st etching process from the side of the said 1st conductor layer through the 2nd mask pattern for masking a part of 1st conductor layer corresponding to the part processed into a thin part in a conductor layer. A process for etching a portion which is not covered by the first mask pattern and the second mask pattern, After removing the second mask pattern, a second etching process is performed on the material substrate from the side of the first conductor layer through the first mask pattern, and covered by the first mask pattern in the first conductor layer. Etching a portion that is not formed, to form a free thin portion in the second conductor layer, which has a pair of side surfaces spaced apart in the in-plane direction of the second conductor layer and contacts the first conductor layer and the insulating layer. Fair, A step for removing a portion remaining in the free thin portion in the first conductor layer by a third etching treatment from the side of the first conductor layer, Process for forming a thin part by removing the part corresponding to the said free thin part at least among the said insulating layers by a 4th etching process. Method for producing a microstructure comprising a. The method of manufacturing a microstructure according to claim 6, wherein the second etching treatment is anisotropic reactive ion etching that exhibits an etching rate faster in the thickness direction than the in-plane direction in the first conductor layer and the second conductor layer. The method of manufacturing a microstructure of claim 6, wherein the third etching process is wet etching that exhibits an etching rate faster in the first conductor layer than the second conductor layer. The microstructure of claim 8, wherein the first conductor layer and the second conductor layer are made of a conductive silicon material, and the dopant concentration in the second conductor layer is higher than the dopant concentration in the first conductor layer. Way. The crystal of claim 6, wherein the first conductor layer has a (110) plane extending in an in-plane direction of the first conductor layer and two (111) planes that are perpendicular to and intersect with the (110) plane. A method for producing a microstructure, comprising a silicon material having a structure, wherein at least part of the contour of the first mask pattern is along the two (11l) planes. The said 3rd conductor layer is parallel to one of the (110) surface which extends in the in-plane direction of the said 3rd conductor layer, and the said 2 (111) surfaces in a said 1st conductor layer. Furthermore, the manufacturing method of the microstructure which consists of a silicon material which has the crystal structure which has two (111) planes mutually crossing each other. The method of claim 6, Before performing the first etching process, the material substrate is passed through the first conductor layer, the second conductor layer, and the insulating layer by the etching process from the side of the first conductor layer. A method for producing a microstructure, further comprising a step for forming a hole reaching the three conductor layers and a step for forming a conductive contact portion by filling the hole with a conductive material. A method for manufacturing a microstructure having a first thin portion and a second thin portion, A first conductor layer, a second conductor layer having a thickness corresponding to the thickness of the first thin portion, and in contact with the first conductor layer and having a lower etching speed than the first conductor layer; and the second thin portion Between the third conductor layer having a thickness corresponding to the thickness, the fourth conductor layer in contact with the third conductor layer and having a faster etching rate than the third conductor layer, and between the second conductor layer and the third conductor layer. A first mask pattern having a portion for masking a portion to be processed into a thick portion in the material substrate and a first thin film portion in the second conductor layer with respect to a material substrate including a laminated structure composed of an insulating layer of The first mask pattern in the first conductor layer is formed by performing a first etching process from the side of the first conductor layer through a second mask pattern for masking a part of the first conductor layer corresponding to the point to be formed. Second mask A process for etching a portion not covered by the pattern, A third mask pattern having a portion for masking a portion to be processed into a thick portion on the material substrate, and a fourth conductor layer corresponding to the portion to be processed into the second thin portion from the third conductor layer, with respect to the material substrate. The second etching process is performed from the side of the fourth conductor layer through a fourth mask pattern for masking a portion of the fourth conductor layer, thereby being covered with the third mask pattern and the fourth mask pattern among the fourth conductor layers. To etch away the untreated portion, After removing the second mask pattern, a third etching process is performed on the material substrate from the side of the first conductor layer through the first mask pattern, and covered by the first mask pattern among the first conductor layers. By etching the portion that is not, a first free thin portion having a pair of side surfaces spaced apart in the in-plane direction of the second conductor layer and contacting the first conductor layer and the insulating layer is formed in the second conductor layer. Process to do, After removing the fourth mask pattern, a fourth etching process is performed on the material substrate from the side of the fourth conductor layer through the third mask pattern, and covered by the third mask pattern among the fourth conductor layers. By etching the portion that is not, a second free thin portion is formed in the third conductor layer, which has a pair of side surfaces spaced apart in the in-plane direction of the third conductor layer and contacts the fourth conductor layer and the insulating layer. Process to do, A process for removing a portion remaining in the first free thin portion in the first conductor layer and removing a portion remaining in the second free thin portion in the fourth conductor layer by a fifth etching process; , A step for forming a first thin portion and a second thin portion by removing a portion corresponding to at least the first free thin portion and the second free thin portion from the insulating layer by a sixth etching process. Method for producing a microstructure comprising a. The said 3rd etching process is anisotropic reactive ion etching which shows the etching rate which is faster in a thickness direction than the in-plane direction in the said 1st conductor layer and the said 2nd conductor layer, The said 4th etching process is a said 1st etching process 4 A method for producing a microstructure, wherein the conductor layer and the third conductor layer are anisotropic reactive ion etching exhibiting an etching rate faster in the thickness direction than in the in-plane direction. The microstructure according to claim 13, wherein the fifth etching process is wet etching that exhibits an etching rate faster in the first conductor layer than the second conductor layer and also shows an etching rate faster in the fourth conductor layer than the third conductor layer. Method of preparation. The said 1st conductor layer, the said 2nd conductor layer, the said 3rd conductor layer, and the said 4th conductor layer are a conductive silicon material, The dopant density | concentration in the said 2nd conductor layer is the said 1st conductor layer. A method for producing a microstructure, wherein the dopant concentration in the conductor layer is higher than the dopant concentration in the third conductor layer and higher than the dopant concentration in the fourth conductor layer. The first conductor layer has a (110) plane extending in the in-plane direction of the first conductor layer and two (111) planes perpendicular to and intersecting with the (110) plane. A method for producing a microstructure, comprising a silicon material having a crystal structure, wherein at least part of the contour of the first mask pattern is along the two (111) planes. 18. The method of claim 17, wherein the fourth conductor layer is parallel to either one of the (110) planes extending in the in-plane direction of the fourth conductor layer and the two (111) planes of the first conductor layer. It is also made of a silicon material having a crystal structure having two (111) planes intersecting with each other, wherein at least a part of the contour of the third mask pattern is microscopic along the two (111) planes in the fourth conductor layer. Method of making a structure. As a method for manufacturing a microstructure having a thin portion, About a material substrate containing a laminated structure which consists of a 1st conductor layer which has a thickness corresponded to the thickness of the said thin part, and a 2nd conductor layer which contact | connects the said 1st conductor layer, and whose etching rate is faster than this 1st conductor layer, A first etching process is performed from the side of the first conductor layer through a mask pattern for masking a portion processed from the first conductor layer to the thin portion, and the mask pattern among the first conductor layer and the second conductor layer is Etching the portion not covered by the step to form a free thin portion in the first conductor layer that has a pair of side surfaces spaced apart in the in-plane direction of the first conductor layer and in contact with the second conductor layer. and, Process for removing the site | part which remain | survives in the said free thin part in the said 2nd conductor layer by the 2nd etching process from the side of a said 1st conductor layer. Method for producing a microstructure comprising a. 20. The method of manufacturing a microstructure according to claim 19, wherein the second etching process is wet etching showing an etching rate faster in the second conductor layer than in the first conductor layer. 21. The method of claim 20, wherein the first conductor layer and the second conductor layer are made of a conductive silicon material, and the dopant concentration in the first conductor layer is higher than the dopant concentration in the second conductor layer. Way. The method of manufacturing a microstructure according to claim 19, wherein the second conductor layer is made of a silicon material having a crystal structure having a (111) plane extending in the in-plane direction of the second conductor layer.  The said material substrate is an insulating layer which contact | connects the said 2nd conductor layer in the side opposite to the said 1st conductor layer, and the 3rd contacting this insulation layer in the side opposite to the said 2nd conductor layer. The manufacturing method of the microstructure which has a laminated structure which further contains a conductor layer. The method of claim 23, wherein Before performing the first etching process, the third substrate passes through the first conductor layer, the second conductor layer, and the insulating layer by the etching process from the side of the first conductor layer on the material substrate. And a step for forming a hole reaching the conductor layer, and a step for forming a conductive contact portion by filling the hole with a conductive material.       As a method for manufacturing a microstructure having a thin portion,      The part processed into the thin part in the said 1st conductor layer with respect to the material board | substrate which has a laminated structure which consists of a 1st conductor layer, a 2nd conductor layer, and the insulating layer between the said 1st conductor layer and a 2nd conductor layer. In-plane direction of the first conductor layer in the first conductor layer by performing a first etching process from the side of the first conductor layer to the middle of the insulating layer through a first mask pattern having a portion for masking. A process for forming a free thin portion having a pair of side surfaces spaced by A step for forming a wet etching stop film having a lower etching speed than the first conductor layer on the surface of the first conductor layer including the free thin portion; Performing a second etching treatment from the side of the first conductor layer to the insulating layer through a second mask pattern having a portion for masking the free thin portion by dry etching; Process for removing the location interposed between the free thin part and the insulating layer in the first conductor layer by wet etching. Method for producing a microstructure comprising a. 27. The microstructure of claim 25, wherein the first conductor layer and the wet etch stop film are made of a conductive silicon material, and the dopant concentration in the wet etch stop film is higher than the dopant concentration in the first conductor layer. Way. The method for producing a microstructure according to claim 25, wherein the first conductor layer is made of a silicon material having a crystal structure having a (111) plane extending in the in-plane direction of the first conductor layer. The method of claim 25, Before performing the first etching process, holes in the material substrate are formed through the first conductor layer and the insulating layer to reach the second conductor layer by etching from the side of the first conductor layer. And a step for forming the conductive contact portion by filling the hole with a conductive material. delete delete delete delete

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