KR100818087B1 - Circuit For Adjusting Delay using Anti-Fuse - Google Patents

Abstract

The present invention discloses a technique for securing a domain crossing margin of a packaged memory chip by controlling delay using antifuse.

 The present invention includes a plurality of delay adjusters for receiving a fuse selection signal and a test mode signal and enabling a delay control signal, and a delay unit for delaying and outputting an input signal according to the delay control signal.

Description

Circuit For Adjusting Delay using Anti-Fuse

1 is a block diagram of a delay control circuit using an anti-fuse according to an embodiment of the present invention;

2 is a detailed circuit diagram of a delay adjusting unit of FIG. 1;

3 is a detailed circuit diagram of a delay unit of FIG. 1;

4 is an operation timing diagram of the delay controller of FIG. 2.

The present invention relates to a delay control circuit using an antifuse, and more particularly, to a technique for securing a domain crossing margin of a packaged memory chip by adjusting a delay using an antifuse.

In general, as a semiconductor memory device gradually performs an operation in synchronization with a clock, a clock is generated when an internal clock is generated and an output result of such an operation is received in response to a command and data applied in synchronization with an external clock. Problems have arisen due to motivation.

The semiconductor memory device is largely divided into two parts according to a clock used to perform its operation, that is, an internal clock synchronization part that performs an operation in synchronization with an internal clock, and a DL that performs an operation in synchronization with a DL clock (DLL CLK). It can be divided into motive part.

In the internal clock synchronizing portion, data and commands synchronized to the external clock are inputted in synchronization with the internal clock to perform an operation. Therefore, a signal synchronized with the external clock undergoes a conversion synchronized with the internal clock.

On the other hand, the DL synchronization part outputs the signals DQ and DQS using a DL clock considering internal delay in advance so that the execution result signal of the internal clock synchronization part is synchronized to the external clock at the final output. The signal synchronized with the clock undergoes a conversion synchronized with the DL clock. As described above, domain crossing is a change in a clock that is synchronized from the standpoint of a signal, and a change in a reference clock that performs an operation on the device side.

On the other hand, a domain crossing problem may occur in a memory chip operating at a high frequency. In a packaged memory chip, it is impossible to modify a circuit using fuse trimming or equipment. Therefore, an additional circuit revision is inevitably required, causing a loss of time and economics.

Accordingly, the present invention has been made to solve the above problems, and an object thereof is to secure a domain crossing margin of a packaged memory chip by adjusting a delay using an anti-fuse.

In order to achieve the above object, the present invention includes a plurality of delay control unit for receiving a fuse selection signal and a test mode signal to enable a delay control signal and a delay unit for delaying and outputting an input signal according to the delay control signal. .

The delay control unit may include a delay control signal enable unit configured to enable and output the delay control signal when the test mode signal is enabled.

The delay control unit may include a delay control signal enable unit, an anti-fuse, and a fuse select signal and a test mode signal that apply the delay control signal to a power supply voltage level when the fuse select signal and the test mode signal are enabled. And a switching unit for shorting the anti-fuse to transition the delay control signal to a "low" level.

The delay control signal enable unit may include a NAND gate that receives the fuse selection signal and the test mode signal, and applies the delay control signal to a power supply voltage level according to an output signal of the NAND gate. A first NMOS transistor and a drain having an output signal of a gate applied to a gate and an output signal of the transfer gate applied to a drain are connected to a source of the first NMOS transistor, a test mode signal is applied to a gate, and a ground voltage is applied to the source. This includes a second NMOS transistor to be applied.

In addition, the anti-fuse is a dielectric is sandwiched between the conductors, it is preferable that the short circuit is shorted by the back bias voltage and the power supply voltage that changes when the fuse selection signal and the test mode signal is enabled at both ends.

The switching unit is connected between the delay control signal enable unit output and the anti-fuse, the back bias voltage is applied to the bulk and the PMOS transistor to which the ground power is applied to the gate, and the operating voltage is applied to the gate. A drain includes a third NMOS transistor connected to the drain and the source of the PMOS transistor, respectively.

The delay control unit may further include an initialization unit configured to receive a power-up signal to initialize an output terminal of the delay control signal enable unit.

The delay control unit may further include a latch unit configured to latch and output an output signal of the delay control signal enable unit.

The delay unit may include a first path through which an input signal is transmitted when the delay control signal is enabled and a second path through which an input signal is transmitted when the delay control signal is disabled, wherein the first path and the second path are transmitted. One of them includes delay means for delaying the input signal.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a delay control circuit using an anti-fuse according to an embodiment of the present invention. As shown in FIG. 1, a delay control circuit using an anti-fuse according to an embodiment of the present invention includes a plurality of delay adjusters 100 and delay units 200.

The delay adjuster 100 receives a power-up signal PWRUP, a fuse select signal FUSE1 to FUSE4, a test mode signal TM_ANTIFUSE, a back bias voltage VBBF, and an operating voltage VBBA. Enable ANTI ~ ANTI4).

The delay unit 200 adjusts the delay of the input signal IN according to the delay control signals ANTI1 to ANTI4 of the plurality of delay adjustment units 100 to output the OUT. The input signal of the delay unit 100 is preferably a signal operating in the DL clock domain.

FIG. 2 is a detailed circuit diagram of the delay adjuster of FIG. 1. As shown in FIG. 2, the delay adjusting unit 100 includes an initialization unit 110, a delay control signal enable unit 120, an antifuse 130, a switching unit 140, and a latch unit 150. do.

The initialization unit 110 receives a power-up signal PWRUP to initialize the state of the delay adjusting unit 100. The initialization unit 110 receives the power-up signal PWRUP and receives the outputs of the inverter INV1 and the inverter INV1 for inverting the phase and outputs the gates, and receives the power supply voltage VDD as the source and delays them. The PMOS transistor P1 has a drain connected to the output terminal (node A) of the control signal enable unit 120.

The delay control signal enable unit 120 receives the fuse selection signal FUSE1 and the test mode signal TM_ANTIFUSE to ground the output terminal (node A) of the delay control signal enable 120 or short-circuits the anti-fuse. (short) makes node A low.

The delay control signal enable unit 120 receives a fuse selection signal FUSE1 and a test mode signal TM_ANTIFUSE and receives a power supply voltage to the node A according to the output signals of the NAND gate ND and the NAND gate ND. The NMOS transistor N1 and the drain of which the output signal of the transfer gate TG, the NAND gate ND are applied to the gate, and the output signal of the transfer gate TG are applied to the drain, and the source of the NMOS transistor N1 are drained. The NMOS transistor N2 is connected to the gate, the test mode signal TM_ANTIFUSE is applied to the gate, and the ground voltage VSS is applied to the source.

The antifuse 130 may be shorted and programmed by a voltage difference between the node B and the back bias voltage VBBF changed according to the fuse select signal FUSE1 and the test mode signal TM_ANTIFUSE.

The anti-fuse 130 is a resistive fuse device positioned between the back bias voltage (VBBF) applying stage and the switching unit 140. The anti-fuse 130 includes a dielectric such as an oxide-nitride-oxide (ONO), and a high voltage across both conductors. When applied, the dielectric is broken and shorted.

The switching unit 140 is connected between the node A and the anti-fuse 130, and is connected between the PMOS transistor P4 and the node A and the anti-fuse 130 to which the ground voltage VSS is applied to the gate. And an NMOS transistor N5 to which a back bias voltage VBBF is applied and an operating voltage VBBA is applied to the gate.

The latch unit 150 latches a signal applied to an output terminal of the delay control signal enable unit 120 and outputs the delay control signal ANTI1. The latch unit 150 includes an inverter INV2 connected to the input terminal and an inverter INV3 and INV4 connected to the output terminal in a structure in which the PMOS transistors P5 and P6 and the NMOS transistors N4 and N5 are coupled to each other. can do.

3 is a detailed circuit diagram of a delay unit of FIG. 1. As shown in FIG. 3, the delay unit outputs the first delay unit 210, the delay control signal ANTI2, and the first delay unit 210 to receive the delay control signal ANTI1 and the input signal IN. The second delay unit 220, the delay control signal ANTI3 and the second delay unit 220 receiving the output signal of the second delay unit 220, the delay control signal ANTI4 and the third delay unit And a fourth delay unit 240 for receiving the output signal 230 and outputting the output signal as the output signal OUT.

The first delay unit 210 includes a NAND gate ND2 for performing a NAND operation on the delay control signal ANTI1 inverted by the input signal IN and the inverter INV5, the input signal IN, and the delay control signal ANTI1. NAND gates ND1 for NAND operation, NAND outputs of the plurality of inverters INV6, INV7, INV8, INV9 and NAND gate ND2 that delay the output of the NAND gate ND1, and the output of the inverter INV9. It includes a NAND gate ND3 to operate.

The second delay unit 220 includes a NAND gate ND5 and a first delay unit NAND for performing an NAND operation on the output signal of the first delay unit 210 and the delay control signal ANTI2 inverted by the inverter INV10. NAND gate ND4 for NAND operation of the output signal and delay control signal ANTI2, a plurality of inverters INV11, INV12, INV13, INV14, and NAND gate ND5 for delaying the output of the NAND gate ND4. And a NAND gate ND6 for NAND operation of the output of the inverter and the output of the inverter INV14.

The third delay unit 230 includes a NAND gate ND8 and a second delay unit 220 that NAND the output signal of the second delay unit 220 and the delay control signal ANTI3 inverted by the inverter INV15. NAND gate ND7 for NAND operation of the output signal and delay control signal ANTI3, and a plurality of inverters INV16, INV17, INV18, INV19 and NAND gate ND7 for delaying the output of the NAND gate ND8. And a NAND gate ND9 for NAND-operating the output and the output of the inverter INV19.

The fourth delay unit 240 includes a NAND gate ND11 and a third delay unit NAND for outputting the output signal of the third delay unit 230 and the delay control signal ANTI4 inverted by the inverter INV20. NAND gate ND10 for NAND operation of the output signal and delay control signal ANTI4, and a plurality of inverters INV21, INV22, INV23, INV24 and NAND gate ND10 for delaying the output of the NAND gate ND11. And a NAND gate ND12 for NAND-operating the output and the output of the inverter INV24 to output the output signal OUT.

Hereinafter, the operation of the delay control circuit using the anti-fuse according to an embodiment of the present invention.

First, the operation of the delay controller will be described with reference to FIG. 4, which is an operation timing diagram of the delay controller. The delay controller 100 may operate in three modes, A mode, B mode, and C mode, depending on the state of the fuse selection signal FUSE1 and the test mode signal TM_ANTIFUSE.

The A mode is a mode in which the delay controller 100 operates normally when the fuse select signal FUSE1 is "low" and the test mode signal TM_ANTIFUSE is "low". When the power-up signal PWRUP is applied, the PMOS transistor P1 is turned on to initialize the node A to the power supply voltage VDD level.

Since the fuse select signal FUSE1 is "low" and the test mode signal TM_ANTIFUSE is "low", the output of the NAND gate ND becomes "high". At this time, the transfer gate TG is turned off, the NMOS transistor N1 is turned on, and the NMOS transistor N2 is turned off. In addition, the back bias voltage VBBF is supplied at the ground voltage VSS level, and the operating voltage VBBA is supplied with a power supply voltage VDD capable of turning on the NMOS transistor N5.

However, since the voltage difference applied across the anti-fuse 130 does not reach a voltage that may short-circuit the anti-fuse 130, the node A is maintained in a "high" state and is delayed through the latch unit 150. The control signal ANTI1 is output as "high".

If the user encounters a domain crossing margin problem in the semiconductor memory when operating in the A mode, that is, the normal mode, the B mode operation, which will be described below, can identify an appropriate amount of delay to be set by the anti-fuse operation. .

The B mode is a mode in which the delay controller 100 performs a test operation when the fuse select signal FUSE1 is "low" and the test mode signal TM_ANTIFUSE is "high". When the power-up signal PWRUP is applied, the PMOS transistor P1 is turned on to initialize the node A to the power supply voltage VDD level.

Since the fuse select signal FUSE1 is "low" and the test mode signal TM_ANTIFUSE is "high", the output of the NAND gate ND becomes "high". At this time, the transfer gate TG is turned off, the NMOS transistor N1 is turned on, and the NMOS transistor N2 is turned on. Therefore, the potential level of the node A is connected to the ground power supply VSS through the NMOS transistor N1 and the NMOS transistor N2, and thus has a "low" level. The latch unit 150 latches the potential level of the node A and outputs a delay control signal ANTI1 having a "low" level.

In the B mode, the back bias voltage VBBF and the operating voltage VBBA are the same as in the A mode. That is, in the B mode, the delay control signal ANTI1 having the same "low" level as the shorted anti-fuse 130 can be output without shorting the anti-fuse 130.

The user may fix the anti-fuse short-circuit through the C-mode operation to determine the amount of delay required to solve the domain crossing problem occurring during the normal-mode operation through the B mode, that is, the test mode operation.

In the C mode, when the fuse select signal FUSE1 is "high" and the test mode signal TM_ANTIFUSE is "high", the delay control unit 100 operates to short-circuit the anti-fuse. When the power-up signal PWRUP is applied, the PMOS transistor P1 is turned on to initialize the node A to the power supply voltage VDD level.

Since the fuse select signal FUSE1 is "high" and the test mode signal TM_ANTIFUSE is "high", the output of the NAND gate ND becomes "low". At this time, the transfer gate TG is turned on, the NMOS transistor N1 is turned off, the NMOS transistor N2 is turned on, and the node A is at the power supply voltage VDD level. In addition, the back bias voltage VBBF is applied as -3V or -4V, and the operating voltage VBBA is applied with a voltage of -0.7V level.

As a result, the anti-fuse 130 is short-circuited by the voltage difference applied across the anti-fuse 130. The NMOS transistor, which receives the operating voltage VBBA as its gate, (N5) cuts off the direct current path when the anti-fuse 130 is short-circuited, and brings node A to the "low" level after the anti-fuse 130 is short-circuited. Perform the grab function. The latch unit 150 latches the potential level of the node A and outputs a delay control signal ANTI1 having a "low" level.

Next, the operation of the delay unit 200 will be described.

The delay unit 200 receives the input signal IN and the delay control signals ANTI1 to ANTI4 and adjusts the delay of the input signal IN according to the state of the delay control signals ANTI1 to ANTI4 to output the output signal OUT. Will output

An operation process of the delay unit 200 will be described by referring to the first delay unit 210. When the delay control signal ANTI1 is input to the first delay unit 210 as "low", the NAND gate ND1 outputs "high" regardless of the state of the input signal IN, and the NAND gate ND1. ) Is input "high" to the NAND gate ND3 via the plurality of inverters INV6, INV7, INV8, INV9.

Therefore, when the delay control signal ANTI1 is input to the first delay unit 210 in the "low" state, the output state of the NAND gate ND3 is determined according to the input signal IN, and thus, the plurality of inverters INV6. , INV7, INV8, and INV9).

That is, when the delay control signals ANTI1, ANTI2, ANTI3, and ANTI4 all have a "low" state, the input signal IN does not have a delay in the first delay unit 210 and the second delay unit 220. Although through the third delay unit 230 and the fourth delay unit 240 is output as the output signal (OUT) through a path having a delay by a plurality of inverters (INV16 ~ INV24).

Therefore, the user can adjust the delay amount of the input signal in the packaged state by adjusting the state of the delay control signal for selecting the paths of the plurality of inverters of the set delay unit, thereby securing a domain crossing margin and the like. The plurality of inverter paths of the delay unit may be appropriately set before packaging by the user.

As described above, the delay control circuit using the anti-fuse according to the present invention adjusts the delay using the anti-fuse, thereby ensuring domain crossing margins of the packaged memory chip, thereby shortening the development period and modifying the wafer. ) Can be minimized and the loss can be minimized even when domain crossing margin shortage occurs at high frequency due to unstable process or power supply.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (9)

delete delete A plurality of delay adjusting units for controlling a short circuit of the antifuse according to the fuse selection signal and the test mode signal to enable the delay control signal; And And a delay unit for delaying and outputting an input signal according to the delay control signal. The delay control unit may include a delay control signal enable unit configured to apply the delay control signal to a power supply voltage level when the fuse selection signal and the test mode signal are enabled; And And a switching unit for shorting the anti-fuse to transition the delay control signal to a "low" level when the fuse selection signal and the test mode signal are enabled. The method of claim 3, wherein The delay control signal enable unit, A NAND gate receiving the fuse selection signal and the test mode signal and performing NAND operation; A transfer gate for applying the delay control signal to a power supply voltage level according to the output signal of the NAND gate; A first NMOS transistor to which an output signal of the NAND gate is applied to a gate and an output signal of the transfer gate is applied to a drain; A second NMOS transistor having a drain connected to a source of the first NMOS transistor, a test mode signal applied to a gate, and a ground voltage applied to a source; Delay control circuit with anti-fuse. The method of claim 3, wherein The anti-fuse has a dielectric sandwiched between conductors, and both ends of the dielectric are shorted due to a difference between the back bias voltage and the power supply voltage, which are changed when the fuse select signal and the test mode signal are enabled. Delay control circuit with anti-fuse. The method of claim 3, wherein The switching unit, It is connected between the delay control signal enable unit output and the anti-fuse, PMOS transistor with ground power applied to the gate A third NMOS transistor, wherein the back bias voltage is applied to a bulk, an operating voltage is applied to a gate, and a source and a drain are respectively connected to a drain and a source of the PMOS transistor. Delay control circuit with anti-fuse. The method of claim 3, wherein The delay adjusting unit, And an initialization unit configured to receive a power-up signal to initialize an output terminal of the delay control signal enable unit. Delay control circuit with anti-fuse. The method of claim 3, wherein The delay adjusting unit And a latch unit for latching and outputting an output signal of the delay control signal enable unit. Delay control circuit with anti-fuse. The method according to any one of claims 3 to 8, The delay unit, A first path through which an input signal is transmitted when the delay control signal is enabled; And a second path through which an input signal is transmitted when the delay control signal is disabled, One of the first path and the second path includes delay means for delaying the input signal. Delay control circuit with anti-fuse.

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