KR100813286B1 - Underfilling method - Google Patents

Underfilling method Download PDF

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KR100813286B1
KR100813286B1 KR1020060131943A KR20060131943A KR100813286B1 KR 100813286 B1 KR100813286 B1 KR 100813286B1 KR 1020060131943 A KR1020060131943 A KR 1020060131943A KR 20060131943 A KR20060131943 A KR 20060131943A KR 100813286 B1 KR100813286 B1 KR 100813286B1
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chip
die
inorganic filler
substrate
pattern
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KR1020060131943A
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Korean (ko)
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이종현
이창우
김정한
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한국생산기술연구원
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

An underfilling method is provided to enhance productivity by shortening an underfilling time and to improve reliability of a junction part by reducing an error rate. An inorganic filler(131) of a powder type is coated on a substrate(110) including a pattern(111). A preprocess is performed to expose the pattern to the outside and to coat only a part of the pattern covered by a chip or a die. A die bonding process is performed to bond the chip or the die on the pattern exposed by the preprocess. An injection process is performed to inject a polymer adhesive without the inorganic filler into a gap between the chip or the die and the substrate. The inorganic filler is coated through a cold spray coating method.

Description

언더필 주입방법{Underfilling method}Underfilling method {Underfilling method}

도 1 은 본 발명의 바람직한 실시 예의 단계(S1)에 따른 공정을 나타낸 단면도,1 is a cross-sectional view showing a process according to a step (S1) of a preferred embodiment of the present invention,

도 2 는 본 발명의 바람직한 실시 예의 단계(S2)에 따른 공정을 나타낸 단면도,2 is a cross-sectional view showing a process according to step S2 of the preferred embodiment of the present invention;

도 3 은 본 발명의 바람직한 실시 예의 단계(S3)에 따른 공정을 나타낸 단면도,3 is a cross-sectional view showing a process according to step (S3) of a preferred embodiment of the present invention,

도 4 는 본 발명에 따른 언더필 주입방법에 따라 언더필이 주입된 상태의 단면도.Figure 4 is a cross-sectional view of the underfill injected state in accordance with the underfill injection method according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

(110) : 기판 (120) : 다이110: substrate 120: die

(130) : 언더필 (131) : 무기 필러(130): Underfill (131): Weapon Filler

(132) : 고분자 접착제(132): polymer adhesive

본 발명은 언더필 주입방법에 관한 것으로, 특히 콜드 스프레이 코팅 전처리에 의해 기판상에 전처리를 수행함으로써 언더필의 주입이 용이하게 하는 언더필 주입방법에 관한 것이다.The present invention relates to an underfill injection method, and more particularly, to an underfill injection method that facilitates injection of an underfill by performing pretreatment on a substrate by cold spray coating pretreatment.

최근 들어 전자기기의 박형화, 소형화 추세에 따라 반도체 소자를 외부환경으로부터 보호하는 기능의 패키징 기술에 있어서 고속, 고밀도 실장등이 요구되며, 이러한 요구에 부응하여 리드프레임이 없는 플립칩 실장기술이 등장하게 되었다.Recently, high-speed, high-density packaging is required for packaging technology that protects semiconductor devices from the external environment according to the trend of thinning and miniaturization of electronic devices, and in response to these demands, flip chip mounting technology without a lead frame has emerged. It became.

플립칩 실장기술은 반도체 칩을 패키징하지 않고 그대로 인쇄회로기판에 실장하는 기술로, 반도체 칩에 범퍼를 형성하고 범퍼와 인쇄회로기판에 인쇄된 접속패드를 솔더링 방식으로 접속시키는 기술을 말한다. 이와 같은 방법으로 인쇄회로기판에 반도체 칩을 실장하면, 칩과 기판의 열팽창 계수의 차이로 인해 칩과 기판을 연결하는 범프에 많은 응력이 발생되어 전기적 접합부가 손상됨으로써 칩의 성능을 저하시키거나 손상시키게 된다. 따라서 반도체 칩을 안정적으로 지지하면서 열팽창 계수의 차이로 인한 손상을 최소화하기 위해 반도체 칩과 인쇄회로기판 사이에 발생된 간극에 액상수지 물질의 언더필 재료를 주입하고 경화시켜 반도체 칩을 지지하는 언더필 층을 형성함으로써 안정적인 접속 유지능력과 칩의 손상을 방지하도록 하고 있다.Flip chip mounting technology is a technology in which a semiconductor chip is mounted on a printed circuit board without packaging, and a bumper is formed on a semiconductor chip, and a technology of connecting a bumper and a connection pad printed on the printed circuit board by a soldering method. In this way, when the semiconductor chip is mounted on the printed circuit board, a large stress is generated on the bumps connecting the chip and the substrate due to the difference in the coefficient of thermal expansion of the chip and the substrate, thereby deteriorating or damaging the performance of the chip by damaging the electrical joint. Let's go. Therefore, in order to stably support the semiconductor chip while minimizing the damage caused by the difference in thermal expansion coefficient, the underfill layer of the liquid resin material is injected and cured into the gap generated between the semiconductor chip and the printed circuit board to support the semiconductor chip. This prevents damage to the chip and stable connection holding ability.

한편 일반적인 언더필의 경우 열팽창 계수를 작게 유지하기 위해 SiC(탄화실리콘) 또는 AlN(질화알루미늄) 등과 같은 분말 형태의 무기물 필러를 포함하고 있 는데, 이로 인하여 점도가 증가함으로써 간극 채움 특성이 크게 감소하여 간극이 매우 작아질수록 간극을 완벽히 채우는데 소요되는 시간이 기하급수적으로 늘어나게 되고, 완벽히 간극을 채우지 못하는 공정 불량이 다량 발생하게 되는 문제점이 있다.Meanwhile, the general underfill includes an inorganic filler in powder form, such as SiC (silicon carbide) or AlN (aluminum nitride), in order to keep the coefficient of thermal expansion small. As a result, the gap filling property is greatly reduced due to the increase in viscosity. As the size becomes very small, the time required to completely fill the gap increases exponentially, and there is a problem in that a large amount of process defects that do not completely fill the gap occur.

본 발명은 상기와 같은 문제점을 고려하여 이루어진 것으로, 본 발명의 목적은 콜드 스프레이 코팅에 의한 전처리 공정을 수행함으로써 미세 간극에도 언더필을 용이하게 채울 수 있게 하는 언더필 주입방법을 제공함에 있다.The present invention has been made in view of the above problems, and an object of the present invention is to provide an underfill injection method that enables easy filling of underfill even in fine gaps by performing a pretreatment process by cold spray coating.

본 발명의 다른 목적은 칩과 기판의 접합부 신뢰성을 향상시킬 수 있는 콜드 스프레이 코팅 전처리에 의한 언더필 주입방법을 제공함에 있다.Another object of the present invention to provide an underfill injection method by cold spray coating pretreatment that can improve the reliability of the junction of the chip and the substrate.

상기한 바와 같은 목적을 달성하고 종래의 결점을 제거하기 위한 과제를 수행하는 본 발명은 패턴이 형성된 기판 상에 분말 형태의 무기 필러를 코팅하되, 패턴은 노출되고 칩 또는 다이에 의해 덮혀지는 부분만이 코팅되도록 전처리하는 단계(S1);The present invention, which achieves the object as described above and performs the task for eliminating the conventional drawbacks, coats an inorganic filler in powder form on a patterned substrate, wherein only the portion of the pattern is exposed and covered by a chip or die. Pretreatment to be coated (S1);

상기 단계(S1)를 통해 노출된 패턴에 칩 또는 다이를 본딩하는 단계(S2); 및Bonding a chip or a die to the pattern exposed through the step (S1) (S2); And

상기 칩 또는 다이와 기판의 사이 간극에 무기 필러가 없는 고분자 접착제만을 간극의 측면으로부터 주입하는 단계(S3);로 이루어진 언더필 주입방법을 특징으 로 한다.Injecting only the polymer adhesive having no inorganic filler in the gap between the chip or die and the substrate from the side of the gap (S3); characterized in that the underfill injection method consisting of.

이하, 본 발명의 바람직한 실시 예를 첨부된 도면과 연계하여 상세히 설명하면 다음과 같다. 본 발명을 설명함에 있어서, 관련된 공지기능 혹은 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그 상세한 설명은 생략한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, if it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

도 1은 본 발명의 바람직한 실시 예의 단계(S1)에 따른 공정을 나타낸 단면도를 도시하고 있고, 도 2는 본 발명의 바람직한 실시 예의 단계(S2)에 따른 공정을 나타낸 단면도를 도시하고 있으며, 도 3은 본 발명의 바람직한 실시 예의 단계(S3)에 따른 공정을 나타낸 단면도를 도시하고 있고, 도 4는 본 발명에 따른 언더필 주입방법에 따라 언더필이 주입된 상태의 단면도를 도시하고 있다. 도 1 내지 도 4를 참조하면, 본 발명은 분말 상태의 무기 필러(131)를 기판(110) 상에 코팅하는 단계(S1)와, 칩 또는 다이(120)를 기판(110)에 본딩하는 단계(S2)와, 칩과 기판(110) 또는 다이(120)와 기판(110)의 사이 간극에 고분자 접착제(132)를 주입하는 단계(S3)로 구성된다. 이러한 본 발명은 언더필(130)을 구성하는 무기 필러(131)와 고분자 접착제(132)를 서로 다른 공정을 통해 칩과 기판(110) 또는 다이(120)와 기판(110) 사이 간극에 주입하도록 구성되는 것으로, 모세관 힘을 극대화하여 미세한 간극에도 언더필(130)을 용이하게 주입할 수 있게 된다. 이하 각 단계를 구체적으로 설명한다.1 is a cross-sectional view showing a process according to the step (S1) of a preferred embodiment of the present invention, Figure 2 is a cross-sectional view showing a process according to the step (S2) of a preferred embodiment of the present invention, Figure 3 Figure 4 shows a cross-sectional view showing a process according to the step (S3) of a preferred embodiment of the present invention, Figure 4 shows a cross-sectional view of the underfill injected state according to the underfill injection method according to the present invention. 1 to 4, the present invention provides a method of coating an inorganic filler 131 in a powder state on a substrate 110 (S1), and bonding a chip or die 120 to the substrate 110. (S2) and injecting the polymer adhesive 132 into the gap between the chip and the substrate 110 or the die 120 and the substrate 110 (S3). The present invention is configured to inject the inorganic filler 131 and the polymer adhesive 132 constituting the underfill 130 into the gap between the chip and the substrate 110 or the die 120 and the substrate 110 through different processes. By being able to maximize the capillary force, the underfill 130 can be easily injected even in the minute gap. Each step will be described in detail below.

먼저 패턴(111)이 형성된 기판(110)에 분말 상태의 무기 필러(131)를 콜드 스프레이 코팅을 통해 코팅하는 단계(S1)를 수행한다. 이때 무기 필러(131)로는 SiC(탄화실리콘) 또는 AlN(질화알루미늄)이 사용될 수 있다. 이 경우 분말의 입도는 특별히 제한되지 않으나 바람직하게는 접합부 형성을 방해하지 않는 선에서 접합부 형성 후의 간극을 최대한 채울 수 있도록 수십 마이크론 수준의 최대한 큰 사이즈의 것이 사용되며, 되도록 유사한 분말의 입도를 사용하여야 하며, 콜드 스프레이 코팅이 진행될 수 있는 가속 에너지의 적용 조건에서 진행될 수 있다. 이와 같이 분말 상태의 무기 필러(131)를 기판(110)상에 코팅함에 있어서, 기판(110)상에 형성된 패턴(111)은 외부로 노출되고 칩 또는 다이(120)에 의해 덮여지는 부분만이 무기 필러(131)에 의해 코팅되도록 마스킹 공정을 진행하게 된다. 이러한 마스킹 공정은 주로 노광공정에 의해 패턴닝의 형성이 가능한 테이프 또는 잉크를 코팅하거나 밀착력이 좋은 메탈 소재 마스크를 적용함으로써 진행된다.
또한 상기와 같이 무기 필러(131)를 기판(110) 상에 코팅함에 있어 무기 필러를 패턴(111) 보다 높게 코팅하는 것이 바람직하다. 이는 기판(110)과 칩 또는 다이(120) 사이 간극의 상, 하부에 걸쳐 균일하게 무기 필러가 위치하여 채워지게 될 때, 간극의 상, 하부부에 균일한 물성이 만들어지고, 간극부의 열팽창계수를 전체적으로 균일하게 낮출 수 있기 때문이다.First, a step (S1) of coating the inorganic filler 131 in a powder state on the substrate 110 on which the pattern 111 is formed through cold spray coating is performed. In this case, SiC (silicon carbide) or AlN (aluminum nitride) may be used as the inorganic filler 131. In this case, the particle size of the powder is not particularly limited, but preferably a size of the largest size of several tens of microns is used to fill the gap after the formation of the junction at the line which does not prevent the formation of the junction. And may be carried out under the conditions of application of the accelerating energy in which the cold spray coating can proceed. As described above, in the coating of the inorganic filler 131 in the powder state on the substrate 110, only a portion of the pattern 111 formed on the substrate 110 is exposed to the outside and covered by the chip or the die 120. The masking process is performed to be coated by the inorganic filler 131. This masking process is mainly performed by coating a tape or ink capable of forming patterning by an exposure process or applying a metal mask having good adhesion.
In addition, when coating the inorganic filler 131 on the substrate 110 as described above, it is preferable to coat the inorganic filler higher than the pattern 111. When the inorganic filler is uniformly positioned and filled over the upper and lower portions of the gap between the substrate 110 and the chip or die 120, uniform physical properties are made at the upper and lower portions of the gap, and the thermal expansion coefficient of the gap portion is made. It is because it can lower uniformly as a whole.

상기와 같이 기판(110) 상의 패턴(111)은 노출되고 칩 또는 다이(120)에 의해 덮여지는 부분만이 무기 필러(131)에 의해 코팅되면, 칩 또는 다이(120)를 기판(110)에 본딩하는 단계(S2)를 수행한다. 이러한 칩 또는 다이(120)의 본딩은 칩 또는 다이(120)와 패턴(111)의 사이에 금속 접합부(112)를 형성함으로써 이루어진다.As described above, when the pattern 111 on the substrate 110 is exposed and only a portion covered by the chip or die 120 is coated by the inorganic filler 131, the chip or die 120 is attached to the substrate 110. Bonding step S2 is performed. Bonding of the chip or die 120 is achieved by forming a metal junction 112 between the chip or die 120 and the pattern 111.

상기와 같이 칩 또는 다이(120)의 본딩 후, 무기 필러(131)가 없는 고분자 접착제(132)를 칩 또는 다이(120)와 기판의 사이 간극 측면으로 주입하는 단계(S3)를 수행하게 된다. 이와 같이 고분자 접착제(132)를 간극에 주입하기 위해서는 주사기(150)가 사용될 수 있으며, 칩과 기판(110) 또는 다이(120)와 기판(110)의 사 이에 무기 필러(131)가 코팅된 상태에서 무기 필러(131)가 없는 고분자 접착제(132)를 주입함으로써, 무기 필러(131) 분말의 사이로 고분자 접착제(132)가 젖으면서 흐르게 되어 모세관 힘이 극대화되어 간극 채움 특성을 매우 향상시킬 수 있게 된다.After bonding the chip or die 120 as described above, the step (S3) of injecting the polymer adhesive 132 without the inorganic filler 131 into the gap side between the chip or die 120 and the substrate. As such, the syringe 150 may be used to inject the polymer adhesive 132 into the gap, and the inorganic filler 131 is coated between the chip and the substrate 110 or between the die 120 and the substrate 110. By injecting the polymer adhesive 132 without the inorganic filler 131, the polymer adhesive 132 flows while the inorganic filler 131 powder is wet, and the capillary force is maximized, thereby greatly improving the gap filling characteristics. .

도면 중 미설명부호 140은 노즐이다.In the drawings, reference numeral 140 denotes a nozzle.

본 발명은 상술한 특정의 바람직한 실시 예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변형실시가 가능한 것은 물론이고, 그와 같은 변경은 청구범위 기재의 범위 내에 있게 된다.The present invention is not limited to the above-described specific preferred embodiments, and various modifications can be made by any person having ordinary skill in the art without departing from the gist of the present invention claimed in the claims. Of course, such changes will fall within the scope of the claims.

본 발명은 상술한 바와 같이 언더필을 구성하는 무기 필러는 칩 또는 다이의 본딩 전 기판상에 코팅되고, 고분자 접착제는 칩 또는 다이의 본딩 후 간극에 주입되는 방식으로, 모세관 힘의 극대화로 인해 언더필링(underfilling) 시간을 단축하여 생산성을 향상시킬 수 있게 되었고, 더욱이 간극 내부의 공극 형성과 같은 불량도 감소시켜 접합부의 신뢰성을 향상시킬 수 있게 되었다.As described above, the inorganic filler constituting the underfill is coated on the substrate before bonding of the chip or die, and the polymer adhesive is injected into the gap after bonding of the chip or die, thereby underfilling due to the maximization of capillary force. The shortening of the underfilling time improves productivity, and further reduces the defects such as the formation of voids in the gap, thereby improving the reliability of the joint.

Claims (4)

패턴이 형성된 기판 상에 분말 형태의 무기 필러를 코팅하되, 패턴은 노출되고 칩 또는 다이에 의해 덮혀지는 부분만이 코팅되도록 전처리하는 단계(S1);Coating an inorganic filler in powder form on the patterned substrate, the pretreatment such that only the portion of the pattern is exposed and covered by the chip or die is coated (S1); 상기 S1 단계를 통해 노출된 패턴에 칩 또는 다이를 본딩하는 단계(S2); 및Bonding a chip or a die to the pattern exposed through the step S1 (S2); And 상기 칩 또는 다이와 기판의 사이 간극에 무기 필러가 없는 고분자 접착제만을 간극의 측면으로부터 주입하는 단계(S3);로 이루어진 것을 특징으로 하는 언더필 주입방법.Injecting only a polymer adhesive having no inorganic filler in the gap between the chip or die and the substrate from the side surface of the gap (S3). 제 1 항에 있어서,The method of claim 1, 상기 S1 단계의 무기 필러는 콜드 스프레이 코팅을 통해 코팅하는 것을 특징으로 하는 언더필 주입방법.The inorganic filler of the step S1 is an underfill injection method, characterized in that the coating through the cold spray coating. 제 1 항에 있어서,The method of claim 1, 상기 S1 단계의 무기 필러는 패턴 보다 높게 코팅하는 것을 특징으로 하는 언더필 주입방법.The inorganic filler of the S1 step is an underfill injection method, characterized in that the coating higher than the pattern. 제 1 항에 있어서,The method of claim 1, 상기 S1 단계는 마스킹 공정(S1-1)을 통해 패턴이 노출되게 하는 것을 특징으로 하는 언더필 주입방법.The step S1 is underfill injection method, characterized in that to expose the pattern through the masking process (S1-1).
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000028361A (en) * 1998-10-31 2000-05-25 김규현 Method for bagging semiconductor device
KR20020036965A (en) * 1999-07-08 2002-05-17 가네다 히로 Underfilling material for semiconductor package
KR20050019917A (en) * 1999-03-03 2005-03-03 인텔 코오퍼레이션 A controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000028361A (en) * 1998-10-31 2000-05-25 김규현 Method for bagging semiconductor device
KR20050019917A (en) * 1999-03-03 2005-03-03 인텔 코오퍼레이션 A controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials
KR20020036965A (en) * 1999-07-08 2002-05-17 가네다 히로 Underfilling material for semiconductor package

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