KR100812692B1 - Apparatus and method for clock synchronous use for dsrc system - Google Patents

Abstract

An apparatus and a method for synchronizing a clock in a DSRC(Dedicated Short Range Communication) system are provided to recognize a start point of a data frame by delaying and sampling a received signal for a predetermined time. An apparatus for synchronizing a clock in a DSRC system includes a signal delay unit(310), a noise removing unit(320), a frame detection unit(330), a phase fixing unit(340), a data extracting unit(350), and a synchronization detection unit(360). The signal delay unit delays a received signal for a predetermined time and performs a sampling of the delayed signal. The noise removing unit detects abnormal data of the sampled data and recovers the abnormal data to normal data. The frame detection unit detects a start point of the sampled signal and generates a reset signal. The phase fixing unit extracts a data clock signal in response to the reset signal, is synchronized with the clock signal of the sampled data and fixes the output signal. The data extracting unit buffers an output of the phase fixing unit sequentially and extracts data from the received signal. The synchronization detection unit detects a synchronization signal from an output of the data extracting unit.

Description

Apparatus and method for clock synchronous use for DSRC system}

1 is a signal diagram showing a signal according to a clock synchronization method according to the related art.

2 is a view schematically showing an entire DSRC system according to an embodiment of the present invention.

3 is a block diagram illustrating a clock synchronization device in a DSRC system according to an embodiment of the present invention.

4 is a flowchart illustrating a clock synchronization method according to an embodiment of the present invention.

5 is a signal diagram illustrating a signal according to the method of FIG. 4.

Explanation of symbols on the main parts of the drawings

310: signal delay unit 320: noise canceling unit

330: frame detector 340: phase fixing unit

350: data extraction unit 360: synchronization detection unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronization device and a synchronization method thereof in a dedicated short range communication (DSRC) system, and more particularly, to easily extract a data clock signal from a received signal encoded with a Manchester code, and to synchronize a clock. A clock synchronizer and a method thereof

DSRC is a wireless dedicated mobile communication for a vehicle, and a short-range dedicated wireless communication radius between a roadside base station device (RSE) located on a roadside and an on-board terminal (OBE) mounted on a vehicle Performs data wireless communication with each other within the system, providing automatic toll collection (ETC), road traffic safety information, BIS (Bus Information), ATIS (Advanced Traveler Information System) traffic control, parking lot management, crackdown detection, emergency It is a dedicated communication method of Intelligent Transport System (ITS) that enables the construction of advanced road traffic environment through vehicle signal control.

In the DSRC system, the Manchester coded data is transmitted and received in units of frames. When transmitting, the data is transmitted with the data clock information included in the transmission data without separately transmitting a synchronization signal (clock signal) of the transmission signal. The Manchester code is coded including both data and data clock information, and loads and transmits data when the signal of the transmission signal synchronized with the data clock changes.

Therefore, the receiving end should extract and synchronize the data clock information from the received signal, and then extract the data from the received signal. According to the related art, a reference clock signal having a predetermined period is generated before receiving the received signal. The method of extracting the phase difference from the time when the signal is input and correcting the phase from the moment when the phase difference occurs is used.

FIG. 1 is a signal diagram illustrating a signal according to a conventional clock synchronization method. Referring to FIG. 1, a problem of the prior art will be described.

As shown in FIG. 1, in the clock synchronization method according to the related art, when a reception signal is input in a state in which a reception terminal generates a clock signal (reference clk) having a predetermined period (2.048 MHz), the first signal of the reception signal is input. The phase difference t1 between the rising edge and the clock signal is detected first. Subsequently, the second rising edge of the received signal and the next phase difference t2 of the clock signal are second detected, and then the first detected phase difference is reflected in the second detected portion. Subsequently, after detecting the third rising edge of the received signal and the next phase difference t3 of the clock signal in the third order, the second difference detected in the third detected portion is reflected. This process is repeated until the phase difference between the received signal and the clock signal does not occur to generate a synchronization signal synchronized with the received signal.

As described above, according to the related art, since the synchronization signal is extracted using the reference clock signal which has not been phase corrected from the reception of the reception signal, the synchronization signal may be extracted without knowing the phase difference between the reception signal and the reference clock signal. Will be extracted. Therefore, it takes a lot of time to extract the data clock information of the received signal, it is not possible to extract the synchronization signal quickly at the start of the communication, the entire frame is not recognized, the communication state is poor or impossible problem occurs.

In addition, according to the related art, it is difficult to remove the noise of the received signal until the receiver generates the synchronization signal.

The present invention was devised to solve the above problems of the prior art, and an object of the present invention is to provide a clock synchronization device and a synchronization method according to the DSRC system to realize a fast phase locked loop.

Another object of the present invention is a clock synchronization device and a synchronization thereof in a DSRC system that can easily recognize a starting point of a preamble frame by sampling a received signal by delaying a predetermined time in a DSRC system that does not use a separate data timing signal. To provide a way.

It is still another object of the present invention to provide a clock synchronization device and a synchronization method thereof in a DSRC system capable of extracting optimal data by removing noise pulses generated during transmission and reception of Manchester codes through wireless communication.

For this purpose, the clock synchronization device in the DSRC system according to the present invention, the signal delay unit for delaying and sampling the received signal for a predetermined time; A frame detector detecting a start point of the sampled signal and generating a reset signal; And a phase fixing unit extracting a data clock signal in response to the reset signal and fixing an output signal in synchronization with a clock signal of the sampled data.

The clock synchronization device in the DSRC system according to the present invention includes a signal delay unit for delaying and sampling a received signal including data and data clock information for a predetermined time; A frame detector detecting a start point of a received signal by using preamble information of the sampled signal; And a phase fixing unit for fixing an output signal synchronized with the data clock from a start point of the received signal.

A clock synchronization method in a DSRC system according to the present invention includes: a) delaying and sampling a received signal for a predetermined time; b) detecting a preamble start point of the sampled received signal and generating a reset signal; And c) generating a data clock signal in response to the reset signal, and fixing an output signal in synchronization with the extracted data clock signal.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings and preferred embodiments. For reference, in the following description, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention are omitted.

2 is a view schematically showing an entire DSRC system according to an embodiment of the present invention.

2, the entire DSRC system according to the present invention includes a plurality of vehicle-mounted terminals 100, a plurality of roadside base station apparatuses 220, and a center server 250. In the present embodiment, the short-range dedicated wireless communication between the roadside base station and the vehicle-mounted terminal is described as an example, but the present invention is not limited thereto and may be applied to all systems for performing short-range dedicated wireless communication.

When the vehicle 210 enters the short-range dedicated wireless communication area A, the on-vehicle terminal 100 installed in the vehicle 210 performs short-range dedicated wireless communication with the roadside base station apparatus 220 according to the DSRC communication standard. Automatic toll collection, road traffic information, various Internet services, etc. may be provided to the user.

The roadside base station apparatus 220 may be installed at appropriate intervals on the side of the road, or may be installed at a toll gate of a highway to perform short-range wireless communication with the on-vehicle terminal 100 to collect traffic information and billing information. In FIG. 2, the roadside base station apparatus 220 is shown to be installed higher than the vehicle 210 for convenience of description. However, the present invention is not limited thereto and may be installed at a height similar to that of the vehicle.

The center server 250 may receive signals including a lot of service information, such as weather forecasts, traffic information, Internet information, etc. from an external service information provider (not shown). Can be sent to In addition, the center server 250 may collect and process traffic information, billing information, etc. obtained through the roadside base station apparatus 220 from the vehicle-mounted terminal 100. For example, when the vehicle-mounted terminal according to an embodiment of the present invention is installed on a bus and the traffic rate card processing terminals are respectively installed in the vehicle-mounted terminal, the center server 250 is generated when the passengers close to the terminal. The billing signal to be received through the roadside base station apparatus can be sent to the card company server (not shown) to be processed.

The center server 250 collects traffic information in real time and stores the traffic information in a traffic information database (not shown), and the vehicle-mounted terminal 100 through the roadside base station apparatus 220 based on a request of the vehicle-mounted terminal 100. It can provide real time traffic information.

In addition, the center server 250 may provide information about the addition of the roadside base station apparatus 220 in a specific region, the addition and / or change of the short-range dedicated wireless communication area of the specific roadside base station apparatus 220, and the like. It may be transmitted to the vehicle-mounted terminals 100 through the 220.

The communication network 240 is a wireless communication network and connects the center server 250 and the roadside base station apparatus 220.

3 is a block diagram illustrating a clock synchronizing apparatus in a DSRC system according to an exemplary embodiment of the present invention, and a clock synchronizing apparatus according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 3.

As shown in FIG. 3, the clock synchronization device 300 includes a signal delay unit 310, a noise canceller 320, a frame detector 330, a phase locker 340, a data extractor 350, and And a synchronization detector 360.

The signal delay unit 310 combines the data and the data clock information to sample and delay the Manchester coded received signal Rx for a predetermined time. The signal delay unit 310 may use a shift register, and the delay time of the received signal is determined according to the performance of the shift register.

For example, the shift register may be composed of 32 or 64 bits and the like, and when composed of 64 bits, the reception signal Rx is delayed for 2 ms capable of receiving 2-bit data and sampled for 2 ms. The received signal Rx includes a preamble (0xaaa), a frame sync signal (0x1ba84b3e), and data (Data).

The preamble, frame synchronization signal, and data are encoded and transmitted at the time of signal change of the received signal. For example, data '1' is displayed on the falling edge within one bit of the received signal Rx, and data '0' is displayed on the rising edge.

The noise canceller 320 detects an abnormal glich from the sampled data Rx_D, filters it, and corrects it to normal data Rx_D '. In general, in a wireless communication environment, a received signal is distorted due to noise. The noise canceller 320 plays a role of restoring a distorted normal signal to a normal signal.

For example, if the sampled data is detected as 16'b1111_1111_0111_1111 when sampled with 32 hexadecimal digits, the noise canceller 320 recognizes it as a glitch that is a noise pulse generated in an unnecessary part because the code cannot be generated in the Manchester code. Filter by normal data 16'b1111_1111_1111_1111.

The frame detector 330 detects the start point of the preamble frame by using the sampling data removed by the noise remover 320.

The starting point of the received signal and the starting point of the preamble frame are provided as 0'b10, and since the 0'b10 is sampled as 0xFFFF_0000_0000_FFFF by the signal delay unit 310, the frame detection unit 330 detects this as the start point of the preamble and reset signal. Is provided to the phase fixing part 340.

The phase fixing unit 340 recognizes the start point of the preamble in response to the reset signal RESET, and fixes the phase according to the data clock of the received signal. The phase locker 340 synchronizes an external clock at a start point of the preamble in response to the reset signal of the preamble, and uses the data phase lock loop to lock the phase locker 340. By detecting the phase difference between the input signal and the output signal, the output signal is fixed to be synchronized with the data clock.

The data extractor 350 receives the output of the phase locker, that is, the data clock signal CLK and the sampled received signal Rx_D 'and extracts data, and the sync detector 360 extracts the sync signal from the buffered data. Detect.

4 is a flowchart illustrating a clock synchronizing method according to an exemplary embodiment of the present invention, and FIG. 5 is a signal diagram illustrating a signal according to the method of FIG. 4. Referring to FIGS. 4 and 5, a clock synchronizing method according to an exemplary embodiment of the present invention is described. The method is described in more detail.

4 and 5, the Manchester coded signal is received (S400). The Manchester code is a code coded by combining data and a data clock, and combines and transmits data to a signal change, rising edge, or falling edge occurring in one bit. The Manchester code is provided in conjunction with a constant clock period, and the received signal is provided in synchronization with the clock period by carrying data upon signal change. As shown in FIG. 5, the reception signal Rx carries data '1' at the falling edge, data '0' at the rising edge, and is synchronized with the data clock (Manchester Code generation clk 1). Lose.

The signal delay unit 310 delays and samples the received signal for a predetermined time (S402). In FIG. 5, a reception signal Rx_D having a 2-bit delay in the reception signal Rx is shown. When the signal delay unit 310 is configured with a 64-bit shift register, 2 ms is delayed, which corresponds to a time when the 2-bit data is delayed and sampled. As another example, when the signal delay unit 310 is configured as a 32-bit shift register, 1 ms is delayed, which corresponds to a time when 1-bit data is delayed and sampled.

Subsequently, the noise removing unit 330 corrects the noise pulse from the delayed received signal (S404). When the signal delay unit 310 is composed of 32-bit or 64-bit registers, the sampled sample value is repeated 1 or 16 times with a high value and zero or 16 times with a low value. In the case of ideal sampling, glitches caused by unnecessary noise pulses are generated, so that the filters are restored to normal data.

Next, the frame detector 330 detects the start point of the preamble using the sampling signal Rx_D and provides a phase lock reset signal DPLL RESET to the phase lock 350 (S406). The sampling signal may be a sampling signal Rx_D 'from which glitches are removed.

The phase fixing unit 340 generates a data clock signal by synchronizing a reference clock signal with a start point of a sampled received signal, that is, a start point of a preamble, in response to the phase locked reset signal DPLL RESET (Manchester code generation clk 2). The phase is fixed by detecting the phase difference between the input signal and the output signal of the phase fixing unit 340 (S408).

Subsequently, the clock signal clk extracted by the data extractor 350 and the received signal having a fixed phase are sequentially buffered to extract data Q from the received signal (S410), and the synchronization detector 360 frame. A synchronization signal is detected (S412).

As described above, in the embodiment of the present invention, since the phase fixing unit can synchronize to the data clock signal at the beginning of the preamble frame, thereby fixing the phase, the phase of the output signal is fastened considerably faster than in the related art. Phase Lock Loop). In addition, there is an advantage that the optimum data can be extracted by removing the noise pulse generated when transmitting and receiving the Manchester code.

The clock synchronization method in the DSRC system according to the present invention may be implemented in the form of program instructions that can be executed by various computer means and recorded in a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program instructions recorded on the media may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks such as floppy disks. -Magneto-Optical Media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. The medium may be a transmission medium such as an optical or metal wire, a waveguide, or the like including a carrier wave for transmitting a signal specifying a program command, a data structure, or the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art to which the present invention pertains can implement the present invention in other specific forms without changing the technical spirit or essential features, The examples are to be understood in all respects as illustrative and not restrictive.

In addition, the scope of the present invention is specified by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention. Should be interpreted as

According to the present invention, in a DSRC system that does not use a separate data timing signal, the reception signal can be easily recognized by sampling the received signal after a predetermined time delay.

In addition, according to the present invention, it is possible to quickly generate a data clock of the received signal which is Manchester encoded and provide it to the phase locked loop, which has the effect of realizing a fast phase locked loop compared to the conventional technology.

In addition, according to the present invention has the effect of extracting the optimum data by removing the noise pulse generated during transmission and reception of the Manchester code through wireless communication.

Claims (17)

In a clock synchronizing apparatus in a DSRC system for synchronizing a clock signal, A signal delay unit delaying and sampling the received signal for a predetermined time; A frame detector detecting a start point of the sampled signal and generating a reset signal; And And a phase locker configured to extract a data clock signal in response to the reset signal and to fix an output signal in synchronization with a clock signal of the sampled data. The method of claim 1, And a noise removing unit for detecting abnormal data of the sampled data and restoring the normal data to normal data. The method of claim 2, The phase fixing unit, The clock synchronization device of the DSRC system, characterized in that for fixing the phase of the output signal by using the sampling signal from which the noise pulse is removed. The method of claim 3, A data extracting unit sequentially extracting data from the received signal by sequentially buffering an output of the phase fixing unit; And And a sync detector configured to detect a sync signal from an output of the data extractor. The method of claim 1, The signal delay unit, A clock synchronization device in a DSRC system, comprising delaying a Manchester coded received signal using a shift register. The method of claim 5, The signal delay unit, The clock synchronization device in the DSRC system, characterized in that for delaying and sampling the received signal for any one of 1 kHz and 2 kHz time. The method of claim 1, The phase fixing unit, A clock synchronizing device in a DSRC system, characterized in that it generates a clock signal in synchronization with a data clock, and locks the phase of the output signal in synchronization with a data clock using a digital phase locked loop. The method of claim 1, And the received signal includes a preamble, a frame sync signal, and data. The method of claim 1, And the received signal is a signal representing data at the time of signal change and synchronizing with a data clock. A clock synchronization device in a DSRC system that synchronizes with a data clock of a received signal, A signal delay unit configured to delay and sample a preamble, a frame synchronization signal, and a received signal in which data is Manchester coded and received; A frame detector detecting a start point of the received signal by using preamble information of the sampled signal; And And a phase locker for generating a clock signal synchronized with the data clock by using the detected starting point, and repeatedly controlling the phase difference between the input signal and the output signal to fix the phase. Device. The method of claim 10, The apparatus may further include a noise removing unit configured to filter abnormal data of the sampled signal into normal data. The phase fixing unit generates a clock signal synchronized with the data clock from the filtered signal, and adjusts a phase difference between an input signal and an output signal to fix an output signal to synchronize with the clock signal Clock synchronizer In a clock synchronization method in a DSRC system for synchronizing a clock signal, a) delaying and sampling a received signal for a predetermined time; b) detecting a preamble start point of the sampled received signal and generating a reset signal; And c) generating a data clock signal in response to the reset signal, and fixing an output signal in synchronization with the extracted data clock signal. The method of claim 12, After step a), and a-1) detecting abnormal data of the sampled data, and restoring the normal data to normal data. The method of claim 12, After step c), Sequentially buffering the output of the phase fixing unit to extract data from the received signal; And And detecting a frame synchronizing signal from an output of the data extracting unit. The method of claim 12, In step a), The received signal is a clock synchronization method in the DSRC system, characterized in that the sample is delayed for any one of 1 kHz and 2 kHz time. The method of claim 12, In step c), And the data clock signal is a signal synchronized with a data clock of the received signal. A computer-readable recording medium having recorded thereon a program for executing the clock synchronizing method according to any one of claims 12 to 16.

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