KR100810232B1 - Memory device for use in a communication terminal and memory control method therein - Google Patents

Abstract

A memory device for use in a mobile communication terminal and a memory control method in the memory device are disclosed. A memory device for use in a mobile communication terminal according to the present invention stores basic code data for initial setting of the terminal and driving software data for operation of the terminal, and service data transmitted and received for service in the terminal. It includes a NAND flash memory for storing the. The first memory is capable of random access and stores the basic code data to be transmitted from the NAND flash memory upon initial setting of the terminal. The second memory is capable of random access and stores the driving software data to be copied from the NAND flash memory upon completion of initial setting of the terminal. The transmission control block automatically transmits the basic code data stored in the NAND flash memory to the first memory when the terminal is powered on. The control unit initializes the terminal by reading the basic code data from the first memory during initial setting of the terminal, and copies the driving software data from the NAND flash memory after the initial setting of the terminal is completed. And driving the terminal by randomly accessing the driving software data stored in the second memory and in the second memory, and reading and writing service data transmitted and received to and from the terminal after the terminal is driven.

Memory Devices, NAND FLASH MEMORY, AUTO-DUMP BLOCK, MODEM CHIP

Description

Memory device for use in communication terminal and memory control method in the device {MEMORY DEVICE FOR USE IN A COMMUNICATION TERMINAL AND MEMORY CONTROL METHOD THEREIN}             

1 is a view showing the configuration of a memory device according to the prior art.

2 is a block diagram illustrating a memory device according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a detailed configuration of the memory device shown in FIG. 2.

4 is a view showing a specific configuration of the MCPAD 300 shown in FIG.

FIG. 5 is a diagram illustrating a detailed configuration of the NAND flash memory block 310 shown in FIG. 3.

FIG. 6 is a diagram illustrating a detailed configuration of a data bus connected between the modem chip 100 and the MCPAD 300 shown in FIG. 3.

FIG. 7 illustrates a detailed configuration of a read / write enable signal connected between the modem chip 100 and the MCPAC 300 shown in FIG. 3.

8A to 8C show processing flows for a memory control operation in the memory device shown in FIG.

The present invention relates to a memory device, and more particularly, to a memory device for use in a mobile communication terminal and a memory control method in the memory device.

As a representative communication terminal, there is a mobile communication terminal such as a cellular phone such as a digital cellular system or a personal communication services (PCS) system. The mobile communication terminal was typically in the form of providing only a voice call service. However, the mobile communication terminal has been developed to provide not only a voice call service but also a data service. Recently, the international mobile telecommunications 2000 (IMT-2000) -based mobile communication systems such as CDMA-2000 (Code Division Multiple Access) and UMTS (Universal Mobile Telecommunication System) are not only providing voice communication services to mobile subscribers. It also enables the provision of data services.

A memory device according to the prior art for storing various data in the mobile communication terminal as shown in Figure 1 NOR-type flash memory (NOR-type Flash Memory) 20, Static Random Access Memory (SRAM) 30 Is being used. The various data stored in the NOR flash memory 20 include basic code data for initial setting of the terminal, operation software data for operation of the terminal, and service data transmitted and received for service in the terminal.                         

Meanwhile, due to the growth of the communication market and the diversification of services, high functionality, and high capacity, there is a limit to using a memory device according to the prior art including the NOR flash memory 20 as shown in FIG. 1. This is because most of the NOR flash memory used in mobile communication terminals has a size of 16M / 32Mbit, but it is expected that 64M / 128MBit or more will be required in the future communication market where data service will be activated. In addition, this high capacity NOR flash memory is a significant economic burden for subscribers as well as manufacturers of mobile communication terminals. To alleviate this burden, NOR flash memory of 64Mbit or more will need to be supplied at a low-cost price of $ 20. However, it is not possible to supply 64 Mbit NOR flash memory at a low cost of $ 20 based on memory demand rate. In addition, due to the explosive demand for NOR flash memory, the difficulty in securing parts of the NOR flash memory is increasing.

Accordingly, an object of the present invention is to economically implement a memory device for use in a mobile communication terminal for a large data service.

Another object of the present invention is to implement a memory device of a mobile communication terminal for a large data service using a memory device having a high density.

According to an embodiment of the present invention, a memory device for use in a mobile communication terminal stores basic code data for initial setting of the terminal and driving software data for operation of the terminal. And a NAND flash memory for storing service data transmitted and received for the service. The first memory is capable of random access and stores the basic code data to be transmitted from the NAND flash memory upon initial setting of the terminal. The second memory is capable of random access and stores the driving software data to be copied from the NAND flash memory upon completion of initial setting of the terminal. The transmission control block automatically transmits the basic code data stored in the NAND flash memory to the first memory when the terminal is powered on. The control unit initializes the terminal by reading the basic code data from the first memory during initial setting of the terminal, and copies the driving software data from the NAND flash memory after the initial setting of the terminal is completed. And driving the terminal by randomly accessing the driving software data stored in the second memory and in the second memory, and reading and writing service data transmitted and received to and from the terminal after the terminal is driven.

The memory device may further include an error correction block connected between the control unit and the NAND flash memory and performing error correction on data read and written between the control unit and the NAND flash memory. Include.

In addition, the memory device of the present invention is connected between a first path connecting the NAND flash memory, the transmission control block and the first memory, and a second path connecting the second memory and the controller, And a buffer block which is powered on of the terminal to open the first path and the second path, and connects the first path and the second path after the initial setting of the terminal is completed. do. The buffer block includes at least one or more tri-state buffers that are in a high impedance state upon power-on of the terminal and open between the first path and the second path.

In addition, the memory device of the present invention is characterized in that the NAND flash memory, the transmission control block, and the first memory are integrated into one chip.

The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that those skilled in the art may better understand the detailed description of the invention that follows.

Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. Those skilled in the art should recognize that the disclosed concepts and specific embodiments of the invention may be readily used as a basis for modifying or designing other structures for achieving the same purposes of the present invention. Those skilled in the art should also recognize that structures equivalent to the invention do not depart from the spirit and scope of the broadest form of the invention.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. It should be noted that reference numerals and like elements among the drawings are denoted by the same reference numerals and symbols as much as possible even though they are shown in different drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The inventors of the present invention have been made to pay attention to the following facts. The use of NAND flash memory, which can be realized at low cost, will become a trend of memory configuration in mobile terminals in the future. Compared to NOR flash memory and NAND flash memory at the same capacity, NOR flash memory per megabyte is $ 3.56 and NAND flash memory is $ 0.83. In 2002, NOR flash memory is expected to be $ 3.06 and NAND flash memory is $ 0.60. In addition, the density of NAND flash memory corresponding to NOR 64Mbytes is 512Mbytes in comparison with the current density. In 2002, the density of NAND flash memory corresponding to NOR 128Mbyte is expected to be 1024Mbyte. In other words, it can be seen that NOR flash memory is inferior in cost or density compared to NAND flash memory. In view of these realities and expectations, the use of NOR flash memory in mobile communication equipment has reached its limit.

The present invention provides data and terminal operations for various services (Grapics, E-mail, Voice-Mail, MP3-Type auto, Navigation, Game, User-Disk, Still Picture, Motion Picture, Date Service) of mobile communication terminal. The memory that stores the OS code, etc., is to replace the low cost and high density NAND flash memory instead of the high cost and low density NOR flash memory. The interface between the modem chip and the NAND flash memory requires a new method unlike the modem chip and the NOR flash memory and the interface. Accordingly, a method of implementing an interface device for efficient data communication with a modem chip in a terminal, a NAND flash memory, and an ASIC (APPLICATION SPECIFIC INTEGRATED CIRCUIT) will be described later.

2 is a block diagram illustrating a memory device according to an embodiment of the present invention. Such a memory device may be used in a mobile communication terminal, which is a representative communication terminal. For example, the memory device may be used in an IMT-2000 mobile phone such as CDMA-2000, UMTS, or a personal digital assistant such as a personal digital assistant (PDA).

Referring to FIG. 2, a memory device according to an embodiment of the present invention includes a controller 100, a multi-chip package with auto-dump (MCPAD) 200, and a second memory 300. The MCPAD 200 includes a NAND-type flash memory 210, a transmission control block 220, a first memory 230, a buffer block 240, and an error correction block 250 integrated into one chip. do.

The NAND flash memory 210 stores basic code data for initial setting of the terminal and operation software data for operation of the terminal. In addition, the NAND flash memory 210 stores service data transmitted and received for service by the terminal. The basic code data includes a vector table, a boot code, a load code, and the like. The driving software data includes an operating system (OS) software, a call software, and the like. The service data includes graphics, e-mail, voice-mail, music files (eg MP3-type file), navigation, games, still images. Picture, Motion Picture, and the like.

The first memory 230 is capable of random access, and stores the basic code data to be transmitted from the NAND flash memory 210 when the terminal is initially set up. The second memory 300 is capable of random access and stores the driving software data to be copied from the NAND flash memory 210 when the initial configuration of the terminal is completed. The second memory 300 is a memory for providing a work area of the controller 100. The first memory 230 and the second memory 300 may be implemented as static random access memory (SRAM). The transmission control block 220 automatically transmits the basic code data stored in the NAND flash memory 210 to the first memory 230 when the terminal is powered on. The transmission control block 220 generates a reset signal having a low level in response to a reset signal input from a reset circuit (not shown) when the terminal is powered on.

The controller 100 initializes the terminal by accessing (reading) the basic code data from the first memory 230 when the terminal is initially set. After the initial setting of the terminal is completed, the controller 100 copies the driving software data from the NAND flash memory 230, stores the driving software data in the second memory 300, and accesses the driving software data stored in the second memory 300. Drive the terminal. In addition, the controller 100 reads service data transmitted to and received from the terminal after driving the terminal from the NAND flash memory 210 or writes to the NAND flash memory 210. The controller 100 may directly access the NAND flash memory 210 to write or read the service data. Instead, the controller 100 may access the NAND flash memory 210 by copying the service data into the second memory. When the memory device is used in a mobile phone, the control unit 100 is a so-called "modem chip", and such a modem chip may be manufactured by SCom Series, Qualcoimm, which is manufactured and sold by Samsung Electronics Co., Ltd. It can be manufactured and sold by MSM Series.

The error correction block 250 is connected between the controller 100 and the NAND flash memory 210, and error correction (ECC) is performed on data accessed (read or written) between the controller 100 and the NAND flash memory 210. Correction). When data is written to the NAND flash memory 210 by the controller 100, the error correction block 250 generates a parity code, which is an error correction code corresponding to data for writing, and generates an ECC of the NAND flash memory 210. Write to the block. When the data is read from the NAND flash memory 210 by the controller 100, the error correction block 250 generates a parity code that is an error correction code corresponding to the data read from the NAND flash memory 210. Accordingly, the controller 100 compares the parity code generated when data is read with the parity code written in the NAND flash memory 210 in response to the read data, thereby enabling error correction.

The buffer block 240 is between the controller 100 and the second memory 300 and the NAND flash memory 210, between the controller 100 and the second memory 300 and the transmission control block 220, and the controller 100 and the second memory 300. And between the first memory 230. That is, the buffer block 240 may include a first path connecting internal components of the MCPAD 200 (the NAND flash memory 210, the transmission control block 220, and the first memory 230), the MCPAD 200, and an external device thereof. A second path connecting the components (the second memory 300 and the controller 100) is connected. The buffer block 240 powers on the terminal to open the first path and the second path, and connects the first path and the second path after the initial setting of the terminal is completed. . The buffer block 240 is at least one or more three state buffers (3 state buffers) to open between the first path and the second path in a high impedance state at the time of power-on (Power_On) of the terminal It is configured to include. Here, the buffer block 240 is shown as an example consisting of four tri-state buffers B1 to B4. The first path and the second path connect an address bus (ABUS), a data bus (DBUS), a control bus (CBUS), and signals (RE, WE, RESET). Meaning to include a path.

Hereinafter, the bus and signal connection relationships among the elements constituting the memory device according to the exemplary embodiment of the present invention will be described in detail.

The controller 100 is connected to the second memory 300 through a control bus CBUS1, an address bus ABUS, and a data bus DBUS. The controller 100 is connected to the first buffer B1 of the buffer block 240 via an address bus ABUS and a control bus CBUS2, and is connected to a third buffer B3 of the buffer block 240 via a data bus DBUS. The control bus CBUS3 and the control bus CBUS4 are connected to the fourth buffer B4 of the buffer block 240. The read enable signal RE and the read enable signal WE from the controller 100 are provided to the second buffer B2 of the buffer block 240. The read enable signal RE and the write enable signal WE from the controller 100 are also provided to the second memory 300, and the NAND flash memory 210 and the transmission control block 220 are provided through the second buffer B2. And the first memory 230.

The first buffer B1 is connected to the first memory 230 and the transmission control block 220 through an address bus ABUS11. In addition, the first buffer B1 is connected to the first memory 230 through a control bus CBUS11. The second buffer B2 receives a read enable signal RE and a write enable signal WE from the controller 100, and transmits the read enable signal RE and the write enable signal WE to the NAND flash memory. 210, the transmission control block 220 and the first memory 230. The third buffer B3 is connected to the first memory 230 through a data bus DBUS11, is connected to the transmission control block 220 through a data bus DBUS12, and the NAND flash memory 210 through a data bus DBUS13. And the error correction block 250. The fourth buffer B4 is connected to the NAND flash memory 210 through a control bus CBUS12 and to the error correction block 250 through a control bus CBUS13.

The transmission control block 220 generates a reset signal having an “L” level in response to a reset signal applied from the outside, and provides the generated reset signal to each of the buffers B1 to B4 and the controller 100 of the buffer block 240. . In addition, the transmission control block 220 generates a reset signal of "H" level when the transmission of the basic code data to the first memory 230 is completed, the control unit 100 accesses the basic code data transmitted to the first memory 230 Allows you to perform an initialization operation.

FIG. 3 is a diagram illustrating a detailed configuration of the memory device shown in FIG. 2. Such a memory device is according to an example applied to an IMT-2000 type mobile phone such as CDMA-2000 and UMTS. An ASIC (APPLICATION SPECIFIC INTEGRATED CIRCUIT) implemented according to an embodiment of the present invention will be referred to as "Multi-Chip Package Auto-Dump" (MCPAD). In the following description, components that perform the same functions as those of the memory device shown in FIG. 2 will be used as the same reference numerals, although differently named. In addition, the buses / signals shown in FIG. 2 will be defined and used in more detail below. The corresponding relationships between the components and buses / signals to be described later and the components and buses / signals shown in FIG. 2 corresponding thereto are as follows in Tables 1 and 2. And the terms shown in the drawings and used in the following description will be described in Table 3 below.

2 3 Remarks Control MODEM CHIP Reference 100 Nand Flash Memory NAND-FLASH BLOCK Reference 210 Transmission control block AUTO-DUMP BLOCK Reference 220 First memory SRAM (UtRAM) BLOCK Reference 230 Second memory SRAM (Work Area) Reference 240 Buffer block 3 STATE BUFFER BLOCK Reference 250 Error Correction Block ECC BLOCK Reference 300

2 3 Remarks ABUS ADD_M [1 ‥‥] DBUS DATA_M [0 ‥ 15] CBUS1 RAM_M [1.2] _CS, UB_M, LB_M, BYTE_M CBUS2 ROM1_CS_M, UB_M, LB_M, BYTE_M CBUS3 ROM2_CS_M, WP_M, CLE_M, ALE_M, R / _B_M CBUS4 ECC_CS_M, ECC_START_M ABUS11 ADD_A_S [1 ‥ 12] DBUS11 DATA_S [0 ‥‥ 15] DBUS12 DATA_A [0 ‥ 7] DBUS13 DATA_N_E [0 ‥ 7] CBUS11 ROM1_CS_A_S, UB_A_S, LB_A_S, BYTE_A_S ROM1_CS_A_S ... display CBUS12 ROM2_CS_A_N, WP_A_N, CLE_A_E, ALE_A_N, R / _B_A_N ROM2_CS_A_N ... CBUS13 ECC_CS_E, ECC_START_E ECC_CS_E ... display

     ROM1_CS_M ⇒ ROM1_CS signal connected to Modem Chip UB_M ⇒ UB signal connected to Modem Chip LB_M ⇒ LB signal connected to Modem Chip BYTE_M ⇒ BYTE signal connected to Modem Chip                                                       ROM1_CS_A_S ⇒ ROM1_CS signal from ADB to SRAM Block UB_A_S ⇒ UB signal from ADB (Auto-Dump Block) to SRAM Block LB_A_S ⇒ LB signal from ADB (Auto-Dump Block) to SRAM Block BYTE_A_S ⇒ ADB (Auto-Dump Block) Signal connected to SRAM Block)                                                       ROM2_CS_A_N ⇒ ROM2_CS signal from ADB to Nand Flash Block WP_A_N ⇒ WP signal from ADB to Nand Flash Block CLE_A_N ⇒ CLE signal from ADB to Nand Flash Block ALE_A_N ⇒ ALE signal from ADB to Nand Flash Block R / _B_A_N ⇒ ADB R / _B signal connected with Nand Flash Block                                                       ECC_CS_E ⇒ ECC_CS signal connected to ECC Block ECC_START_E ⇒ ECC_START signal connected to ECC Block

Referring to FIG. 3, MCPAD is largely composed of five elements.

First, an Auto-Dump Block (ADB) 220 is configured.

When the terminal is powered on, the basic code data for internal setting of the modem chip 100 for the operation of the initial terminal should be random access. Conventional NOR flash memory was randomly accessible, so this basic code was stored in NOR flash memory. However, since the NAND flash memory 210 according to the embodiment of the present invention does not have random access, it is necessary to automatically transfer basic code data of about 16 KByte in the NAND flash memory 210 to the SRAM (UtRAM) 230 that can be randomly accessed. For this role is the ADB 220.

Second, an SRAM (UtRAM) block 230 is constructed.                     

This is where ADB 220 stores the basic code in NAND flash memory 210 when the terminal is powered on. The modem chip 100 randomly accesses the SRAM block 230 to perform a basic code.

Third, a Nand Flash Block 210 is configured.

It stores basic codes, applications, and fonts stored in the existing NOR-flash memory, and the modem chip 100 is NAND flash memory so that the modem chip 100 can access data of the NAND flash memory 210. The controller 210 controls the 210 and informs the modem chip 100 of the NAND FLASH control state.

Fourth, an ECC block 250 is configured.

The ECC block 250 generates a parity code so that the modem chip 100 can investigate and correct a bit error using the generated parity code.

Fifth, a three-state buffer block 240 is configured.

When the terminal is powered on, the MCPAD's ADB 220 connects the basic code data in the NAND flash memory 210 to the SRAM (UtRAM) block 230 during auto-dumping and auto-loading. By maintaining the pins in Hi-Impedance state, it helps to automatically transmit the basic code data by the ADB 220 in the MCPAD 200.

A more specific configuration of the MCPAD 200 shown in FIG. 3 is shown in FIG. 4.

Referring to FIG. 4, the MCPAD 200 is a NAND flash block 210, an automatic transfer block 220, an SRAM (UtRAM) block 230, a three-state buffer block 240, and an ECC block 250. It is composed. The components of the MCPAD 200 are integrally formed in the form of a one-chip.

First to fourth buffers 3 State Buffer 1 to 4 of the tri-state buffer block 240 are included. The first buffer is connected to the SRAM block 230 and the automatic transfer control block 220 via an address bus ADD_A_S [1 ... 12] and a data bus ROM1_CS_A_S .... The second buffer is connected to the SRAM block 230 in a form of providing a read enable signal RE_S and a write enable signal WE_S. In addition, the second buffer is connected to the automatic transmission control block 220, the NAND flash block 210 in the form of providing a read enable signal RE_A_N and a write enable signal WE_A_N, respectively. The third buffer is connected to the SRAM block 230 via data bus DATA_S [0 .. 15], and is connected to the automatic transfer control block 220 via data bus DATA_A [0 .. 7], and data bus DATA_N_E [0. 7] are connected to the NAND flash block 210 and the ECC block 250. The fourth buffer is connected to the automatic transmission control block 220 and the NAND flash block 210 through a control bus ROM2_CS_A_N ..., and to the ECC block 250 through a control bus ECC_CS_E ....

The automatic transmission control block 220 receives the reset signal RESET_A from the reset circuit 410 installed outside the MCPAD 200 and receives the oscillation signal X_TAL_A from the frequency oscillator (X-TAL) 420. In addition, the automatic transmission control block 220 generates a reset signal RESET_A_M and provides it to each of the buffers of the three-state buffer block 240.

As illustrated in FIG. 5, the NAND flash block 210 includes a plurality of blocks including a memory area and an error correction area. Each block may store 32 pages of data. For example, a basic code used for initial setting of a terminal may be stored in a memory area of one block, and an error correction code for the basic code may be stored in an ECC area corresponding to the memory area. In this case, each page contains data of a parity code, which is a basic code of 512 bytes and an error correction code of 16 bytes. That is, the block for the basic code is composed of an area for storing the basic code of 16KByte (512Byte * 32PAGE), and an area for storing the error correction code of 512Byte (16Byte * 32PAGE).

FIG. 6 is a diagram illustrating a detailed configuration of a data bus connected between the modem chip 100 and the MCPAD 200 shown in FIG. 3.

Referring to FIG. 6, the SRAM block 230 includes a control area and a basic code loading area. The automatic transmission control block 220 is structured as a control area and an area for inputting / outputting a reset signal. The NAND flash block 210 is structured as a control area, a memory area, and an error correction area. Modem chip 100 has UB, LB, RESET, DATA [8… 15], and DATA [0… 7] pins. The SRAM block 230 includes UB, LB, DATA [8.15], and DATA [0… 7] pins. The automatic transmission control block 220 includes UB, LB, DATA [0 .. 7], WE pins. The NAND flash block 210 has I / O [0 .. 7], WE pins.

The UB_M signal from the UB pin of the modem chip 100 is provided to the UB pin of the SRAM block 230 as the UB_S signal through the buffer b1 of the tri-state buffer block 240. The LB_M signal from the LB pin of the modem chip 100 is provided to the LB pin of the SRAM block 230 as the LB_S signal through the buffer b2 of the tri-state buffer block 240. The buffer b3 of the tri-state buffer block 240 connects data buses DATA_S [8.15] and DATA_M [8 ... 15] for transmission data from the SRAM block 230 to the modem chip 100. The buffer b4 of the tri-state buffer block 240 connects the data buses DATA_M [8.15] and DATA_S [8 ... 15] for transmission data from the modem chip 100 to the SRAM block 230. Buffer b5 of the tri-state buffer block 240 connects data buses DATA_S [0.7] and DATA_M [0.7] for transmission data from the SRAM block 230 to the modem chip 100. The buffer b6 of the tri-state buffer block 240 connects data buses DATA_M [0.7] and DATA_S [0.7] for transmission data from the modem chip 100 to the SRAM block 230. Buffer b7 of the tri-state buffer block 240 connects data buses DATA_N_E [0.7] and DATA_M [0.7] for transmission data from the NAND flash block 210 to the modem chip 100. Buffer b8 of the tri-state buffer block 240 connects data buses DATA_M [0.7] and DATA_N_E [0.7] for transmission data from the modem chip 100 to the SRAM block 230. The buffers b9 and b11 of the tri-state buffer block 240 are connected in series to connect the data buses DATA_N_E [0 .. 7] and DATA_S [8..15] to each other. The buffers b9 and b12 of the tri-state buffer block 240 are connected in series to connect the data buses DATA_N_E [0 .. 7] and DATA_S [0 .. 7]. Buffer b10 of the tri-state buffer block 240 connects the data buses DATA_N_E [0 .. 7] and DATA_A [0..7].

The buffers b1 to b8 are enabled by the reset signal RESET_A_M provided from the automatic transmission control block 220. The buffer b9 is enabled by an inverted signal of the reset signal RESET_A_M provided from the automatic transmission control block 220. The buffer b10 is enabled by the inverted signal of the write enable signal WE_A_N provided from the automatic transmission control block 220. The buffer b11 is enabled by the inverted signal of the signal UB_A provided from the automatic transmission control block 220. The buffer b12 is enabled by the inverted signal of the signal LB_A provided from the automatic transmission control block 220.

FIG. 7 is a diagram illustrating a detailed configuration of a read / write enable signal provided between the modem chip 100 and the MCPAD 200 shown in FIG. 3.

Referring to FIG. 7, buffers b21 to b25 for providing read / write enable signals RE_M / WE_M from the modem chip 100 to the NAND flash block 210, the automatic transmission control block 220, and the SRAM block 230 of the MCPAD 200 are provided. The tri-state buffer block 240 is provided. The read enable signal RE_M from the modem chip 100 is provided to the NAND flash block 210 and the automatic transmission control block 220 as the read enable signal RE_A_N through the buffer b21. The write enable signal WE_M from the modem chip 100 is provided to the NAND flash block 210 and the automatic transmission control block 220 as the write enable signal WE_A_N through the buffer b22. The read enable signal RE_A_N is provided to the SRAM block 230 as a signal RE_S through a buffer b23. The write enable signal WE_A_N is provided to the SRAM block 230 as a signal WE_S through a buffer b24 or the read enable signal RE_A_N as a signal WE_S through a buffer b25. The buffers b21 to b24 are enabled by the reset signal RESET_A_M generated by the automatic transmission control block 220, and the buffer b25 is enabled by the inverted signal of the reset signal RESET_A_M. In addition, the control region of the automatic transmission control block 220 is enabled by the inverted signal of the reset signal RESET_A_M. A power supply voltage terminal Vcc is connected to the output terminal of the buffer b23 through a resistor R.

The operation of the memory device according to the embodiment of the present invention as described above will be described with reference to FIGS. 3 to 7.

A vector table, a boot code, and a load code, which are basic codes for initial terminal internal configuration, are stored in the NAND flash memory 210.

The reset signal (RESET_A in FIG. 3) generated by the external reset IC 410 at power-on of the terminal is received by the reset terminal of the automatic transmission control block (ADB) 220 of the MCPAD 200. The reset signal of all circuits is sent to the ADB RESET OUT terminal until the basic code data in the NAND flash block 210 is transferred to the SRAM (UtRAM) block 230 (Auto-Dumping, Auto-Loading). L "(RESET_M in FIG. 3). In this state, all systems except the MCPAD 200 are reset and stop working. In addition, the ADB 220 operates the 3-state buffer block 240 inside the MCPAD 200 to automatically transmit the basic code, thereby disconnecting the high pins from the connection pins of the system and the MCPAD 200. When the basic code data is automatically transferred to the SRAM (UtRAM) block 230, the ADB 220 inside the MCPAD 200 changes the reset signal (RESET_M in FIG. 3) to "H" through the reset output terminal. . At this time, the modem chip 100 reads the data stored in the SRAM (UtRAM) block 230 and initializes the terminal.

After the initial setup of the terminal, the modem chip 100 reads the OS code and call software (S / W) from the NAND flash block 210 and copies it into the SRAM (Work Area) 300. The modem chip 100 then copies the SRAM 300. Access and drive The reason why the modem chip 100 copies data from the NAND flash block 210 to the work area (SRAM) 300 is that the SRAM can be randomly accessed.

After the normal operation of the terminal, the modem chip 100 is not random access, but the various data (Graphics, E-mail, Voice-Mail, MP3-Type auto, Navigation, Game User-Disk, Still Picture, Motion Picture, Date Service) It can be read or written directly to the NAND flash block 210, and can be copied to the SRAM 300 and randomly accessed as necessary.

After the normal operation of the terminal, when the modem chip 100 writes data to the NAND flash block 210, the modem chip 100 writes data to be actually written to the memory area of the NAND flash block 210. At this time, the ECC block 250 receives this data as an input and outputs a parity code as an output value of the ECC block 250. The modem chip 100 writes this output parity code to the ECC area of the NAND flash block 210. When the modem chip 100 reads the data in the NAND flash block 210, the output data of the NAND flash block 210 is provided to the input of the ECC block 250, and the ECC block 250 reads the output data of this new NAND flash block 210. To generate a new parity code. The modem chip 100 compares this new parity code with the parity code already stored in the corresponding ECC area of the NAND flash block 210. The modem chip 100 checks for a bit error and corrects it if there is a bit error.

However, the ECC region of the NAND flash block 210 is not transmitted when the basic code data in one block of the NAND flash block 210 is automatically transmitted to the SRAM (UtRAM) block 230 by the ADB 220 of the MCPAD 200 when the terminal is initially powered on. This is because one block of NAND flash memory is designated by the manufacturing company as an area in which an error does not need to be corrected. As described above, one block containing the basic code of the NAND flash block is composed of 32 pages, and the one block is composed of a memory area of 16 Kbytes and an error correction area of 512 bytes. At this time, 1 Page is composed of 512 Byte Memory Area and 16 Byte Error Correction Area (ECC Area). And one block of NAND flash memory in manufacturing is an area which does not need to correct an error.

A memory control operation in the memory device according to the embodiment of the present invention as described above will be described below with reference to FIGS. 8A to 8C.

(Step 500 of FIG. 8A) Initially power on the terminal.

The external reset IC 410 of FIG. 3 enables RESET_A. The external oscillator 420 oscillates the clock.

The ADB 220 enables the RESET_A_M signal at the RESET OUT terminal until all basic codes are automatically transferred to the SRAM block 230 (step 502).

(Step 503) Check the RESET_A_M signal.

If the RESET_A_M signal is "H", all pins of the ADB 220 are in the high impedance ('Z' or Hi-Impedance) state and the connection is floated. Some buffers in the tri-state buffer block 240 operate, and some buffers become high impedance, connecting the modem chip 100 and the internal SRAM / NAND FLASH / ECC blocks of the MCPAD 200. ADB 220 is floating. The modem chip 100 is released from the reset state to perform normal operation. The modem chip 100 thus executes the basic code in the SRAM block 230.

If the RESET_A_M signal is "L", all pins of the ADB 220 are enabled. Some buffers in the tri-state buffer block 240 operate, and some buffers become high impedance, floating the modem chip 100 and the MCPAD 200. It connects ADB 220 of MCPAD 200 and SRAM / NAND FLASH / ECC blocks. As a result, the modem chip 100 enters a reset state and stops its operation.

(Step 506) Specify a variable value for generating an address. That is, it is designated as ADD ← (00H) and PAGE_COUNT ← (00H).

The ADB 220 enables the ROM2_CS_A_N signal to use the NAND flash memory block 210 (step 507). That is, to write data to the NAND flash memory block 210, the NAND flash chip select signal is first enabled.

The ADB 220 enables CLE_A_N (Command Latch Enable_Auto-dump_Nand-flash) to give a command to write to the NAND flash memory block 210 (step 521 of FIG. 8B). Enable WE_A_N before issuing the command. Write a command (00H) to read into the NAND flash memory data line. After giving (DATA_N_E [0..7] ← (00H)) command, disable CLE_A_N & WE_A_N. Enable ALE_A_N (Address Latch Enable Auto-dump_Nand-Flash) to give an address value.

(Steps 522 to 527) The NAND flash memory block 210 is generated for addressing. AX ← (ADD + PAGE_COUNT) consists of 3 bytes as follows: Low Byte [0..7] = AL (Add Low), Middle Byte [8..15] = AM (Add Mid), High Byte [16..23] = AH (Add Hi). First, data is transmitted to DATA_N_E [0..7] three times in the order of AL, AM, and AH of AX.

In step 528, when addressing is completed, ALE_A_N is disabled.

In operation 529, it is checked whether the NAND flash memory block 210 is busy or ready. In the case of ready state, the operation of the next step is performed.

In step 530, the address of the SRAM block 230 is set to ADD_COUNT ← (00H).

The ADB 220 enables the ROM1_CS_A_N signal to use the SRAM block 230 (step 541 of FIG. 8C). That is, the ADB 220 enables SRAM chip select in order to automatically transfer data to the SRAM block 230.                     

(Steps 542 to 544) Generation for addressing of the SRAM block 230 is performed. Check if ADD_COUNT is even. At this time, if even, LB_A is enabled (step 543). If it is odd, UB_A is enabled (step 544).

(Step 545) The address of the SRAM block 230 is designated as follows. ADD_A_S [1..12] ← ADD + ADD_COUNT + PAGE_COUNT Enables RE_A_N to read the data of the NAND flash memory block 210. Enable WE_S to write data to the SRAM block 230. That is, in order to read the data of the NAND flash memory block 210 and write it to the SRAM block 230, when the modem chip 100 of FIG. 7 generates the RE_M signal, the buffer block 240 applies the RE_A_N signal to the NAND flash memory block 210. At the same time, the data is put on the data bus of the tri-state buffer block 240. Then, since the RE_M signal generated by the modem chip 100 is provided to the SRAM block 230 as the WE_S signal, the data of the data bus of the tri-state buffer block 240 is immediately stored in the SRAM block 230. After storing data in the SRAM block 230, LB_A, UB_A, RE_A_N, WE_S are disabled.

After performing step 545, the method adds ADD_COUNT ← ADD_COUNT + 1.

If ADD_COUNT is less than 512, the process returns to step 542 and the above operation is repeated. This iterative processing operation is for storing one page (512 bytes) of the NAND flash memory block 210 in the SRAM block.

In step 548, if ADD_COUNT is not less than 512 in step 547, PAGE_COUNT ← PAGE_COUNT + 512.

If PAGE_COUNT is less than 512 * 32 (step 549), the process returns to step 521 of FIG. 8B and repeats the above operation. This iterative processing operation is for storing 32 pages (512 bytes * 32 pages) of the NAND flash memory block 210 in the SRAM block.

In step 550, if PAGE_COUNT is less than 512 * 32, the RESET_A_M signal is changed to "H". After performing step 550, the process returns to step 503.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, the present invention can interface with the memory of the next mobile communication terminal to replace the high capacity and low price NAND flash memory with the memory of the next mobile communication terminal instead of the NOR flash memory that is burdened with price, capacity, supply and purchase. Implementing the device as an ASIC chip can reduce the price of the terminal and improve the performance.

Claims (8)

A memory device for use in a mobile communication terminal, A NAND type flash memory for storing basic code data for initial setting of the terminal, driving software data for operation of the terminal, and storing service data transmitted and received for service in the terminal; A first memory capable of random access and storing the basic code data to be transmitted from the NAND flash memory upon initial setting of the terminal; A second memory capable of random access and storing the driving software data to be copied from the NAND flash memory upon completion of initial setting of the terminal; A transmission control block for automatically transmitting the basic code data stored in the NAND flash memory to the first memory when the terminal is powered on; Initialize the terminal by reading the basic code data from the first memory at the initial setting of the terminal, copy the driving software data from the NAND flash memory after the initial setting of the terminal is completed, and the second memory. And a control unit configured to drive the terminal by randomly accessing the driving software data stored in the second memory and to read and write service data transmitted and received to and from the terminal after the terminal is driven. And a memory device. 2. The apparatus of claim 1, further comprising an error correction block connected between the control unit and the NAND flash memory and performing error correction on data read and written between the control unit and the NAND flash memory. Characterized in that the memory device. The terminal of claim 1, further comprising: a first path connecting the NAND flash memory, the transmission control block, and the first memory; and a second path connecting the second memory and the control unit. And a buffer block opening between the first path and the second path at power-on and connecting the first path and the second path after the initial setting of the terminal is completed. Memory device. 4. The memory device of claim 3, wherein the buffer block includes at least one tri-state buffer configured to enter a high impedance state when the terminal is powered on to open a space between the first path and the second path. . The memory device of claim 1, wherein the NAND flash memory, the transmission control block, and the first memory are integrated into one chip. A memory control method in a mobile communication terminal having a NAND type flash memory and a memory device including a randomly accessible first memory and a second memory, Automatically transmitting basic code data stored in the NAND flash memory for the initial setting of the terminal to the first memory when the terminal is powered on; Initializing the terminal by reading the basic code data from the first memory upon initial setting of the terminal; After the initial setting of the terminal is completed, the driving software data stored for the operation of the terminal is copied from the NAND flash memory and stored in the second memory, and the driving software data stored in the second memory is randomly accessed for the operation. Driving the terminal; And reading and writing the service data transmitted to and received from the terminal to the NAND flash memory after the terminal is driven. The method of claim 6, further comprising performing error correction on data read and written between the controller and the NAND flash memory. The method of claim 6, wherein a first path connecting the NAND flash memory, the transmission control block, and the first memory when the terminal is powered on, and a second path connecting the second memory and the controller, respectively. And opening the connection between the first path and the second path after the initial setting of the terminal is completed.

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