KR100807118B1 - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device is provided to reduce current consumption in a termination circuit during termination operation while improving tAA using the termination circuit. A global data line transfers data between a core region and an interface region. A signal generation unit generates a termination enable signal in response to an internal column command signal and a column address predecoding signal. A driving unit(140) performs termination driving of the global data line with an expected termination voltage level in response to the termination enable signal. A latching unit(150) latches data loaded on the global data line.

Description

Semiconductor memory device {SEMICONDUCTOR MEMORY DEVICE}

1 is a block diagram for explaining a part of a configuration of a general semiconductor memory device.

FIG. 2 is a view for explaining a voltage level variation range of a global input / output line when the termination circuit of FIG. 1 is driven.

FIG. 3 is a circuit diagram illustrating the termination circuit of FIG. 1. FIG.

FIG. 4 is a timing diagram for describing an termination operation of the termination circuit of FIG. 3.

5 is a timing diagram for explaining a problem that may occur in a conventional termination circuit.

6 is a circuit diagram illustrating a termination circuit according to an embodiment of the present invention.

FIG. 7 is a timing diagram illustrating the termination operation of the termination circuit of FIG. 6. FIG.

* Explanation of symbols for the main parts of the drawings

100: termination circuit 110: set signal generation unit

120: reset signal generation unit 130: SR latch unit

140: termination drive unit 150: latch unit

NAND1, NAND2: NAND gate PM1: PMOS transistor

NM1: NMOS transistor PMD1: PMOS diode

NMD1: NMOS diode R1, R2, resistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a semiconductor memory device using a termination scheme on a data line.

In recent years, as the capacity of semiconductor memory devices increases, the size of chips increases, and thus the length of data lines increases. In general, data lines used in semiconductor memory devices are classified into segment input / output lines, local input / output lines (LIO), and global input / output lines (GIO), and the like, in particular, termination circuits in the global input / output lines (GIO). When the termination circuit is connected, the terminating operation of the global input / output line (GIO) is performed.

Briefly describing the termination operation, the global input / output line is precharged to the termination voltage level (V_TERM), e.g., the ½ voltage level of the external voltage (VDD), before the data is loaded onto the global input / output line (GIO). Termination operation is also performed in the applied section to reduce the voltage level change, that is, the swing width, according to data in the global input / output line (GIO). As a result, the current swing may be reduced due to the small swing width of the global input / output line GIO, and the time parameter 'tAA' of the semiconductor memory device may be reduced.

Meanwhile, in the case of semiconductor memory devices including synchronous DRAM (SDRAM), the number of data prefetches that determine the number of global input / output lines (GIO) has also increased as DDR (Double Data Rate) has evolved from DDR2 to DDR3. In other words, based on the data option of 'x16', 32 bit I / O is required for DDR, so 32 global I / O lines (GIO) are needed, and 64 bit I / O is required for DDR2. GIO). In addition, DDR3 is an 8-bit prefetch, requiring 128 global input / output lines (GIO). As such, the increasing number of global input / output lines (GIO) has become a major cause of increasing current consumption during input / output of data, and many problems have arisen as the spacing between lines decreases.

1 is a block diagram illustrating a part of a general semiconductor memory device.

Referring to FIG. 1, in a read operation, data stored in a cell (not shown) is transferred to the read sense amplifier 20 through a local input / output line LIO and amplified by the sense amplifier 20. The collected data are transferred to the data output mux 30 through the global input / output line GIO. The data muxed by the data output mux 30 is output to the pad 50 through the pipe latch unit 40. In addition, during the write operation, the data input through the pad 50 is amplified by the write sensing amplifier 60 and transferred to the write driver 70 through the global input / output line GIO. These data are driven by the write driver 70 and stored in the cell through the local input / output line (LIO).

At this time, the voltage level of the global input / output line GIO is fully swinged to the CMOS level from the external voltage VDD to the ground voltage VSS according to the data. The termination circuit 10 transmits data to the global input / output line GIO. Termination is performed before the signal is loaded, thereby precharging the global input / output line GIO to the ½ voltage level of the external voltage VDD. In addition, since the termination operation continues, the global input / output line GIO swings only by 'VDD / 2 (logic threshold voltage) ± ΔV' without full swing even when data is applied.

FIG. 2 is a diagram for describing a voltage level variation range of the global input / output line GIO when the termination circuit 10 of FIG. 1 is driven.

Referring to FIG. 2, when the termination circuit 10 is not driven (OFF_TERM), the voltage level variation of the global input / output line GIO is fully swinged from the external voltage VDD to the ground voltage VSS. In contrast, when the termination circuit 10 is driven (ON_TERM), the global input / output line GIO swings only by 'VDD / 2 ± ΔV'.

FIG. 3 is a circuit diagram illustrating the termination circuit 10 of FIG. 1.

Referring to FIG. 3, the termination circuit 10 includes an NMOS transistor NM1 that is turned on in response to a termination enable signal EN_TERM, and a PMOS transistor that is turned on in response to an inverted termination activation signal. PM1), a PMOS / NMOS diode connected between the NMOS transistor NM1 and the PMOS transistor PM1 to distribute an external voltage VDD and resistors PMD1, NMD1, R1, and R2, and a global input / output line. A latching unit 11 may be further configured to latch data loaded on the GIO.

The termination circuit 10 performs the termination operation when the termination enable signal EN_TERM is logic 'high' and performs the termination operation when the termination enable signal EN_TERM is logic 'low'. I never do that. Therefore, the termination circuit 10 precharges the voltage level of the global input / output line GIO to the termination voltage level V_TERM during the termination operation, and when the data is loaded, the termination voltage level V_TERM collides with each other. This prevents the full swing of the voltage level of the global input / output line (GIO).

The latching unit 11 is enabled when the termination enable signal EN_TERM is logic 'low', and latches logic 'high' or logic 'low' according to data contained in the global input / output line GIO. .

FIG. 4 is a timing diagram illustrating the termination operation of the termination circuit 10 of FIG. 3.

Referring to FIG. 4, the respective read command signals (Internal ReaD Pulse (IRDP)) are signals generated at the read command, and the input / output strobe signal IOSTBP is used to read the read sense amplifier 20. 'YBSTC' signal is a logic 'high' by the internal read command signal (IRDP) and transitions to logic 'low' according to the burst length, and the termination enable signal EN_TERM is 'YBSTC'. When the signal goes to logic high, it is set to logic high and the YBSTC signal transitions to logic low and then resets to logic low after a certain delay.

For example, when the logic 'high' is latched to the global input / output line GIO, when the logic 'low' data is read, the termination enable signal EN_TERM is activated so that the voltage level of the global input / output line GIO is increased. It is gradually lowered to the termination voltage level (V_TERM). Thereafter, when the input / output strobe signal IOSTBP is activated in the termination voltage level V_TERM state, the read detection amplifier 20 is driven to lower the voltage level of the global input / output line GIO. The data output mux 30 recognizes the voltage level of the global input / output line GIO sufficiently low, and the global input / output line GIO maintains the termination voltage level V_TERM again.

In the conventional configuration, the termination circuit 10 forms a direct current pass in the interval in which the termination enable signal EN_TERM is activated to consume current. In order to reduce the current consumed, a resistor with a large resistance value can be attached to the termination circuit 10 to minimize the current consumed during the termination operation.However, in this case, the global input / output line GIO during the termination operation terminates the termination voltage level V_TERM. It will take a long time to get there.

5 is a timing diagram illustrating a problem that may occur in the conventional termination circuit 10. Since each signal of FIG. 5 is the same as that described with reference to FIG.

Referring to FIG. 5, in order to minimize the current consumed by the termination circuit 10, a large resistor may be attached, or the voltage level of the global input / output line GIO may vary depending on process, voltage, and temperature (PVT). This is a case where the termination voltage level V_TERM is not sufficiently lowered. In this case, even if the sense amplifier 20 is driven in response to the input / output strobe signal IOSTBP, the voltage level of the global input / output line GIO may not be accurately determined by the data output mux 30. Occurs. In particular, such a situation occurs when the data latched in the global input / output line GIO and the data to be driven in the read sense amplifier 20 are different. In a serious case, the data output mux 30 in the read sense amplifier 20 You will recognize the exact opposite of the data you want to drive. This results in a loss of reliability of data and circuit operation.

4 and 5, the resistance of the termination circuit 10 may be increased to reduce the DC current consumed in the activation period of the termination enable signal EN_TERM. However, the global input / output line GIO ) Takes a long time to reach the termination voltage level (V_TERM), which could cause circuit malfunction in severe cases. However, if the termination circuit 10 is not configured, a problem arises in that DC current is consumed and 'tAA' is increased as the global input / output line (GIO) needs to swing full.

On the other hand, when data is applied to the global input / output line GIO, the termination voltage level V_TERM and the data cause a collision with each other, thereby preventing full swing. However, in the situation where the gap between each global input / output line (GIO) is reduced according to the development of the technology, this is affected by the coupling by the adjacent lines, which causes distorted data.

The present invention has been proposed to solve the above problems of the prior art, it is possible to use the termination circuit to speed up 'tAA', reduce the current consumed in the termination circuit during the termination operation, coupling effect by adjacent lines It is an object of the present invention to provide a semiconductor memory device that can receive less.

According to an aspect of the present invention for achieving the above object, a global data line for transferring data between the core region and the interface region; Signal generating means for generating a termination enable signal in response to the internal column command signal and the column address predecoding signal; And driving means for terminating the global data line at a predetermined termination voltage level in response to the termination enable signal.

According to the present invention, it is possible to reduce the termination driving interval of the global input / output line (GIO) and effectively consume current only during the termination operation, and the margin of the data applied to the global input / output line (GIO)-logic 'high' data and logic By increasing the voltage level displacement of the 'low' data to be less affected by adjacent lines, excessive current consumption and malfunction caused by the conventional circuit can be prevented.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

6 is a circuit diagram illustrating a termination circuit 100 according to an embodiment of the present invention.

Referring to FIG. 6, the termination circuit 100 includes a core area-an area in which the read sense amplifier 20 and the write driver 70 are located in FIG. 1-and an interface area-the data output mux 30 and write detection in FIG. 1. A set signal generator 110 generating a set signal S_SET in response to an internal read command signal IRDP and a global input / output line GIO for transferring data input / output between the region where the amplifier 40 is located. And a signal obtained by predecoding a plurality of column addresses corresponding to each bank (e.g., eight banks, not shown in the figure) (LAY01PD_B0, LAY01PD_B1, LAY01PD_B2, LAY01PD_B3, LAY01PD_B4, respectively corresponding to eight banks). , LAY01PD_B7: LAY01PD_Bi, where 'i' denotes a corresponding bank), a reset signal generator 120 generating a reset signal S_RES in response to at least one of the banks, and a set signal S_SET and a reset signal S_RES. Termination Enable Scene in response to SR latch unit 130 for generating EN_TERM, and the global input / output line GIO in response to the termination enable signal EN_TERM to a predetermined termination voltage level, e.g., the ½ voltage level of the external voltage VDD. And a termination driver 140 for driving.

Here, the internal read command signal IRDP is a pulse signal that is active at logic 'high' during a read operation, and the 'LAY01PD_Bi' signal is an input / output strobe signal IOSTBP in a bank during a read operation. A logic 'low' active pulse signal produced before the activation signal of the read sense amplifier 20 of FIG.

On the other hand, the SR latch unit 130 is a first NAND gate (NAND1) receiving the set signal (S_SET) and the output signal of the second NAND gate (NAND2), the output signal and the reset signal of the first NAND gate (NAND1) A second NAND gate NAND2 receiving S_RES may be provided, and an output signal of the first NAND gate NAND1 may be driven at the second stage of the inverter to generate a termination enable signal EN_TERM. Thus, the termination enable signal EN_TERM is set to logic 'high' in response to the set signal S_SET and reset to logic 'low' in response to the reset signal S_RES.

In addition, the termination driver 140 includes an NMOS transistor NM1 turned on with the termination enable signal EN_TERM and a PMOS transistor PM1 turned on with a signal inverting the termination enable signal EN_TERM. And a PMOS diode PMD1 formed between the NMOS transistor NM1 and the PMOS transistor PM1 to adjust the amount of DC current, resistors R1 and R2, and an NMOS diode NMD1. In this case, the resistance values of the resistors R1 and R2 may use small resistance values, which will be described below in detail with reference to FIG. 7.

Meanwhile, a latch unit 150 may be further provided to latch data loaded on the global input / output line GIO, and the latch unit 150 is a three-state latch, and the termination enable signal EN_TERM is logic 'low'. In this case, the latch operation is performed, and when the termination enable signal EN_TERM is logic 'high', the latch operation is stopped. This is also to prevent the global input / output line GIO from floating in a section other than the termination operation.

FIG. 7 is a timing diagram illustrating the termination operation of the termination circuit 10 of FIG. 6. Since each signal is as described with reference to FIG. 6, a description thereof will be omitted.

Referring to FIG. 7, for example, when the global input / output line GIO reads data of logic 'low' while logic 'high' is latched, the termination enable signal EN_TERM is an internal read command signal IRDP. ), The global input / output line GIO is gradually lowered to the termination voltage level V_TERM. At this time, since the resistors R1 and R2 having a small resistance value are used, the global input / output line GIO can be quickly terminated. After the termination operation, the termination enable signal EN_TERM is reset in response to the 'LAY01PD_Bi' signal, so that the termination circuit 100 stops the operation. Therefore, the global input / output line GIO slightly shifts the voltage level to the external voltage VDD or the ground voltage VSS according to the latched value of the latch unit 150. Here, the rising to the external voltage VDD is shown. However, this fluctuating voltage level is so small that it can be ignored. When the input / output strobe signal IOSTBP is activated in this state, the read sense amplifier 20 is driven so that the global input / output line GIO has a lower voltage level according to the applied logic 'low' data. The data output mux 30 of FIG. 1 can recognize the voltage level of the global input / output line GIO lowered to the ground voltage VSS.

That is, in the related art, in order to suppress DC current consumption during a long activation period of the termination enable signal EN_TERM, the resistance value of the termination circuit has to be increased, and thus, many problems have occurred. However, in the present invention, by using the termination enable signal EN_TERM that activates the short period and the resistors R1 and R2 having a smaller resistance value than before, the current can be efficiently consumed only in the desired period. In addition, since the termination enable signal EN_TERM is only activated up to the termination voltage level V_TERM, the DC current is not consumed thereafter. In addition, when data is applied to the global input / output line GIO, the termination circuit 100 does not operate. Therefore, the global input / output line GIO is at the voltage level of the external voltage VDD or the ground voltage VSS according to the data. As a result, the coupling effect to the global input / output line (GIO) and the adjacent line is less.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment, the case where the termination of the global input / output line (GIO) is possible during the read operation has been described as an example. However, the present invention may be applied to the termination of the global input / output line (GIO) during the write operation. have. In addition, the present invention can be applied to data lines for transmitting and receiving data as well as global input / output lines (GIO).

By using the termination circuit described above, the present invention can reduce tAA, efficiently consume current, reduce unnecessary DC current, and receive less coupling effect on adjacent lines. Clear data can be loaded on the global input / output line (GIO), so that the operation of the semiconductor memory device can be more precise and stable.

In addition, by reducing the chip size by using a resistor with a small resistance value in the termination circuit, the profitability can be improved.

Claims (10)

A global data line for transferring data between the core region and the interface region; Signal generating means for generating a termination enable signal in response to the internal column command signal and the column address predecoding signal; And Driving means for driving termination of the global data line to a predetermined termination voltage level in response to the termination enable signal A semiconductor memory device having a. The method of claim 1, And latching means for latching data carried on the global data line. The method of claim 2, And said latching means is a tri-state latch responsive to said termination enable signal. The method according to claim 1 or 2, The signal generating means, First signal generating means for generating a first signal for driving the global data line in a read operation; Second signal generating means for generating a second signal for terminating the global data line during a write operation; And And output means for receiving the first and second signals and outputting the termination enable signal. The method according to claim 1 or 2, And the termination voltage level is ½ of an external voltage. A global data line for transferring data between the core region and the interface region; A set signal generator for generating a set signal in response to an internal read command signal; A reset signal generator for generating a reset signal in response to a plurality of column address predecoding signals corresponding to each bank; An SR latch unit for generating a termination enable signal in response to the set signal and the reset signal; And Driving means for driving termination of the global data line to a predetermined termination voltage level in response to the termination enable signal A semiconductor memory device having a. The method of claim 6, And latching means for latching data carried on the global data line. The method of claim 7, wherein And said latching means is a tri-state latch responsive to said termination enable signal. The method according to claim 6 or 7, The SR latch portion A first NAND gate receiving the set signal at one side; The reset signal is input to one end and the output terminal of the first NAND gate is connected to the other end, and its output terminal has a second NAND gate connected to the other end of the first NAND gate, And the first NAND gate outputs the termination enable signal. The method according to claim 6 or 7, And the termination voltage level is ½ of an external voltage.

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