KR100803264B1 - Lateral insulated gate bipolar transistor - Google Patents

Abstract

The present invention provides a lateral insulated gate bipolar transistor having excellent prevention of latch-up.

The lateral insulated gate bipolar transistor of the present invention is formed over a plurality of adjacent single crystal silicon regions which are insulated from each other from a semiconductor substrate, and a stripe collector formed on each main surface of the plurality of single crystal silicon regions. There are four or more collectors arranged at the ends of the single crystal silicon regions with the stripe emitters arranged opposite to the collectors therebetween.

Description

Lateral insulated gate bipolar transistors {LATERAL INSULATED GATE BIPOLAR TRANSISTOR}

1 is a schematic diagram of a cross-sectional structure of a lateral insulated gate bipolar transistor of Example 1,

2 is a schematic diagram of a planar structure of a lateral insulated gate bipolar transistor of Example 1;

3 is a schematic diagram of a cross-sectional structure of a lateral insulated gate bipolar transistor of Example 2. FIG.

※ Explanation of code for main part of drawing

1, 2: main surface 3: polycrystalline silicon

4: oxide film 5: n-type buried layer

6, 6 ', 6 ": single crystal silicon region 7, 15: p type diffusion layer

8: insulating film 9: n-type diffusion layer

11 gate electrode 12 gate oxide film

13 collector electrode 13 'collector wiring

14 emitter electrode 14 'emitter wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a lateral insulated gate bipolar transistor, and more particularly to a lateral insulated gate bipolar transistor with excellent latch-up prevention.

Recently, an insulated gate bipolar transistor (hereinafter referred to as IGBT), which combines high speed and low on-resistance, has been used as a power switching element. The IGBT forms a p-type base region extending inwardly from one surface of the n-type semiconductor substrate serving as a drift region and an n-type emitter region extending inwardly from the surface of the base region, and the other surface of the semiconductor substrate. The p-type collector region is formed away from the base region, and the emitter electrode is provided in the emitter region and the base region, and the collector electrode is provided in the collector region. In the IGBT, when the collector electrode applies a voltage having a positive potential than the emitter electrode, and a positive potential is applied to the gate electrode, electrons in the emitter region reach the collector region through the channel and the drift region. The electrons reaching the collector region prompt the injection of holes from the collector region, whereby the high-resistance drift region is modulated with conductivity to become a low-resistance region, so that the p-type drain has no function of injecting the collector region in approximately the same structure. On-resistance lower than that of the MOSFET switched to the area can be realized.

In the case of realizing an IC by integrating such an IGBT with other circuit elements, a horizontal structure (lateral structure) in which an emitter electrode, a collector electrode, and a gate electrode are provided on the same surface of a semiconductor substrate in order to facilitate mutual connection. desirable. IGBT of this structure is described in patent document 1. As shown in FIG. On the other hand, since the IGBT has a limit on the current value that can flow in the unit unit constituted by the collector emitter pair, the desired current capacity is realized by integrating many unit IGBTs in the semiconductor body.

In the IGBT described in Patent Literature 1, the emitter region, the base region, and the collector region have a comb shape on the surface of the semiconductor substrate, and the comb teeth are combined. The gate electrode is provided on the base region, the drift region and the emitter region in the vicinity thereof via an insulating film. An emitter electrode and a collector electrode are provided on the emitter region, the base region, and the collector region, respectively, and both electrodes have a comb-like shape, and the comb-tooth portions of both are combined.

In addition, since the IGBT is integrated with other circuits to realize an IC, the IGBT and, if necessary, other devices are separated from each other by dielectric isolation techniques. In this way, an IC having a circuit function can be realized by combining devices of different kinds.

[Patent Document 1]

Japanese Patent Laid-Open No. 5-29614 (FIGS. 1, 2, 5, and 9)

When a lateral IGBT is formed on a dielectric separation substrate having an n-type buried layer, there are two paths for electrons in the emitter region to reach the collector electrode. One is the first path that moves from the adjacent (paired) collector region to the collector electrode via the channel and the drift region, and the other is from the collector region at the end of the IGBT to the collector electrode via the channel, drift region and the n-type buried layer. The second path to travel. Due to the presence of the second path, a larger amount of current flows in the unit IGBT at the end than in the other unit IGBTs. This means current concentration for the end unit IGBT, resulting in a latch-up configuration at the current concentration. As a result, the current to control the IGBT was at a level below the design value.

SUMMARY OF THE INVENTION An object of the present invention is to provide a lateral insulated gate bipolar transistor with excellent latch-up prevention.

In the horizontal IGBT of the present invention, the number of collectors arranged at the end of the single crystal silicon region is increased to four or more by dividing the single crystal silicon region forming the IGBT into two or more.

EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described in detail using drawing.

(Example 1)

This embodiment is shown and described in FIG. 1 and FIG. 1 is a schematic diagram showing a cross-sectional structure of an n-type lateral IGBT of the present embodiment, and FIG. 2 is a schematic diagram for explaining a planar pattern of a lateral IGBT. As shown in FIG. 1, the n-type lateral IGBT of this embodiment has a dielectric separation substrate having single-crystal silicon regions 6 and 6 'of n-type silicon insulated and separated from the polycrystalline silicon 3 with oxide films 4 and 4'. It is formed on the top.

First, the manufacturing process of the IGBT of this embodiment is demonstrated. The n-type silicon single crystal substrate is etched from the main surface 2 using an alkali anisotropic photoetch technique to form the single crystal silicon region 6 and the single crystal silicon region 6 '. Next, ion implantation is performed in the single crystal silicon region 6 and the single crystal silicon region 6 'to form the n-type buried layer 5. Next, an oxide film 4 separating the single crystal silicon region 6 and the single crystal silicon region 6 'is grown. Next, the polycrystalline silicon 3 for supporting the single crystal silicon region 6 and the single crystal silicon region 6 'is deposited, and the polycrystalline silicon 3 is ground to be flattened. Next, the other main surface 1 of the n-type silicon substrate serving as the element formation region is ground until the oxide film 4 for element isolation appears to produce a dielectric separation substrate.

A lateral IGBT is formed in each of the single crystal silicon region 6 and the single crystal silicon region 6 'of the prepared dielectric separation substrate. 1 is a p-type diffusion layer forming an IGBT channel, 9 is an n-type diffusion layer forming an emitter, and the p-type diffusion layer 15 and the n-type diffusion layer 9 are connected to the emitter electrode 14. Is shorted. Reference numeral 11 in FIG. 1 denotes a gate electrode of polysilicon, 12 a gate oxide film, and 8 an insulating film. 1 is a p-type diffusion layer which comprises a collector, and 13 is a collector electrode. In the IGBT of the present embodiment, the p-type diffusion layer 7 constituting these collectors and the n-type diffusion layer 9 constituting the emitters are arranged to face each other in a stripe shape extending to the main surface 1. The lengths of the type diffusion layer 7 and the n type diffusion layer 9 are substantially the same, and the p type diffusion layer 7 constituting the collector is arranged in the outermost column as shown in FIG. 1. As described above, in the IGBT according to the present embodiment, the p-type diffusion layer 7 constituting these collectors and the n-type diffusion layer 9 forming the emitter are alternately arranged in a plurality of comb-toothed shapes, and the stripe shape for forming channels is also provided. The stripe-type gate oxide film 12 constituting the gate and the gate electrode 11 of polysilicon are disposed on the p-type diffusion layer 15, and the stripe-shaped p-type diffusion layer 15 forming the channel is formed by emitters. It arrange | positioned at both sides of the n type diffused layer 9 to form.

Fig. 2 shows a planar structure of the lateral IGBT of this embodiment. A lateral IGBT is formed in each of the two adjacent single crystal silicon regions 6 and the single crystal silicon region 6 ', and one end of the emitter electrode 14 of each IGBT is connected to the emitter wiring 14', Moreover, one end of the collector electrode 13 of each IGBT was connected by the collector wiring 13 '. In addition, the emitter electrodes 14 of the horizontal IGBTs formed in each of the two adjacent single crystal silicon regions 6 and the single crystal silicon region 6 'are connected to each other by the emitter wiring 14', and the collector electrode 13 ) Were connected to the collector wiring 13 '. As described above, in this embodiment, the single crystal silicon region forming the lateral IGBT is divided into two, so that the number of unit IGBTs in one single crystal silicon region is reduced. In other words, in this embodiment, since the single crystal silicon region forming the lateral IGBT is divided into two, the p-type diffusion layer 7 constituting the outermost column collector formed in the single crystal silicon region is increased from two stripes to four stripes. It was. As a result, current concentration to the collector of the unit IGBT disposed at the end of the single crystal silicon region can be alleviated.

1 and 2, two adjacent single crystal silicon regions 6 and single crystal silicon regions 6'are n-type without passing through the polycrystalline silicon 3 with only the oxide film 4 serving as an insulating layer therebetween. It is in contact with the main surface 1 of the silicon substrate.

In the structure of the above-described horizontal lateral IGBT, a plurality of unit IGBTs are arranged in one single crystal silicon region in order to obtain a desired current capacity, and a current flows from the channel to the two unit IGBTs at both ends via the n-type buried layer 5. Is concentrated, and there is a case where latch-up occurs at the portion where this current is concentrated. However, in the present embodiment, as shown in FIG. 1, the single crystal silicon region is divided into two, and the number of unit IGBTs in one single crystal silicon region is reduced to alleviate the current concentration to the end unit IGBT, thereby making it difficult to generate latch-up. It was.

Thus, according to this embodiment, the number of unit IGBTs of one single crystal silicon region insulated and separated by the oxide film 4 is reduced to six, and conversely, the number of p-type diffusion layers 7 constituting the outermost column collector is reduced in the entire IGBT. Since the number is increased to four, the current flowing through the n-type buried layer 5 through the collector of the IGBT end can be reduced.

(Example 2)

The cross-sectional structure of the n type horizontal IGBT of a present Example is shown in FIG. In the present embodiment, as shown in Fig. 3, horizontal IGBTs are formed over three single crystal silicon regions 6, 6 ', and 6 ", and the IGBTs formed in each single crystal silicon region are connected in parallel as in the first embodiment.

Also in the present embodiment, as in Example 1, the number of unit IGBTs formed in the three single crystal silicon regions 6, 6 ', and 6 ", respectively, is reduced to four as shown in FIG. The number of p-type diffusion layers 7 is increased to six in the entire IGBT, thereby alleviating the current concentration to the collector of the unit IGBT disposed at the end of the single crystal silicon region even in the n-type horizontal IGBT of this embodiment. The latch-up prevention performance can be improved.

In addition, the number of single crystal silicon regions connected in parallel to form one lateral IGBT is not limited to two or three, and the same effect is obtained when there are a plurality. An important point of the present invention is to form IGBTs in a plurality of adjacent dielectric separated single crystal silicon regions and connect unit IGBTs in parallel to reduce the number of unit IGBTs in one single crystal silicon region, and to form a p-type diffusion layer constituting the outermost collector. To increase the number of (7).

(Example 3)

In the present embodiment, in the n-type lateral IGBTs of Examples 1 and 2, the p-type lateral IGBT was obtained in which the single crystal silicon region 6 and the conductivity type of each diffusion layer were reversed. The other than this structure is the same as that of Example 1, Example 2.

In the p-type horizontal IGBT of the present embodiment, similarly to the n-type horizontal IGBTs of Examples 1 and 2, IGBTs are formed in a plurality of adjacent dielectric separated p-type single crystal silicon regions, and the unit IGBTs are connected in parallel. The number of unit IGBTs in one single crystal silicon region was reduced, and the number of n-type diffusion layers constituting the outermost column collector was increased. As a result, current concentration to the collector of the unit IGBT disposed at the end of the single crystal silicon region can be alleviated, and the latch-up prevention performance can be improved.

According to the present invention, the current flowing from the emitter to the collector of the end portion of the single crystal silicon region through the n-type buried layer can be reduced.

Claims (10)

delete delete delete delete delete A horizontal insulated gate bipolar transistor formed on a dielectric separation substrate having a semiconductor substrate and a single crystal silicon region of a first conductivity type insulated and separated from the semiconductor substrate by an oxide film. The first conductive single crystal silicon region is provided with a buried layer of a first conductivity type in contact with the oxide film, And said lateral insulated gate bipolar transistor is formed over a plurality of adjacent single crystal silicon regions of a first conductivity type insulated from and separated from each other. The method of claim 6, The stripe-shaped second conductive type collector formed on each of the main surfaces of the plurality of single crystal silicon regions has the stripe-type first conductive type emitter disposed to face the collector. Horizontal insulated gate bipolar transistor. The method of claim 7, wherein The horizontal type channel of the 2nd conductivity type was extended between the said 2nd conductivity type collector and the said 1st conductivity type emitter which were formed in each main surface of the said single crystal silicon area | region. Insulated gate bipolar transistors. In a lateral insulated gate bipolar transistor formed on a dielectric separation substrate having a single crystal silicon region insulated from a semiconductor substrate, The lateral insulated gate bipolar transistors are insulated from each other and are formed over a plurality of adjacent single crystal silicon regions, A stripe collector formed on each of the main surfaces of the plurality of single crystal silicon regions has a stripe emitter disposed to face the collector. And at least four stripe collectors arranged at the ends of the main surfaces of the plurality of single crystal silicon regions. The method of claim 9, A plurality of stripe collectors and stripe emitters are arranged on each of the main surfaces of the plurality of single crystal silicon regions, and one end of the collector electrodes arranged on the stripe collectors is connected to each other, One end of the emitter electrode disposed on the stripe emitter is connected to each other, and the collector electrode and the emitter electrode connected to each other are arranged in a comb-tooth shape.

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