KR100800307B1 - Image sensor, and method for controlling pixel circuit and sample and holder - Google Patents

Abstract

The present invention relates to a pixel circuit for an image sensor, a method for controlling a sample and a holder, and an image sensor. More specifically, the present invention relates to a pixel circuit for a CMOS image sensor, a method for controlling a sample and a holder, and a CMOS image sensor. to be.

The present invention provides a method of controlling a pixel circuit for a CMOS image sensor, the method comprising: (a) maintaining a first transistor connected between a photodiode and a floating diffusion region and a second transistor connected between the floating diffusion region and an overflow capacitor in an off state; Resetting the floating diffusion region; (b) maintaining the first transistor in an off state, maintaining the floating diffusion region in a reset-released state, and turning on the second transistor to receive overflow charges that overflow from the photodiode to the floating diffusion region; Storing in an overflow capacitor; (c) repeating steps (a) and (b) at least once; And (d) outputting a low illuminance voltage corresponding to the charge accumulated in the photodiode and a high illuminance voltage corresponding to the overflow charge stored in the overflow capacitor.

Description

Image sensor, and method for controlling pixel circuit and sample and holder

1 is a diagram illustrating a pixel circuit of a conventional CMOS image sensor.

FIG. 2 is a signal diagram for describing an operation of the pixel circuit 10 of FIG. 1.

3 is a diagram illustrating a conventional image sensor including the pixel circuit of FIG. 1.

4 is a signal diagram illustrating a control method according to an embodiment of the present invention.

5 is a flowchart illustrating a method of controlling a sample and a holder according to an embodiment of the present invention.

FIG. 6 schematically shows a sample and a holder 41 in which the control method of FIG. 5 is performed.

7 is a flowchart illustrating a method of controlling a sample and a holder according to another embodiment of the present invention.

FIG. 8 schematically shows a sample and a holder 42 in which the control method of FIG. 7 is performed.

FIG. 9 is a diagram illustrating an image sensor employing a method of controlling a sample and a holder described with reference to FIGS. 7 and 8.

FIG. 10 is a diagram for describing the ADC 80 of FIG. 9 in detail.

FIG. 11 is a timing diagram for describing an operation of the image sensor illustrated in FIGS. 9 and 10, and in particular, when an overflow does not occur.

FIG. 12 is a timing diagram for describing an operation of the image sensor illustrated in FIGS. 9 and 10, and particularly, when an overflow occurs.

* Explanation of symbols in the main part of the drawing *

PD: photodiodes M1 to M5: first to fifth transistors

FD: Floating Diffusion Area CS: Overflow Capacitor

10 pixel circuit 20 pixel array

30: low drive unit 40, 41, 42, 50: sample and holder

60, 61, 70: column driver 80: ADC

81: CDS circuit 82: CDS control circuit

83: comparator 84: first latch

85: counter 86: second latch

The present invention relates to a pixel circuit for an image sensor, a method for controlling a sample and a holder, and an image sensor. More specifically, the present invention relates to a pixel circuit for a CMOS image sensor, a method for controlling a sample and a holder, and a CMOS image sensor. to be.

In recent years, with the widespread use of digital cameras, digital camcorders, and mobile phones including their functions, image sensors are rapidly developing. An image sensor is a semiconductor device that converts an optical image into an electrical signal. The image sensor may be classified into a charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor. . Among them, the CCD image sensor is not easy to be single-chip with the CMOS circuit, there is a problem that the power consumption is high. In contrast, a CMOS image sensor has advantages in that it can be easily chipped with a CMOS circuit, has low power consumption, and can be manufactured using a general CMOS process. Therefore, in recent years, the development of the CMOS image sensor has been concentrated.

The prior art of such a CMOS image sensor is "shigetoshi sugawa et al., A 100dB Dynamic Range CMOS Image Sensor Using a Lateral Overflow Integration Capacitor, 2005 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 352-353 "There is a technique disclosed in. The prior art disclosed in the above document will be briefly described with reference to FIGS.

1 is a diagram illustrating a pixel circuit of a conventional CMOS image sensor. Referring to FIG. 1, the pixel circuit 10 includes a photodiode PD, first through fifth transistors M1, M2, M3, M4, and M5 and an overflow capacitor CS. The first to fifth transistors M1, M2, M3, M4, and M5 are CMOS transistors.

The photodiode PD performs a function of generating a charge corresponding to the input light.

The first transistor M1 is connected between the photodiode PD and the floating diffusion region FD and operates according to the first control signal CS1. The floating diffusion region FD stores a charge generated in the photodiode PD. In principle, when the first transistor M1 is turned off by the first control signal CS1, the charge generated in the photodiode PD is not transferred to the floating diffusion region FD and the photodiode PD is applied. Accumulate within. In addition, when the first transistor M1 is turned on by the first control signal CS1, the charge accumulated in the photodiode PD is transferred to the floating diffusion region FD. However, when high intensity light such as sunlight is input to the photodiode PD, a large amount of charge is generated in the photodiode PD. The electric charge generated in this way overflows the gate potential barrier of the first transistor M1 to the floating diffusion region FD even when the first transistor M1 is in an off state. The charges transferred to the floating diffusion region FD due to the overflow are referred to as 'overflow charge' in this specification. In addition, among the charges generated in the photodiode PD, the charge accumulated in the photodiode PD without overflowing is simply referred to as “charge accumulated in the photodiode”.

The overflow capacitor CS performs a function of storing the overflow charge.

The second transistor M2 is connected between the floating diffusion region FD and the overflow capacitor CS and operates according to the second control signal CS2.

The third transistor M3 is connected between the power supply voltage and the floating diffusion region FD and performs a function of resetting the floating diffusion region FD according to the third control signal CS3.

The fourth transistor M4 acts as a source follower buffer amplifier to amplify and output the voltage of the floating diffusion region FD. Due to the characteristics of the source follower buffer amplifier, the voltage gain of the fourth transistor M4 may be 1.

The fifth transistor M5 operates according to the fourth control signal CS4 and outputs a voltage output from the fourth transistor M4, that is, a voltage of the amplified floating diffusion region FD.

FIG. 2 is a signal diagram for describing an operation of the pixel circuit 10 of FIG. 1.

Referring to FIG. 2, the first control signal CS1 is applied in the first period P11 to turn off the first transistor M1 in one period. Since the first transistor M1 is in the off state, charge generated in the photodiode PD is accumulated in the photodiode PD, and only the overflow flow moves to the floating diffusion region FD. Since the second control signal CS2 and the third control signal CS3 are applied such that the second transistor M2 is turned on and the third transistor M3 is turned off, the second transistor M2 is moved to the floating diffusion region FD. The overflow charges generated are stored in the overflow capacitor CS. Since the fourth control signal CS4 is applied such that the fifth transistor M5 is turned off, the voltage of the amplified floating diffusion region FD is not output.

In the second period P12, the third control signal CS3 is applied such that the third transistor M3 is turned on, and the floating diffusion region FD is reset. In this period, the first and second control signals CS1 and CS2 are applied so that the first and second transistors M1 and M2 are turned off. In addition, the fourth control signal CS4 is applied such that the fifth transistor M5 is turned on, and the pixel circuit 10 outputs a voltage corresponding to the charge located in the floating diffusion region FD. In this case, the output voltage is used to remove noise components of the low illuminance voltage VSN1, which is the voltage output in the third period P13. In this specification, the voltage used to remove the noise component of the low light voltage VSN1 is referred to as the low light noise voltage VN1.

In the third period P13, the first control signal CS1 is applied so that the first transistor M1 is turned on, and the charge accumulated in the photodiode PD moves to the floating diffusion region FD. In this period, the second and third control signals CS2 and CS3 are applied so that the second and third transistors M2 and M3 are turned off. In addition, the fourth control signal CS4 is applied such that the fifth transistor M5 is turned on, and the pixel circuit 10 outputs a voltage corresponding to the charge located in the floating diffusion region FD. In this case, the output voltage is a voltage corresponding to the charge accumulated in the photodiode PD, and is a useful voltage when light of low illumination that does not cause overflow is incident on the photodiode PD. In this specification, a voltage that is effective when light of low illumination is incident is referred to as a low illumination voltage VSN1.

In the fourth period P14, the first and second control signals CS1 and CS2 are applied such that the first and second transistors M1 and M2 are turned on, and are accumulated in the photodiode in the floating diffusion region FD. Charges and overflow charge stored in the overflow capacitor are located. In this period, the third control signal CS3 is applied such that the third transistor M3 is turned off. In addition, the fourth control signal CS4 is applied such that the fifth transistor M5 is turned on, and the pixel circuit 10 outputs a voltage corresponding to the charge located in the floating diffusion region FD. In this case, the output voltage is a voltage corresponding to the charge stored in the overflow capacitor CS, and is a voltage useful when high intensity light causing an overflow is incident on the photodiode PD. In this specification, a voltage that is effective when light of high illumination is incident is referred to as high illumination voltage VSN2.

In the fifth period P15, the second and third control signals CS2 and CS3 are applied to turn on the second and third transistors M2 and M3 so that the floating diffusion region FD and the overflow capacitor CS) is reset. In this period, the first control signal CS1 is applied so that the first transistor M1 is turned off. In addition, the fourth control signal CS4 is applied such that the fifth transistor M5 is turned on, and the pixel circuit 10 outputs a voltage corresponding to the charge located in the floating diffusion region FD. At this time, the output voltage is used to remove the noise component of the high illuminance voltage VSN2. In this specification, the voltage used to remove the noise component of the high illuminance voltage VSN2 is referred to as a high illuminance noise voltage VN2.

The pixel circuit according to the prior art operates as described above to respond to the low light voltage VSN1 corresponding to the charge accumulated in the photodiode PD, the low light noise voltage VN1 corresponding to the noise component of the low light voltage, and the overflow charge. Outputs a high illuminance voltage VSN2 and a high illuminance noise voltage VN2 corresponding to the noise component of the high illuminance voltage.

3 is a diagram illustrating a conventional image sensor including the pixel circuit of FIG. 1.

Referring to FIG. 3, an image sensor includes a pixel array 20 including a plurality of pixel circuits, a row driver 30, first and second samples and holders 40 and 50, and a first pixel. And second column drivers 60 and 70.

Of these, the first sample and the holder 40 are used to sample the low light voltage VSN1 and the low light noise voltage VN1, and the second sample and holder 50 are the high light voltage VSN2 and the high light noise voltage. Used to sample (VN2).

The image sensor according to the prior art outputs a low illuminance voltage VSN1, a low illuminance noise voltage VN1, a high illuminance voltage VSN2 and a high illuminance noise voltage VN2 in this manner, thereby providing a wide dynamic range. Has the advantage. More specifically, the image sensor according to the prior art further includes the second transistor M2 and the overflow capacitor CS as compared to the prior art, thereby accumulating and outputting the overflow charge, and thus, the overflow. The operating range can be wider than in previous technologies that cannot store charge.

However, the image sensor according to the prior art has a problem that the pixel circuit must have a large capacity overflow capacitor CS in order to widen the operation range. However, there is a technical limitation in generating a large capacitor in a narrow pixel region, so that only an operating range of about 100 dB can be obtained as in the prior art. Further, the image sensor according to the prior art requires the first sample and holder 40 for the low light voltage VSN1 and the second sample and holder 50 for the high light voltage VSN2, i.e., two samples and the holder. Has the problem.

Accordingly, an object of the present invention is to solve the above problems, and provides a method of controlling a pixel circuit for an image sensor that can increase an operating range without increasing the capacity of an overflow capacitor.

In addition, the technical problem to be achieved by the present invention is to provide a control method and an image sensor of the sample and the holder for the image sensor that can sample the low and high illumination voltage using a single sample and the holder.

As a technical means for achieving the above object, a first aspect of the present invention provides a method for controlling a pixel circuit for a CMOS image sensor, comprising: (a) a first transistor connected between a photodiode and a floating diffusion region and the floating diffusion region; Resetting the floating diffusion region while keeping the second transistor coupled between the overflow capacitor and the overflow capacitor off; (b) maintaining the first transistor in an off state, maintaining the floating diffusion region in a reset-released state, and turning on the second transistor to receive overflow charges that overflow from the photodiode to the floating diffusion region; Storing in an overflow capacitor; (c) repeating steps (a) and (b) at least once; And (d) outputting a low illuminance voltage corresponding to the charge accumulated in the photodiode and a high illuminance voltage corresponding to the overflow charge stored in the overflow capacitor.

A second aspect of the invention includes the steps of: (a) sampling a low light voltage output from a pixel circuit by a sample and holder circuit; (b) comparing the low light voltage with a reference voltage to determine whether an overflow has occurred; And (c) if it is determined that an overflow has occurred as a result of performing step (b), the sample and holder circuit samples a high illuminance voltage, and overflow does not occur as a result of performing step (b). If not determined, the method provides a method of controlling the sample and holder circuit, the method comprising maintaining the sampled low illuminance voltage.

A third aspect of the present invention includes the steps of: (a) sampling a low light voltage and a low light noise voltage output from a pixel circuit by a sample and holder circuit; (b) determining whether an overflow has occurred by comparing the low light voltage from which noise corresponding to the difference between the low light voltage and the low light noise voltage is removed with a reference voltage; And (c) if it is determined that an overflow occurs as a result of performing step (b), the sample and holder circuit samples a high illuminance voltage and a high illuminance noise voltage, and performs the step (b). If it is determined that no overflow has occurred, the method provides a method of controlling the sample and holder circuit, the method comprising maintaining the sampled low light voltage and low light noise voltage.

A fourth aspect of the invention outputs a low light voltage corresponding to the charge accumulated in the photodiode and a low light noise voltage corresponding to the noise component of the low light voltage in the first period, and a high peak corresponding to the overflow charge in the second period. A pixel circuit outputting a high illuminance noise voltage corresponding to a nominal voltage and a noise component of the high illuminance voltage; And a digital conversion value corresponding to any one selected from the noise-reduced low light voltage and the noise-reduced high light voltage according to the magnitude of the noise-reduced low light voltage, and the digital conversion value being the low light voltage from which the noise is removed. And an analog-to-digital converter for outputting a flag bit indicating which of the noise canceled high illumination voltages corresponds to, wherein the noise canceled low illumination voltage corresponds to a voltage corresponding to a difference between the low illumination voltage and the low illumination noise voltage. And the high illumination voltage from which the noise is removed is a voltage corresponding to the difference between the high illumination voltage and the high illumination noise voltage.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in various forms, the scope of the present invention should not be construed in a way that is limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art.

4 is a signal diagram illustrating a control method according to an embodiment of the present invention. The control method shown in FIG. 4 can be used to control the pixel circuit 10 for the CMOS image sensor shown in FIG.

1 and 4, in the first period P21, the overflow charge is stored in the overflow capacitor CS while the reset of the floating diffusion region FD is repeated. More specifically, first, the first and second transistors M1 and M2 are turned off, and the first to third control signals CS1, CS2, and CS3 are applied to turn on the third transistor M3. do. In this period, the overflow charges from the photodiode PD are not stored in the overflow capacitor CS and are discharged through the third transistor M3. Thereafter, the first to third control signals CS1, CS2, and CS3 are applied such that the first transistor M1 and the third transistor M3 are turned off, and the second transistor M2 is turned on. In this period, the overflow charges from the photodiode PD are stored in the overflow capacitor CS. During the first period P21, the period for resetting the floating diffusion region FD as described above and the period for storing the overflow charge in the capacitor CS are repeated several times.

As described above, the control method according to the present invention, unlike the control method according to the related art, resets the floating diffusion region FD and overflows the overflow charge newly transferred to the floating diffusion region FD after the reset capacitor CS. By repeatedly performing the operation of storing in, only a part of the overflow charges can be stored in the overflow capacitor. In this way, if only a part of the overflow charge is stored in the overflow capacitor, the sensitivity to the overflow charge can be lowered, and consequently, the operating range of the image sensor can be extended. More specifically, if T and ts are defined as shown in the drawing, the sensitivity to the overflow charge may be expressed by Equation 1 below.

Overcharge Sensitivity 전하 (Cfd / (Cfd + Cs)) × (ts / T)

In the above equation, Cfd denotes the capacitance of the floating diffusion region, and Cs denotes the capacitance of the overflow capacitor CS. To widen the operating area of the image sensor, the sensitivity to the overflow charge should be lowered. As shown in Equation 1 and FIG. 4, by reducing the time ts storing the overflow charge in the total PD charge accumulation time, The sensitivity of the overflow charge can be easily lowered without increasing the capacity of the overflow capacitor CS.

In addition, by accumulating the overflow charge periodically, instead of accumulating the overflow charge only in one period of the PD charge accumulation period, the overflow charge accumulates more accurately even when the intensity of light incident in one PD charge accumulation period changes. The advantage is that you can.

In addition, when the period for storing the overflow charge is programmable, there is an advantage in that the sensitivity and the operating area can be changed as necessary.

In the second period P22, the first to third control signals CS1, CS2, and CS3 are turned off and the first and second transistors M1 and M2 are turned off, and the third transistor M3 is turned on. Is applied to reset the floating diffusion region FD. In this period, the fourth control signal CS4 is applied to the fifth transistor M5 so that the fifth transistor M5 is turned on, and the low light noise voltage VN1 corresponding to the charge located in the floating diffusion region FD is output. The low light noise voltage VN1 is used to remove a noise component included in the low light voltage VSN1 measured in the third period.

In the third period P23, the second transistor M2 and the third transistor M3 are turned off, and the first to third control signals CS1, CS2, and CS3 are turned on. Is applied, and the charge accumulated in the photodiode PD moves to the floating diffusion region FD. In this period, the fourth control signal CS4 is applied such that the fifth transistor M5 is turned on, and the low light voltage VSN1 corresponding to the charge located in the floating diffusion region FD is output. The low illuminance voltage VSN1 output in this manner has a voltage corresponding to the charge accumulated in the photodiode PD during the PD charge accumulation period.

In the fourth period P24, the first to second control signals CS1, CS2, and CS3 are turned off and the first and second transistors M1 and M2 are turned off, and the third transistor M3 is turned on. Is applied to reset the floating diffusion region FD. In this period, the fourth control signal CS4 is applied to the fifth transistor M5 to be in an on state, and the high illuminance noise voltage VN2 corresponding to the charge located in the floating diffusion region FD is output. The high illuminance noise voltage VN2 is used to remove a noise component included in the high illuminance voltage VSN2 measured in the fifth period.

In the fifth period P25, the first to third control signals CS1, CS2, and CS3 are turned off and the first and third transistors M1 and M3 are turned off, and the second transistor M2 is turned on. Is applied, and the overflow charge stored in the overflow capacitor CS moves to the floating diffusion region FD. In this period, the fourth control signal CS4 is applied such that the fifth transistor M5 is turned on, and the high illuminance voltage VSN2 corresponding to the charge located in the floating diffusion region FD is output. The high illuminance voltage VSN2 output in this manner is a voltage corresponding to the overflow charge stored in the overflow capacitor CS.

In the sixth period P26, the first to third control signals CS1, CS2, and CS3 are turned off and the first and third control signals CS1, CS2, and CS3 are turned on. Is applied to reset the overflow capacitor CS.

In the control method according to the present invention, in order to output the low illuminance voltage VSN1, the low illuminance noise voltage VN1, the high illuminance voltage VSN2 and the high illuminance noise voltage VN2, and to reset the overflow capacitor CS. 4 may be operated in the manner expressed in the second to sixth periods P2 to P6 of FIG. 4, but may be operated in the manner expressed in the second to fifth periods P2 to P5 of FIG. 2. Also, it operates in a different manner from FIGS. 2 and 4 to output the low light voltage VSN1, the low light noise voltage VN1, the high light voltage voltage VSN2, and the high light noise voltage VN2, and the overflow capacitor CS. May be reset.

5 is a flowchart illustrating a method of controlling a sample and a holder according to an embodiment of the present invention. More specifically, the low light voltage and the high light voltage output from the pixel circuit are not used as separate samples and holders, that is, the samples and holders used for sampling and holding the low light voltage are also used for sampling and holding the high light voltage. A flowchart showing a sample and holder control method capable of reducing the number of samples and holders. FIG. 6 schematically shows a sample and a holder 41 in which the control method of FIG. 5 is performed.

5 and 6, in a first step S10, the sample and the holder 41 sample the low light voltage VSN1.

In a second step S20, the low illuminance voltage VSN1 and the reference voltage Vref are compared. The reference voltage Vref is a voltage capable of determining whether or not an overflow has occurred. For example, the reference voltage Vref may have a value corresponding to the low illuminance voltage VSN1 immediately before the overflow occurs. When it is determined that the overflow has occurred as a result of the comparison, a third step S30 is performed to measure the high illuminance voltage VSN2, and when it is determined that the overflow has not occurred, the high illuminance voltage VSN2 is determined. Is unnecessary, so the fourth step S40 is performed.

In a third step S30, the high illuminance voltage VSN2 is sampled using the sample and the holder 41 used in the first step.

In a fourth step S40, the signals stored in the sample and the holder 41 are output to the analog-digital conversion circuit. If it is determined that the overflow does not occur in the second step S20, the fourth step S40 is performed immediately, and thus the low light voltage VSN1 is stored in the sample and the holder 41, and thus the low light voltage VSN1 will be output to the analog-to-digital conversion circuit. If it is determined that the overflow has occurred in the second step S20, since the fourth step S40 is performed after the third step S30 is performed, the sample and the holder 41 have a high illuminance voltage VSN2. Will be stored, and therefore the high illuminance voltage VSN2 will be output to the analog-to-digital conversion circuit. In a fourth step S40, a flag bit indicating whether the signal output to the analog-to-digital conversion circuit is the low illuminance voltage VSN1 or the high illuminance voltage VSN2 is also output.

7 is a flowchart illustrating a method of controlling a sample and a holder according to another embodiment of the present invention. More specifically, the low illuminance voltage, the low illuminance noise voltage, the high illuminance voltage, and the high illuminance noise voltage output from the pixel circuit, for example, the pixel circuit 10 represented in FIG. 1, do not use separate samples and holders, that is, low illuminance. Samples and holders used for sampling and holding voltages are also used for sampling and holding high illumination voltages, and samples and holders used for sampling and holding low illuminance noise voltages are also used for sampling and holding high illuminance noise voltages. And a sample and holder control method capable of reducing the number of holders. FIG. 8 schematically shows a sample and a holder 42 in which the control method of FIG. 7 is performed.

7 and 8, in a first step S11, the sample and holder 41 samples the low light voltage VSN1 and the low light noise voltage VN1.

In a second step S21, the low light voltage VS1 from which the noise corresponding to the difference between the low light voltage VSN1 and the low light noise voltage VN1 is removed is compared with the reference voltage Vref. The reference voltage is a voltage capable of determining whether or not an overflow has occurred. For example, the reference voltage may be a voltage slightly lower than the low light voltage VS1 from which the noise when the overflow occurs is removed. When it is determined that the overflow has occurred as a result of the comparison, a third step S31 is performed to measure the high illuminance voltage VSN2, and when it is determined that the overflow has not occurred, the high illuminance voltage VSN2 is determined. Is unnecessary, so the fourth step S41 is performed.

In a third step S31, the high illuminance voltage VSN2 and the high illuminance noise voltage VN2 are sampled using the sample and holder 41 used in the first step.

In a fourth step S41, the voltage corresponding to the difference between the two voltages stored in the sample and the holder is output to the analog-to-digital conversion circuit. If it is determined that the overflow does not occur in the second step (S21), the fourth step (S41) is performed immediately, so that the low light voltage VSN1 and the low light noise voltage VN1 are stored in the sample and holder 41. The low light voltage VS1 from which the noise is removed will be output to the analog-to-digital conversion circuit. If it is determined that the overflow has occurred in the second step S21, since the fourth step S41 is performed after the third step S31 is performed, the sample and the holder 41 have a high illuminance voltage VSN2. And the high illuminance noise voltage VS2 will be stored, and thus the noise canceled high illuminance voltage VS2 will be output to the analog-to-digital conversion circuit. In a fourth step S41, a flag bit indicating whether the signal output to the analog-to-digital conversion circuit is the low-noise voltage VS1 from which the noise is removed or the high-light voltage VS2 from which the noise is removed is also output.

FIG. 9 is a diagram illustrating an image sensor employing a method of controlling a sample and a holder described with reference to FIGS. 7 and 8, and FIG. 10 is a diagram for describing the ADC 80 of FIG. 9 in detail.

9 and 10, the image sensor includes a pixel array 20 including a plurality of pixel circuits, a row driver 30, a column driver 61, and an ADC 80.

The ADC 80 includes a correlated double sampling circuit (hereinafter simply referred to as a CDS circuit) 81, a CDS control circuit 82, a comparator 83, a first latch 84, a counter 85 and A second latch 86 is included.

The CDS circuit 81 may use any CDS circuit in general. The CDS circuit 81 is controlled by the third and fourth sampling signals SSR 'and SSD' output from the CDS control circuit 82. In the first period P31, the CDS circuit 81 samples the low light voltage VSN1 and the low light noise voltage VN1 transmitted from the pixel circuit 10 to remove the low light voltage corresponding to the difference between the two voltages. (VS1) is output to the comparator 83. In the second period, the CDS circuit 81 supplies the low light voltage VSN1 and the low light noise voltage VN1 when the flag bit OVS is input to the CDS control circuit 82 indicating that no overflow has occurred. And the flag bit OVS indicating that an overflow has occurred is input to the CDS control circuit 82, the high illuminance voltage VSN2 and the high illuminance noise voltage VN2 transmitted from the pixel circuit 10. ) And outputs the high illuminance voltage VS2 from which noise corresponding to the difference between the two voltages is removed, to the comparator 83.

The CDS control circuit 82 receives the first and second sampling signals SSR and SSD and the flag bits OVS, and outputs the third and fourth sampling signals SSR 'and SSD'. The CDS control circuit 82 may include two AND operators. In the first period P31, the CDS control circuit 82 outputs the first and second sampling signals SSR and SSD as the third and fourth sampling signals SSR 'and SSD' as they are. In the second period P32, when the CDS control circuit 82 receives the flag bit OVS indicating that an overflow has occurred, the CDS control circuit 82 receives the first and second sampling signals SSR and SSD as they are. The third and the third sampling signals SSR and SSD are output when the outputted as four sampling signals SSR 'and SSD' and a flag bit OVS indicating that no overflow has occurred. 4 Does not transfer to sampling signals SSR 'and SSD'.

The comparator 83 compares the ramp signal RAMP with the signal output from the CDS circuit and outputs the result. In the first period P31, the comparator 83 receives the ramp signal RAMP corresponding to the reference voltage Vref and the low light voltage VS1 from which the noise is removed, and any one of the two input voltages is further received. Outputs the result of judging whether it is large. If an overflow occurs, the low-noise voltage VS1 without noise will be greater than the reference voltage Vref, so a signal corresponding to '1' will be output. If no overflow occurs, the low-light voltage without noise is eliminated. Since VS1 will be smaller than the reference voltage Vref, a signal corresponding to '0' will be output. At this time, the output signal is a signal corresponding to the flag bit OVS and is stored in the first latch 84 controlled by the first latch control signal SP. In the second period P32, the comparator 83 receives the output of the ramp signal RAMP and the CDS circuit 81 corresponding to the ramp voltage at which the voltage value gradually increases, and any one of the two voltages received is input. Output the result of judging whether it is larger. At this time, if no overflow occurs, the CDS circuit 81 outputs the low-light voltage VS1 without noise, and if the overflow occurs, the CDS circuit 81 removes the high-light voltage VS2 with the noise removed. Will print

The first latch 84 stores a signal corresponding to the flag bit OVS output from the comparator 83. The stored flag bit OVS is input to the CDS control circuit 82 and output to the outside of the ADC 80.

The counter 85 performs a function of outputting a digital value corresponding to the value of the lamp voltage.

The second latch 86 receives a result of comparing the ramp voltage increasing gradually with the output of the CDS circuit 81 from the comparator 83 and inputs a digital value corresponding to the voltage value of the ramp voltage from the counter 85. Receive. The second latch 86 outputs a digital value at the instant when the ramp voltage becomes larger than the output of the CDS circuit 81.

The image sensor according to the embodiment of the present invention has such a configuration, and digitally converts any one of the low illumination voltage VS1 from which the noise is removed and the high illumination voltage VS2 from which the noise is removed and the flag bit OVS. )

FIG. 11 is a timing diagram for describing an operation of the image sensor illustrated in FIGS. 9 and 10, and in particular, when an overflow does not occur.

Referring to FIG. 11, in the first period P31, the CDS circuit 81 generates a low-light voltage by the first and third control signals CS1 and CS3 and the third and fourth sampling signals SSR 'and SSD'. VSN1) and the low light noise voltage VN1 are sampled to output the low light voltage VS1 from which the noise is removed. The low light voltage VS1 from which the noise is removed may be a voltage corresponding to the voltage difference between the low light voltage VSN1 and the low light noise voltage VN1. Since the overflow did not occur, the noise-reduced low light voltage VS1 has a voltage lower than the reference voltage Vref, so that the comparator 83 outputs a voltage corresponding to '0', and as a result, a flag bit ( OVS) becomes '0'.

In the second period P32, the pixel circuit 10 outputs the high illuminance voltage VNS2 and the high illuminance noise voltage VN2 by the second and third control signals CS2 and CS3. In addition, since the flag bit OVS is '0', although the first and second sampling signals SSR and SSD that are '1' are applied, the third and fourth sampling signals SSR 'and SSD' are not. It keeps being '0'. Accordingly, the CDS circuit 81 does not newly sample the high illuminance voltage VNS2 and the high illuminance noise voltage VN2 and maintains the previous low illuminance voltage VNS1 and the low illuminance noise voltage VN1. Accordingly, the comparator 83 outputs a result of comparing the ramp voltage gradually increasing and the low light voltage VS1 from which the noise is removed, and the second latch 86 of the comparator 83 of the values output from the counter 85. The value selected according to the output is output as a digital conversion value corresponding to the low light voltage VS1 from which the noise is removed.

The image sensor operates as described above and outputs a digital conversion value corresponding to the flag bit OVS having a value of '0' and the low light voltage VS1 from which the noise is removed when no overflow occurs.

FIG. 12 is a timing diagram for describing an operation of the image sensor illustrated in FIGS. 9 and 10, and particularly, when an overflow occurs.

Referring to FIG. 12, first, the CDS circuit 81 generates a low light voltage VSN1 and a low light noise voltage by the first and third control signals CS1 and CS3 and the third and fourth sampling signals SSR 'and SSD'. Sampling VN1) outputs the low-light voltage VS1 from which the noise is removed. The low light voltage VS1 from which the noise is removed may be a voltage corresponding to the voltage difference between the low light voltage VSN1 and the low light noise voltage VN1. Since the overflow has occurred, the low-light voltage VS1 from which the noise is removed has a voltage higher than the reference voltage Vref, so that the comparator 83 outputs a voltage corresponding to '1', and as a result, the flag bit OVS. Becomes '1'.

Thereafter, the pixel circuit 10 outputs the high illuminance voltage VNS2 and the high illuminance noise voltage VN2 according to the second and third control signals CS2 and CS3. In addition, since the flag bit OVS is '1', when the first and second sampling signals SSR and SSD are '1', the third and fourth sampling signals SSR and SSD are '1'. ') Is applied. Therefore, the CDS circuit 81 newly samples the high illuminance voltage VNS2 and the high illuminance noise voltage VN2 and outputs the high illuminance voltage VS2 from which the noise is removed. The high illuminance voltage VS2 from which the noise is removed may be a voltage corresponding to the voltage difference between the high illuminance voltage VSN2 and the high illuminance noise voltage VN2. Accordingly, the comparator 83 outputs a result of comparing the ramp voltage gradually increasing and the noise-removed high illuminance voltage VS2, and the second latch 86 compares the comparator 83 among the values output from the counter 85. And outputs the selected value as a digital conversion value corresponding to the noise-free high illuminance voltage VS2.

The image sensor operates as described above and, when an overflow occurs, outputs a digital value corresponding to the flag bit OVS having a value of '1' and the high illuminance voltage VS2 from which the noise is removed.

The method of controlling a pixel circuit for a CMOS image sensor according to the present invention has an advantage that the operating range can be increased without increasing the capacitance of the capacitor.

In addition, the control method of the pixel circuit for a CMOS image sensor according to the present invention does not accumulate the overflow charge only in one period of the PD charge accumulation period, but periodically accumulates the overflow charge, thereby preventing the incident light during one PD charge accumulation period. The advantage is that the overflow charge can be measured more accurately even when the intensity changes.

The control method and image sensor of the CMOS image sensor sample and holder according to the present invention has the advantage that it is possible to efficiently output a low light voltage and a high light voltage while reducing the number of samples and holders.

Claims (13)

In the method of controlling a pixel circuit for a CMOS image sensor, (a) resetting the floating diffusion region while keeping the first transistor connected between the photodiode and the floating diffusion region and the second transistor connected between the floating diffusion region and the overflow capacitor off; (b) maintaining the first transistor in an off state, maintaining the floating diffusion region in a reset-released state, and turning on the second transistor to receive overflow charges that overflow from the photodiode to the floating diffusion region; Storing in an overflow capacitor; (c) repeating steps (a) and (b) at least once; And (d) outputting a low illuminance voltage corresponding to the charge accumulated in the photodiode and a high illuminance voltage corresponding to the overflow charge stored in the overflow capacitor. According to claim 1, And a period in which step (a) is performed is longer than a period in which step (b) is performed. According to claim 1, And a period during which step (a) is performed and a period during step (b) are programmable. delete According to claim 1, Step (d) (d1) a low light noise voltage corresponding to a charge located in the floating diffusion region after resetting the floating diffusion region while the first and second transistors are kept in an off state, and the low light noise voltage is included in the low light voltage. Outputting the used noise component; (d2) controlling the first transistor to be in an on state to move charges accumulated in the photodiode to the floating diffusion region and to output the low light voltage corresponding to the charges transferred to the floating diffusion region; (d3) a high illuminance noise voltage corresponding to a charge located in the floating diffusion region after resetting the floating diffusion region in a state where the first and second transistors are kept in an off state, wherein the high illuminance noise voltage is the high illuminance; Outputting a noise component included in the voltage; (d4) controlling the second transistor to be in an on state and outputting the high illuminance voltage corresponding to the overflow charge stored in the capacitor; And (d5) maintaining the second transistor on and resetting the floating diffusion region and the overflow capacitor. (a) sampling the low light voltage output from the pixel circuit by the sample and holder circuit; (b) comparing the low light voltage with a reference voltage to determine whether an overflow has occurred; And (c) If it is determined that an overflow occurs as a result of performing step (b), the sample and holder circuit samples a high illuminance voltage, and the overflow does not occur as a result of performing step (b). If it is determined that the sample and holder circuits maintain a sampled low light voltage. The method of claim 6, Performed after step (c). and (d) outputting a flag bit indicating whether an overflow has occurred and a voltage stored in the sample and holder circuit. (a) sampling the low light voltage and low light noise voltage output from the pixel circuit by the sample and holder circuit; (b) determining whether an overflow has occurred by comparing the low light voltage from which noise corresponding to the difference between the low light voltage and the low light noise voltage is removed with a reference voltage; And (c) If it is determined that an overflow has occurred as a result of performing step (b), the sample and holder circuit samples the high illuminance voltage and the high illuminance noise voltage, and the result of performing the step (b) is over. And if it is determined that no flow has occurred, maintaining the sampled low light voltage and low light noise voltage in the sample and holder circuit. The method of claim 8, Performed after step (c). and (d) outputting a flag bit indicating whether an overflow has occurred and a voltage corresponding to a difference between two voltages stored in the sample and holder circuit. Outputs a low light voltage corresponding to the charge accumulated in the photodiode and a low light noise voltage corresponding to the noise component of the low light voltage in a first period, and a high light voltage corresponding to the overflow charge and the high light voltage in a second period. A pixel circuit for outputting a high illuminance noise voltage corresponding to the noise component of? And A digital conversion value corresponding to any one selected from among the noise-free low light voltage and the noise-free high light voltage according to the magnitude of the noise-free low light voltage, and the digital conversion value being the low-light voltage from which the noise is removed, and An analog-to-digital converter that outputs a flag bit indicating which of the high-noise voltages the noise is removed from, The low light voltage from which the noise is removed is a voltage corresponding to the difference between the low light voltage and the low light noise voltage, and the high light voltage from which the noise is removed is a voltage corresponding to the difference between the high light voltage and the high light noise voltage. Image sensor. The method of claim 10, The analog to digital converter In the first period, the difference between the two stored voltages is stored by storing the low illumination voltage and the low illumination noise voltage output from the pixel circuit, and in the second period, the two voltages stored in the first period according to the value of the flag bit A CDS circuit which maintains or newly stores the high illuminance voltage and the high illuminance noise voltage output from the pixel circuit and outputs a difference between the two stored voltages; A comparator for outputting the flag bit which is a result of comparing the output of the CDS circuit with a reference voltage in the first period, and a result of comparing the output of the CDS circuit with a ramp voltage in a second period; A counter for outputting a digital value corresponding to the ramp voltage; And And a latch configured to output, as the digital conversion value, a value selected according to a result of comparing the lamp voltage with the output of the CDS circuit output from the comparator among the digital values output from the counter. The method of claim 10, The pixel circuit The photodiode; A first transistor operating according to a first control signal and connected between the photodiode and the floating diffusion region; Overflow capacitors; A second transistor operating according to a second control signal and connected between the floating diffusion region and the overflow capacitor; A third transistor for resetting the floating diffusion region according to a third control signal; A fourth transistor that amplifies the voltage in the floating diffusion region; And And a fifth transistor configured to output the amplified floating diffusion region voltage according to a fourth control signal. The method of claim 12, The pixel circuit Maintaining the first and second transistors in an off state, maintaining the third transistors in an on state, and maintaining the first and third transistors in an off state and maintaining the second transistors in an on state. And after repeating at least two or more times, the low light voltage, the low light noise voltage, the high light voltage and the high light noise voltage.

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