KR100799908B1 - Interface module which connects memory - Google Patents

Abstract

An interface module connected to a memory is provided to minimize delay time when multimedia data is processed, and diversify usage of the memory by enabling an additional processor to store data received from an image sensor irrespective of memory use of a main controller. A clock generator(825) generates a clock for operating the memory(230). A multiplexer(835) receives data for transceiving by synchronizing with a received selection signal or the data delayed for the predetermined time by synchronizing with the clock, and selects and outputs one data. Each flip-flop(840,845) latches the data received from the multiplexer and outputs the latched data by synchronizing with the clock. A first I/O(Input/Output) pad(810) outputs the clock to the memory. A second I/O pad(815) receives the data from the memory by synchronizing with the clock. A third I/O pad(820) receives the clock output through the first I/O pad as feedback and outputs the received clock to the flip-flop.

Description

Interface module which connects memory

1 is a block diagram illustrating a structure in which a main processor and an additional processor share an additional memory coupled to an additional processor according to the related art.

2 is a block diagram illustrating a structure in which a main processor and an additional processor share a dual port memory coupled to each processor, according to an exemplary embodiment of the present invention.

3 is a block diagram illustrating an internal region of a dual port memory in accordance with a preferred embodiment of the present invention.

Fig. 4 is a block diagram of an interface when writing data to a conventional shared memory.

FIG. 5 is a timing diagram illustrating a relationship between a clock and a time when data is written to the shared memory corresponding to the interface of FIG. 4. FIG.

Fig. 6 is a block diagram of an interface when reading data into a conventional shared memory.

7 is a timing diagram illustrating a relationship between a clock and time according to an operation corresponding to data read when data is read into a shared memory corresponding to the interface of FIG. 6.

8 is a block diagram of an interface when reading data from a shared memory according to an embodiment of the present invention.

FIG. 9 is a timing diagram illustrating a relationship between a clock and an operation corresponding to data read when a data is read from a shared memory corresponding to the interface of FIG. 8. FIG.

<Explanation of symbols for the main parts of the drawings>

810: first input / output pad

815: second input / output pad

820: third input and output pad

825: clock generator

830: delay unit

835: Multiplexer

840: first flip-flop

845: second flip-flop

TECHNICAL FIELD The present invention relates to digital processing apparatus, and more particularly, to an interface module that can input and / or output data at high speed to a memory having a plurality of ports.

In general, a digital processing apparatus includes a plurality of processors. For example, a mobile communication terminal having a camera function includes a main processor for controlling the overall operation of the mobile communication terminal and an application processor (additional processor) for performing a predetermined function (eg, a camera function). do. Operation start / end and the like of the additional processor may be controlled by the main processor.

1 is a block diagram illustrating a structure in which a main processor and an additional processor share an additional memory coupled to an additional processor according to the related art. Hereinafter, it will be described on the assumption that the additional processor 120 is a multimedia processor (ie, a processor for controlling the image sensor 160 and processing multimedia data input from the image sensor 160).

Referring to FIG. 1, the main processor 110 includes a plurality of memory controllers (eg, the first memory controller 112 and the second memory controller 114). The main processor 110 is connected to the additional processor 120 through the main processor (MP) -AP (BUS) bus (BUS) by the operation of the first memory controller 112 and coupled to the additional processor 120. Data is written to the additional memory 140, or data stored in the additional memory 140 is read.

In addition, the main processor 110 is connected to the main memory 130 directly coupled to the main processor 110 through the MP-MM bus BUS by the operation of the second memory controller 114. Record or read stored data.

The additional processor 120 includes an interface 121, a controller 123, an image scaling 125, a multimedia processor 127, and a memory controller 129.

The additional processor 120 is coupled to the additional memory 140 having one port through an application memory bus (AP-AM). In addition, the additional processor 120 may be combined with the display unit 150 for displaying the processed multimedia data.

The interface 121 performs data transmission and reception between the main processor 110 and the additional processor 120. The additional processor 120 performs a corresponding processing operation when a control signal is received from the main processor 110 through the interface 121.

The controller 123 controls the operation of the additional processor 120 by a built-in program for driving the additional processor 120. For example, the controller 123 may control an operation of the additional processor 120, read data necessary for executing a program from the additional memory 140, and store the processed programming result in the additional memory 140. . That is, the controller 123 may access the additional memory 140 through the system bus 170 and the memory controller 129. In general, the controller 123 controls the operation of the additional processor 120 in response to a control signal received from the main processor 110. The controller 123 may be, for example, a microcontroller unit (MCU).

The image scaler 125 processes the data input from the image sensor 160 under the control of the controller 123 and converts the data into preset data. The image scaler 125 performs, for example, resizing an image, changing a color, and generating a smooth image by filtering. Data processed by the image scaler 125 is stored by the memory controller 129 in the additional memory 140 via the AP-AM bus.

The multimedia processor 127 reads image data stored in the additional memory 140 and compresses the image data into a predetermined format (for example, MPEG-4, JPEG, etc.) or performs a function to give a necessary effect. In addition, the multimedia processor 127 reads the compressed file received from the main processor 110 and stored in the additional memory 140, performs decoding, and outputs the decoded file to the display unit 150.

The memory controller 129 determines a priority when the internal components of the additional processor 120 request access to the additional memory 140 to control which component accesses the additional memory 140. Perform. In addition, when the main processor 110 and the additional processor 120 request access to the additional memory 140 at the same time, the memory controller 129 determines the priority so that any one processor may access the additional memory 140. Can be controlled.

As such, a conventional memory structure is a structure in which a plurality of processors and / or components access one memory through one bus. Thus, there are many time limits for using the memory of any additional processor 120 in the main processor 110.

For example, when playing an MPEG file, the main processor 110 should deliver the MPEG file stored in the connected main memory 130 or received in real time to the additional processor 120. Since the MPEG file is large in size, the MPEG file is first recorded in the additional memory 140 coupled to the additional processor 120, and a specific transport element (eg, the multimedia processing unit 127) of the additional processor 120 is needed when necessary. ) Reads the data, performs decoding, and delivers the data to the display unit 150.

Therefore, according to the conventional memory sharing structure, the larger the size of the data transferred between the processors, there is a lot of limitations in using the additional memory 150 connected to the additional processor 120. This is because each of the internal components included in the additional processor 120 must use the AP-AM bus connected to the additional memory 140 when performing the processing operation.

As described above, the conventional memory sharing structure has a problem that a large time delay occurs in the case of high performance, high quality image processing, and the like. In addition, there is a problem that the processing efficiency of the additional processor is reduced.

Accordingly, an object of the present invention for solving the above problems is to provide an interface module that can minimize the time delay in the case of multimedia data processing (for example, high-definition, high-performance image processing, audio data playback, and the like).

Another object of the present invention is to provide an interface module that can allow an additional processor to store data input from an image sensor regardless of memory use of the main processor, thereby diversifying the use of memory.

Yet another object of the present invention is to secure a timing margin in the memory controller when operating at a fast clock, thereby providing an interface module that can secure memory internal operation by improving memory clock paths. It is.

It is still another object of the present invention to provide an interface module in which a main processor and an additional processor can access a memory through each independent bus, and can quickly store and read data from the accessed memory.

Other objects of the present invention will be easily understood through the description of the following examples.

In order to achieve the above object, according to a preferred aspect of the present invention, there is provided an interface module for transmitting and receiving the combined memory and data.

According to an exemplary embodiment of the present invention, an interface module for transmitting and receiving data with a combined memory, the interface module comprising: a clock generator for outputting a clock for operating the memory; A multiplexer which receives data for transmission and reception and data delayed for a predetermined time corresponding to the input selection signal corresponding to the clock, and selects and outputs one of the multiplexers; And a flip-flop for latching data input from the multiplexer and outputting the latched data to correspond to the clock.

A first input / output pad outputting the clock to the memory; A second input / output pad configured to receive data from the memory in response to the clock; And a third input / output pad configured to receive the clock output through the first input / output pad as feedback and output the feedback to the flip-flop.

The data may be read from the memory and input through the second input / output pad corresponding to the clock.

The apparatus may further include a delay unit configured to delay the data by a predetermined time and output the data to the multiplexer.

The flip-flop may include a first flip-flop configured to receive data selectively outputted through the multiplexer, receive a clock fed back through the third input / output pad, and output the selected output data corresponding to the feedback clock; And a second flip-flop that latches data output through the first flip-flop, receives a clock output through the clock generator, and outputs the latched data corresponding to the clock.

The clock generation unit may include a phase locked loop (PLL) for generating and controlling the clock; And a divider for outputting the generated clock corresponding to a predetermined period.

According to another preferred aspect of the present invention, there is provided a digital processing apparatus comprising an interface module for transmitting and receiving data with a combined memory.

According to one preferred embodiment of the present invention, there is provided a digital processing apparatus comprising: a memory; And a processor including an interface module for transmitting and receiving data with the memory, wherein the interface module comprises: a clock generator configured to output a clock for operating the memory; A multiplexer which receives data for transmission and reception and data delayed for a predetermined time corresponding to the input selection signal corresponding to the clock, and selects and outputs one of the multiplexers; And a flip-flop for latching data input from the multiplexer and outputting the latched data to correspond to the clock.

The data may be read from the memory and input to the interface module corresponding to the clock.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted. In addition, in describing the present invention, when it is determined that the detailed description of the related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

FIG. 2 is a block diagram illustrating a structure in which a main processor and an additional processor share a dual port memory coupled to each processor, according to an exemplary embodiment of the present invention, and FIG. 3 is a block diagram of the preferred embodiment of the present invention. A block diagram illustrating an internal area of dual port memory. Hereinafter, assuming that the additional processor 220 is a multimedia processor, it will be described based on this. For example, the multimedia processor processes multimedia data input from the image sensor 240, processes the audio data stored in the main memory 230, transmits the audio data to the audio reproducing unit 260, and executes a 3D game. May perform one or more of the functions.

Referring to FIG. 2, the main processor 210 includes a plurality of memory controllers (eg, a first memory controller 212 and a second memory controller 214). The main processor 210 is coupled with the additional processor 220 through a main-processor (AP) -AP (BUS) bus (BUS) by the operation of the first memory controller 212 to transmit and receive data or control commands. can do.

In addition, the main processor 210 may access the shared memory 230 through the MP-SM bus via the operation of the second memory controller 214 to record data or to read stored data.

The additional processor 220 is coupled to the main processor 210 through a main processor (MP) -AP (application processor) bus. The additional processor 220 is coupled via a shared memory 230 having two ports and an AP-CM bus. In addition, the additional processor 220 processes the multimedia data input from the image sensor 240 and stores it in the shared memory 230, and processes the multimedia data stored in the shared memory 230 to output an output means (for example, a display unit). 250, the audio reproduction unit 260 may be output.

The additional processor 220 includes an MP interface 221, a controller 222, a multimedia processor 223, an image scaler 224, an audio interface 225, and a memory controller 226.

The MP interface 221 transmits and receives data between the main processor 210 coupled with the additional processor 220 through the MP-AP bus. For example, when the control signal is received from the main processor 210 through the MP interface 221, the additional processor 220 performs a corresponding processing operation.

The controller 222 controls the operation of the additional processor 220 by a built-in program for driving the additional processor 210. The operation of the additional processor 220 is controlled, data necessary for the execution of the program is read from the shared memory 230, and the processed result is stored in the shared memory 230 or output through the output means. The controller 222 may be, for example, a microcontroller unit (MCU).

The multimedia processor 223 reads data stored in the shared memory 230 through the memory controller 226 and performs a corresponding process. For example, if the read data is image data, the multimedia processing unit 223 compresses the data into a predetermined format (for example, MPEG-4 or JPEG) or gives a necessary image effect (for example, black and white processing). And the like. In addition, the multimedia processor 223 may perform decoding when the read data is audio data. The data processed by the multimedia processing unit 223 may be stored in the shared memory 230 or output through the output means (for example, the display unit 250 and the audio reproduction unit 260).

The image scaler 224 processes the data input from the image sensor 240 under the control of the controller 222 and converts the data into preset image data. For example, the image scaler 224 may perform image resizing, color change, smooth image generation by filtering, and the like. The data processed by the image scaler 224 may be stored in the shared memory 230 through the AP-CM bus allocated to the memory controller 226.

The image scaler 224 of the present invention may be just one embodiment of a component that stores multimedia data in the shared memory 230, and the present invention provides a multimedia data (e.g., image data and And / or audio data) may be universally applied to all multimedia data inputs that need to be stored in real time.

In addition, the multimedia processing unit 223 is just an embodiment of a component that processes the multimedia data stored in the shared memory 230, and processes the multimedia data stored in the shared memory 230 and returns to the shared memory 230. Obviously, the present invention can be universally applied to any multimedia data processing unit that stores, displays through the display unit 250, or transmits the data to the main processor 210.

The audio interface 225 is in charge of the interface with the audio reproducing unit 260. For example, the audio player 260 may include an audio codec, a speaker, and the like.

The memory controller 226 may input data input from the image sensor 240 and data input through internal components of the additional processor 220 (eg, the multimedia processor 223, the audio interface 225, etc.). The memory controller 226 stores internal components (eg, the multimedia processor 223, the audio interface 225, and the like) of the additional processor 220 in the shared memory 230. The allocation of the AP-SM bus is controlled to read data stored in the memory controller 226. The memory controller 226 may control the bus allocation under the control of the controller 222.

The shared memory 230 has two ports, one of which is coupled to the main processor 210 and the other to the additional processor 220. For example, the shared memory 230 may be combined with the main processor 210 through the MP-CM bus and may be combined with the additional processor 220 through the AP-CM bus. In this case, the shared memory 230 may access the entire region through any of two ports due to the characteristics of the dual port memory, and the internal region may be divided so that only limited access is possible through each port.

For example, as illustrated in FIG. 3, the shared memory 230 may be divided into three regions, each of which may access a predetermined region (eg, the first access port 310, The second access port 335 may be included, and may include an internal controller 315 for controlling access to an arbitrary area through each port.

Referring to FIG. 3, the shared memory 230 may include a first region 320 accessible only to the main processor 210, a third region 330 accessible only to the additional processor 220, and a main processor 210. ) And a second area 325 that can be jointly accessed by the additional processor 220.

The first access port 310 is coupled to the main processor 210, and the second access port 335 is coupled to the additional processor 220 to provide a path for accessing a predetermined area. Here, each of the ports (eg, the first access port 310 and the second access port 335) may include data signals Data_A and Data_B, address signals Addr_A and Addr_B, and control signals Ctrl-A, Ctrl-B) and pins for clock signals CLK-A and CLK-B, respectively, which are combined with the main processor 210 or the additional processor 220 to provide data (e.g., data signals, address signals). Etc.) can be transmitted and received.

The internal controller 315 accesses an area when the main processor 210 or the additional processor 220 accesses an area through either the first access port 310 or the second access port 335. It performs the function to control so that it can be done.

In addition, when the main processor 210 and the additional processor 220 approach a region commonly used (for example, the second region 325), the internal controller 315 may access the common region (that is, the second region). Until the access of 325 is completed, it may be controlled to prevent access to the common area (ie, the second area 325) by another processor.

For example, assume that the main processor 210 accesses the second area 325 of the shared memory 230 through the MP-SM bus to store data. The additional processor 220 may then access the shared memory 230 through the AP-SM bus. However, in the memory controller 226, the additional processor 220 may maintain the corresponding area (ie, the second area 325) until the main processor 210 completes storing data in the second area 320 of the shared memory 230. ) Can be controlled from access. That is, the shared memory 230 may simultaneously access the main processor 210 or the additional processor 220 through respective ports provided in a plurality of areas. However, for memory consistency, the memory controller 226 may maintain the memory controller 226 until the region (eg, the second region 325) accessed by either the main processor 210 or the additional processor 220 is released. You can control access to an area. The memory controller 226 may prevent an error due to a data collision caused by simultaneous access to an arbitrary area by the main processor 210 or the additional processor 220 of the shared memory 230.

Hereinafter, the internal flip-flop corresponds to a fast clock output by the memory controller 226 or the second memory controller 214 to control the shared memory 230 for writing and / or reading data into the shared memory 230. Stable output of the data after latching will be described with reference to the accompanying drawings.

As described above, the main processor 210 or the additional processor 220 is coupled to the shared memory via each bus (e.g., MP-SM bus, AP-SM bus, etc.) to write or read each data. I can ship it.

First, for convenience of understanding and description, a clock and time relationship according to a conventional interface will be briefly described with reference to FIGS. 4 to 7 when writing or reading data to the shared memory 230.

4 is a block diagram of an interface in the case of writing data in a conventional shared memory, and FIG. 5 is a timing diagram illustrating a relationship between a clock and time when data is written in the shared memory corresponding to the interface of FIG. 4. In the following description, the interface coupled to the shared memory 230 may be the memory controller 226 or the second memory controller 214. However, for convenience of description, it is assumed that the interface is coupled to the memory controller 226.

Here, the clock generator 410 generates a clock signal for the operation of each component of the memory controller 226 (eg, the D flip-flop 420) or the shared memory 230, or at predetermined time periods. It includes a PLL and a divider that adjusts and outputs a clock period. Here, since the detailed operation of the PLL and the divider is obvious to those skilled in the art, a detailed description thereof will be omitted and will be collectively described as a clock generator for convenience of understanding and description.

In addition, the data generator 415 may receive data from the outside (for example, the multimedia processor 223, the image sensor 240, or the like), or may execute the shared memory 230 by an arbitrary operation inside the memory controller 226. This function creates and outputs the data that needs to be recorded in.

Referring to FIG. 4, the clock generator 410 may use a clock (hereinafter, referred to as a “memory clock”) to operate the shared memory 230 to write data to the shared memory 230 at a predetermined time. SDR_CLK) "is output to the D flip-flop 420. Here, the D flip-flop 420 may be latched by receiving data output through the data generator 415.

In addition, the memory clock SDR_CLK output through the clock generator 420 is output to the shared memory 230 through the second input / output pad 430.

The D flip-flop 420 outputs data to the first input / output pad 425 corresponding to the input memory clock SDR_CLK. In the process of transferring data to the shared memory 230 through the first input / output pad 425, a time delay occurs by the first input / output pad 425. However, since the time delay generated by the first input / output pad 425 or the second input / output pad 430 is the same, the description thereof will be omitted.

The shared memory 230 receives data to be written through the first input / output pad 425, and receives a clock for controlling operation according to data writing of the shared memory 230 through the second input / output pad 430. The input data corresponding to the input clock can be recorded in an arbitrary area.

Referring to 510 and 515 of FIG. 5, it is illustrated that the data generator 415 outputs data corresponding to the memory clock SDR_CLK output through the clock generator 410. Since this is obvious to those skilled in the art, a detailed description thereof will be omitted.

In the present specification, a time at which the data output from the data generator 415 is transmitted to the D flip-flop 420 will be referred to as a “first time t1”, and the data output from the D flip-flop 420 is generated. The time taken to transfer to the first input / output pad 425 will be referred to as "second time t2". The time taken for the memory clock SDR_CLK output through the clock generator 410 to be transferred to the second input / output pad 430 will be referred to as a “third time t3”.

Referring to 520, the memory clock SDR_CLK is delivered to the shared memory 230 after being delayed by a third time, and the data is delayed by the time t1 + t2 that is the sum of the first time and the second time. Is delivered). Of course, the first time, the second time, and the third time may all be several nanoseconds.

That is, the shared memory 230 writes data DATA_OUT input through the second input / output pad 430 corresponding to the memory clock SDR_CLK_OUT input through the first input / output pad 425. In the present specification, it is assumed that each component and the shared memory 230 are operated corresponding to the positive operation of the clock.

FIG. 6 is a block diagram of an interface when reading data into a conventional shared memory, and FIG. 7 corresponds to a clock and data reading when reading data into the shared memory according to the interface according to FIG. 6. A timing diagram illustrating a relationship of time according to an operation. Hereinafter, it will be described on the assumption that the interface is the memory controller 226.

Referring to FIG. 6, the clock generator 625 may include a memory clock for controlling the operation of the shared memory 230 to read data from the shared memory 230 (hereinafter, referred to as a “memory clock SDR_CLK”). Is output to the shared memory 230 through the first input / output pad 610.

Referring to 710 and 715 of FIG. 7, the shared memory 230 corresponds to the memory clock SDR_CLK_OUT input through the first input / output pad 610, and the shared memory 230 stores the stored data (ie, the memory controller 226). Read data) is inputted through the third input / output pad 620. As shown in FIG. 715, since the shared memory 230 takes a predetermined time to access the area in which the read data is stored, it is delayed by a data access time t4 such as 715 corresponding to the memory clock SDR_CLK_OUT. The data is read and transferred to the memory controller 226.

Referring back to FIG. 6, the memory clock SDR_CLK_OUT output through the first input / output pad 610 is fed back and input through the second input / output pad 615 to be transmitted to the delay unit 630 or the multiplexer 635. . The delay unit 630 delays the clock FB_CLK input through the second input / output pad 615 for a predetermined time and outputs the delayed signal to the multiplexer 635. In response, the multiplexer 635 selects one of a clock input delayed for a predetermined time through the delay unit 630 and a clock input through the second input / output pad 615, and transfers it to the first flip-flop 640. do. That is, as described above, the multiplexer 635 selectively outputs a clock corresponding to the data input to the first flip-flop 640.

The first flip-flop 640 outputs data input through the third input / output pad 620 corresponding to the clock FB_DLY_CLK input through the multiplexer 635.

Referring to 720 and 725 of FIG. 7, since the feedback clock is transmitted to two places (ie, the delay unit 630 and the multiplexer 635), the output loading becomes large.

Referring to FIG. 6 again, the second flip-flop 645 receives data from the first flip-flop 640 and latches the data, and then latches the data corresponding to the clock input through the clock generator 625. Outputs Here, when the time difference between the clock FB_DLY_CLK output through the multiplexer 635 and the clock SDR_CLK_OUT output through the clock generator 625 is shortened, the second flip-flop 645 becomes the first flip-flop 640. There is a problem in latching the output data.

FIG. 8 is a block diagram of an interface when reading data from a shared memory according to an embodiment of the present invention, and FIG. 9 is a clock when reading data from a shared memory corresponding to the interface of FIG. 8. And a timing diagram illustrating a relationship between time according to an operation corresponding to data reading. The interface may be some components included in the memory controller 226 or the second memory controller 214, and the following description will be mainly given assuming that the memory controller 226 is the memory controller 226.

Referring to FIG. 8, in order to read data from the shared memory 230, the clock generator 825 transfers the memory clock to the shared memory 230 through the first input / output pad 810. As described above, the shared memory 230 reads out data stored corresponding to the memory clock SDR_CLK_OUT input through the first input / output pad 810 and outputs the stored data to the third input / output pad 820.

The data DATA_IN input through the third input / output pad 820 is transferred to the delay unit 830 and the multiplexer 835. Here, the delay unit 830 delays the input data for a predetermined time and outputs the data to the multiplexer 835. The multiplexer 835 selects one of the data input delayed from the delay unit 830 and the data input through the third input / output pad 820 and outputs the selected flip-flop 840. Here, the multiplexer 835 may select one of two pieces of data that are preset or input in correspondence with a selection signal input from internal components (eg, the controller 222) of the additional processor 220. You can print

 The memory clock output through the first input / output pad 810 is fed back through the second input / output pad 815 and input to the first flip-flop 840.

The first flip-flop 840 receives the clock fed back through the second input / output pad 815 and outputs the data input through the multiplexer 835 to the second flip-flop 845 accordingly. Data output through the first flip-flop 840 will be referred to as "FF_OUT" for convenience.

The second flip-flop 845 latches the data FF_OUT input through the first flip-flop 840 and then outputs the latched data corresponding to the memory clock SDR_CLK input from the clock generator 825. .

As a result, the second flip-flop 845 has an advantage of increasing the time for latching the data input from the first flip-flop 840 to more stably output the data.

Unlike the prior art, the feedback clock is output directly to the first flip-flop 840, and the data input through the shared memory 230 is selectively (eg, preset or internal components of the additional processor 220). Outputting the data through the first flip-flop 840 to the second flip-flop 845 by speeding up the output of the data through the first flip-flop 840. Sufficient time for latching data can be secured (see 930 and 935 of FIG. 9).

As described above, the present invention provides a user terminal capable of high-speed data transmission and a method thereof, thereby minimizing time delay in the case of multimedia data processing (for example, high quality, high performance image processing, audio data reproduction, and the like). It has an effect.

In addition, the present invention may allow the additional processor to store data input from the image sensor regardless of the memory usage of the main processor, thereby diversifying the use of the memory.

In addition, the present invention is difficult to secure the timing margin (timing margin) of the memory interface when operating at a fast clock (clock) has the effect of ensuring the stability of the internal operation of the interface by improving the clock path.

In addition, another object of the present invention is that the main processor and the additional processor can access the memory through each independent bus, there is an effect that can be quickly stored and read data into the accessed memory.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Claims (8)

In the interface module for transmitting and receiving the combined memory and data, A clock generator for outputting a clock for operating the memory; A multiplexer which receives data for transmission and reception and data delayed for a predetermined time corresponding to the input selection signal corresponding to the clock, and selects and outputs one of the multiplexers; And And a flip-flop for latching data input from the multiplexer and outputting the latched data to correspond to the clock. The method of claim 1, A first input / output pad outputting the clock to the memory; A second input / output pad configured to receive data from the memory in response to the clock; And And a third input / output pad configured to receive the clock output through the first input / output pad as feedback and output the feedback to the flip-flop. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 2, The method of claim 1, And a delay unit configured to delay the data by a predetermined time and output the delayed data to the multiplexer. The method of claim 2, The flip flop, A first flip-flop configured to receive data selectively outputted through the multiplexer, receive a clock fed back through the third input / output pad, and output the selected output data corresponding to the feedback clock; And And a second flip-flop for latching data output through the first flip-flop, receiving a clock output through the clock generator, and outputting the latched data corresponding to the clock. . Claim 6 was abandoned when the registration fee was paid. The method of claim 1, A phase locked loop (PLL) for generating and controlling the clock; And And a divider for outputting the generated clock in correspondence with a predetermined period. In the digital processing device, Memory; And Including a processor including an interface module for transmitting and receiving data with the memory, The interface module, A clock generator for outputting a clock for operating the memory; A multiplexer which receives data for transmission and reception and data delayed for a predetermined time corresponding to the input selection signal in response to the clock, and selects and outputs one of the multiplexers; And And a flip-flop for latching data input from the multiplexer and outputting the latched data to correspond to the clock. The method of claim 7, wherein And the data is read from the memory and input to the interface module corresponding to the clock.

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