KR100798775B1 - Method for fabricating semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to prevent movement of a void toward a gate dielectric by using a gate conductive layer having a discontinuous interface. A semiconductor substrate(101) is etched to form a bulb-type recess pattern comprised of a neck pattern(104) and a bulb pattern(106). A gate dielectric(107) is formed on the semiconductor substrate including the bulb-type recess pattern. A gate conductive layer is formed on the gate dielectric to gap-fill the bulb-type recess pattern. The gate conductive layer includes a discontinuous interface by sequentially performing a first deposition, a stoppage of source gas of process gases in the state of keeping a process temperature, and a second deposition. The process gases include purge gas, doping gas, and the source gas. The doping gas is not supplied when the stoppage of the source gas is occurred.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

1 shows a bulb type recess transistor;

2A and 2B are cross-sectional views and electron micrographs showing portions of a bulb type recess transistor without a gate polysilicon film on an upper surface of the gate insulating film.

3A to 3J illustrate a method of manufacturing a bulb type recess transistor according to an exemplary embodiment of the present invention.

4A and 4B are timing diagrams showing the process environment of FIGS. 3I to 3J in time.

5A and 5B are electron micrographs of bulb-type recess transistors fabricated in the process environment of FIGS. 4A and 4B, respectively.

Explanation of symbols on the main parts of the drawings

101 semiconductor substrate 107 gate insulating film

108: first gate conductive film 109: second gate conductive film

110: void

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a process of forming a bulb type recess transistor in a semiconductor device manufacturing process.

As the degree of integration of semiconductor memory devices increases, the conventional two-dimensional transistor structure is approaching various aspects, for example, in terms of current drivability and data retention time. In particular, in the case of a low power device, the existing two-dimensional transistor structure cannot satisfy the required data storage time.

Meanwhile, a DRAM device, which is a representative semiconductor memory device, is required to manufacture a memory array transistor having a design rule of sub-100 nm or less as the degree of integration increases. Transistors of sub-100 nm or less show very low threshold voltage (Vth) characteristics due to problems such as short channel effects, and thus, data storage time (similarly, refresh time ( refresh time). Recently, a recessed channel array transistor (RCAT) device has been developed to solve this problem. Unlike conventional planar transistors, a recessed channel array transistor (RCAT) device has a very long channel length because of a very long data storage time. It has the merit of showing characteristics.

Recently, in order to obtain better data storage time and current characteristics than the recess transistor, a method of increasing the length of a recessed channel has been proposed.

In response thereto, a bulb-type recessed transistor array (BRCAT) is further etched by a ball shape under the recess region of the recess transistor. As a diagram supporting this, FIG. 1 is a view showing such a bulb type recess transistor.

However, in the case of the bulb type recess transistor, when the gate polysilicon layer 13 is formed, the gate polysilicon layer 13 is filled in the ball because the ball size is larger than the width of the recess region. As a result, voids (14, void) are formed in the center of the ball. In addition, voids 15 are generated in the gate polysilicon film 13 together with the voids 14.

At this time, the subsequent high temperature heat treatment process-the heat treatment process at this time corresponds to a heat treatment process, such as a curing process of a subsequent layer (layer), or a heat treatment process after ion implantation. Re-crystallization of the gate polysilicon film 13 causes the voids 14 to move toward the gate insulating film 12, where portions of the gate polysilicon film 13 that do not have the gate polysilicon film 13 are observed. 2A and 2B are cross-sectional views and electron micrographs showing portions of the bulb type recess transistor without the gate polysilicon layer 13 on the upper surface of the gate insulating layer 12.

The portion 16 without the gate polysilicon layer 13 on the upper surface of the gate insulating layer 12 reduces the channel capacitance to reduce the drain current, as well as the threshold. It acts as a factor that makes voltage uncontrollable.

The present invention has been proposed to solve the above problems of the prior art, and a first object of the present invention is to provide a method for manufacturing a semiconductor device which prevents movement of voids formed during manufacturing of a bulb type recess transistor.

Another object of the present invention is to provide a method of manufacturing a semiconductor device that solves the problems of reducing the operating current and difficulty of controlling the threshold voltage of a bulb type recess transistor.

According to an aspect of the present invention for achieving the above object, forming a bulb-shaped recess pattern consisting of a neck pattern and a bulb pattern by etching the semiconductor substrate, on the semiconductor substrate including the bulb-type recess pattern Forming a gate insulating film, and filling the bulb-type recess pattern formed on the gate insulating film, and stopping supply of source gas in the process gas and performing secondary deposition in a state of maintaining the first deposition and the process temperature; To provide a method for manufacturing a semiconductor device comprising the step of forming a gate conductive film having a discontinuous interface.

 The present invention is a method of manufacturing a bulb type recess transistor to prevent the voids generated during deposition of the gate polysilicon film to the upper surface of the gate insulating film.

In the high temperature heat treatment process, the cause of the internal voids of the bulb pattern of the bulb-type recess transistor is moved to the upper surface of the gate insulating film. Vacancy dissolved in the equilibrium state in the gate polysilicon film grows, or the gate insulating film Because it moves to.

Accordingly, the present invention forms a stable gate polysilicon film surface by temporarily depositing the first gate polysilicon film to a thickness before the deposition voids generated by closing the inlet of the neck pattern are formed, and then temporarily stopping the deposition. The second gate polysilicon film is then deposited to bury the ball.

At this time, the gate polysilicon film surface becomes a discontinuous interface due to the temporary stop of deposition of the gate polysilicon film-the supply of the source gas of the polysilicon film, and the gate polysilicon film is heat-treated and crystallized by maintaining the process temperature. At this time, the void disappears due to crystallization and thus serves as a barrier for the voids generated during deposition in the ball to move to the upper surface of the gate insulating film during the subsequent heat treatment process.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3A to 3J illustrate a method of manufacturing a bulb type recess transistor according to an exemplary embodiment of the present invention.

First, referring to FIG. 3A, a hard mask 102 is formed on a substrate 101 on which an isolation layer is formed. In this case, the hard mask 102 is a film used as an etch barrier for forming a neck pattern for forming a bulb-type transistor, and generally uses a nitrided insulating film.

Next, referring to FIG. 3B, a photosensitive film pattern 103 is formed on the hard mask 102. In this case, the photoresist pattern 103 may have a shape in which an upper portion of the recess formation region of the substrate 102 is opened through an exposure process and an etching process.

Next, referring to FIG. 3C, the hard mask 102 is etched using the photoresist pattern 103 as an etching barrier.

Subsequently, the neck pattern 104 is formed by etching the substrate 101 using the photoresist pattern 103 and the etched hard mask 102 as an etch barrier. In this case, after removing the photoresist pattern 103, the neck pattern 104 may be formed using only the hard mask 102 as an etching barrier.

And it is preferable that the width | variety of the neck pattern 104 is 100-2000 micrometers, and the depth is 1000-3000 micrometers.

Subsequently, when the neck pattern 104 is formed using the photoresist pattern 103 as an etch barrier, the photoresist pattern 103 is removed after the neck pattern 104 is formed.

Next, referring to FIG. 3D, a dielectric film 105 for spacers is formed on a resultant product on which the neck pattern 104 is formed.

In this case, the spacer dielectric film 105 is a protective film for protecting the sidewall of the neck pattern 104 when forming the bulb pattern, and is generally formed of any one of SiO ₂ , Si ₃ N ₄ , and SiON. The thickness of the spacer dielectric film 105 is preferably 30 to 150 kPa.

Next, referring to FIG. 3E, a vertical etch process is performed on the resultant formed dielectric layer 105 for spacers.

The vertical etching process is a process for removing the spacer dielectric layer 105 formed on the bottom surface of the neck pattern 104.

Next, referring to FIG. 3F, an isotropic etch is performed on the substrate 101 when the exposed neck pattern 104 is bottomed.

This is a basic process for forming a bulb type recess transistor, and is a process for forming the bulb pattern 106 under the neck pattern 104.

At this time, the bulb pattern 106 has a radius of 110 ~ 4000Å should be wider than the width of the neck pattern 104.

Next, referring to FIG. 3G, wet cleaning of the resultant product of the bulb pattern 106 is performed.

This is a process for removing the spacer dielectric film 105 and the hard mask 102 remaining on the substrate 101.

Next, referring to FIG. 3H, the gate insulating layer 107 is formed on the resultant of the cleaning.

In this case, the gate insulating layer 107 may be formed of any one of SiO ₂ , SiON, Si ₃ N ₄ , Hf silicate (HfSiO), and Hf silioxynitride (HfSiON).

Next, referring to FIGS. 3I to 3K, the first gate conductive layer 108 is first deposited on the resultant formed with the gate insulating layer 107.

The first gate conductive film 108 is a polysilicon film, and is formed to such an extent that the inlet of the neck pattern 104 is not closed, that is, has a thickness at which no void is formed.

In this case, the thickness of the first gate conductive layer 108 may be smaller than 1/2 of the width of the neck pattern 104.

Thereafter, the second gate conductive layer 109 filling the bulb pattern 106 and the neck pattern 104 is deposited through a temporary stop of deposition.

Here, the second gate conductive film 109 is also a polysilicon film like the first gate conductive film 108, and the reason why the gate conductive films 108 and 109 are divided into the first and second portions is for convenience of explanation. In addition, the deposition is performed by the deposition of the primary gate conductive film 108 and the deposition of the secondary gate conductive film 109.

A general bulb type recess transistor is manufactured by forming a neck pattern 104 and a bulb pattern 106 and forming a gate conductive film that completely fills them. However, in the present invention, in order to solve the existing problem, a temporary deposition stop step is performed when forming the gate conductive film.

In the deposition stop step, the deposition process of the first gate conductive layer 108 is performed at the same process temperature. As a result, the first gate conductive layer 108 is annealed and crystallized.

According to the present invention, even when the void 110 is generated when the second gate insulating layer 109 is formed, it is prevented from moving to the gate insulating layer 107 due to the crystallization of the first gate conductive layer 108. In addition, a discontinuous interface is formed between the first gate conductive layer 108 and the second gate conductive layer 109 due to the step of stopping the temporary deposition. This discontinuous interface is also prevented from moving to the void 110 gate insulating film 107.

Here, the process temperature of the deposition process of the first and second gate conductive films 108 and 109 is preferably performed in an amorphous or crystalline structure at 450 to 650 ° C. In addition, the process temperature is 450 ~ 650 ℃ even in the temporary deposition stop step.

Then, the first and second gate conductive film (108, 109) is a (PH ₃₎ in-situ doped poly can be used a silicon film (in-situ P doped poly silicon), wherein the phosphorous is 1E19 / cm ³ It is preferable that it is -5E20 / cm <^3> .

Alternatively, the first and second gate conductive films 108 and 109 may use a boron (B ₂ H ₆ ) in-situ doped poly silicon film, wherein the concentration of boron is 1E19. that the / cm ³ ~ 5E20 / cm ³ is preferred.

The first and second gate conductive films 108 and 109 may form a p-type polysilicon film or an n-type polysilicon film through a subsequent boron or phosphorus ion implantation process after the polysilicon film is formed. At this time, the concentration of ion implantation of boron or phosphorus is the same concentration as in-situ doping.

Hereinafter, for convenience of description, the first and second gate conductive layers 108 and 109 will be described as being in-situ.

Then, the temporary deposition stop step is performed by blocking the flow of the source gas SiH ₄ gas and the doping gas PH ₃ gas or B ₂ H ₆ gas in the chamber. Alternatively, only SiH ₄ gas, which is the source gas, may block the flow.

As described above, the formation of the first gate conductive film 108 → the temporary stop of deposition → the formation of the second gate conductive film 109 is performed in the same chamber, and thus, in the manufacturing process of the bulb type recess transistors of FIGS. 3I to 3K. The temperature and the gas flow are described below.

4A and 4B are timing diagrams illustrating the process environment of FIGS. 3I through 3K according to time. For better understanding of the description, reference numerals of FIGS. 3A to 3K will be described.

Referring to FIGS. 4A and 4B, T1 means a time for inserting a substrate advanced to FIG. 3H into a chamber, and T2 means a time when a process is started and a temperature is raised to a target process temperature.

Subsequently, T3 starts to inject a purge gas (N ₂ ), a source gas and a doping gas to form a polysilicon film in which phosphorus (PH ₃ ) or boron (B ₂ H ₆ ) is infiltrated. Means. That is, the time when the first gate conductive layer 108 is formed.

Subsequently, T4 is a time for temporarily stopping the deposition, which suspends the deposition process by blocking the source gas (SiH4) and the doping gas (PH ₃ or B ₂ H ₆ ) of the polysilicon film into the chamber. This corresponds to FIG. 4A. In FIG. 4B, only the supply of the source gas (SiH ₄ ) of the polysilicon film is interrupted to suspend the deposition process.

Subsequently, T5 refers to a time for forming a polysilicon film by injecting a source gas (SiH4) and a doping gas (PH ₃ or B ₂ H ₆ ) into the chamber. That is, it means the time for forming the second gate conductive film 109.

Thereafter, T6 means the process is over.

Here, T3 is a relatively short process time to prevent the inlet of the neck pattern 104 to form a void, T4 is to maintain the time to sufficiently heat the first gate conductive film 108 formed in T3 , T5 is a process for a relatively long time to ensure that the bulb pattern 106 and the neck pattern 104 is securely embedded.

5A and 5B are electron microscope (SEM) photographs of bulb-type recess transistors fabricated in the process environment of FIGS. 4A and 4B, respectively. At this time, in order to help the understanding of the description will be described with reference to the reference numerals of FIGS. 3A to 3J.

5A and 5B, it can be seen that voids generated when the second gate conductive layer 109 is formed do not move to the surface of the gate insulating layer 107 even after performing a subsequent process such as a heat treatment process.

In summary, the inlet of the neck pattern 104 is closed and the first gate conduction film is temporarily deposited after the first gate conduction film 108 is deposited to a thickness before the void 110 is formed. The film 108 is crystallized. Thereafter, the second gate conductive layer 109 is deposited to fill the bulb pattern 106 and the neck pattern 104. At this time, an interface between the first gate conductive film 108 and the second gate conductive film 109 becomes a discontinuous interface.

As a result, although the voids 110 are generated when the second gate conductive layer 109 is formed, the voids have a discontinuous interface, and the voids 110 do not move to the gate insulating layer 107 due to the crystallized first gate conductive layer 108. can not do it.

Even if the void 110 moves, the movement range is the boundary between the first gate conductive film 108 and the second gate conductive film-the discontinuous interface-so that the void 110 approaches the gate insulating film 107. To prevent them.
Referring to the difference between the present invention and the method of forming the gate conductive film by performing two or more deposition processes as the prior art as follows.
First, the prior art forms a neck pattern and a bulb pattern, forms a primary gate conductive film so that voids do not form in the bulb pattern, and then forms a secondary gate conductive film to fill the bulb pattern and the neck pattern. This seems to be the same as the present invention, but the prior art does not maintain the process temperature between the formation of the first gate conductive film and the formation of the secondary gate conductive film, and thus the primary gate conductive film cannot be crystallized.
However, the present invention maintains the process temperature between the formation of the primary gate conductive film and the formation of the secondary gate conductive film to crystallize the primary gate conductive film. Therefore, crystallization of the primary gate conductive film creates a discontinuous interface between the primary gate electrode and the secondary gate conductive film, thereby preventing subsequent movement of voids.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

delete

As described above, the present invention prevents the voids formed when manufacturing the bulb type recess transistor from moving toward the gate insulating layer, thereby solving problems such as a reduction in operating current and difficulty in controlling the threshold voltage.

Therefore, the effect which can ensure the stability and reliability of a semiconductor element can be acquired.

Claims (9)

Etching the semiconductor substrate to form a bulb-type recess pattern formed of a neck pattern and a bulb pattern; Forming a gate insulating film on the semiconductor substrate including the bulb type recess pattern; And A gate conduction having a discontinuous interface formed on the gate insulating layer and filling the bulb-type recess pattern, and stopping supply of source gas in the process gas and performing secondary deposition in order while maintaining the primary deposition and the process temperature. Forming film Method for manufacturing a semiconductor device comprising a. delete The method of claim 1, Forming the gate conductive film, Depositing a polysilicon film for a gate coating film by injecting a process gas to a thickness at which the inlet of the neck pattern is not closed; Stopping the source gas of the polysilicon film in the process gas; And Depositing a polysilicon film for a gate conductive film filling the neck pattern and the bulb pattern Method for manufacturing a semiconductor device comprising a. The method of claim 3, The process gas includes a purge gas, a doping gas and a source gas manufacturing method of a semiconductor device. The method of claim 4, wherein And when the supply of the source gas is stopped, the supply of the doping gas is also stopped. The method of claim 3, The process temperature of the step of forming the gate conductive film is a manufacturing method of a semiconductor device, characterized in that 450 ~ 650 ℃. The method of claim 1, The gate conducting film is a method of manufacturing a semiconductor device, characterized in that the in-situ doped polysilicon film or boron in-situ doped polysilicon film. The method of claim 7, wherein The concentration of phosphorus is 1E19 / cm ³ ~ 5E20 / cm ³ The concentration of boron is 1E19 / cm ³ ~ 5E20 / cm ^{3 The} method of manufacturing a semiconductor device. The method of claim 3, And depositing a polysilicon film for a gate conductive film to a thickness at which the inlet of the neck pattern is not closed, wherein the thickness of the polysilicon film is less than half of the width of the neck pattern.

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